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Jean-Luc Danger
2010 – today
- 2013
[c68]Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger: Stochastic Model of a Metastability-Based True Random Number Generator. TRUST 2013: 92-105- 2012
- [j6]Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography. Int. J. Reconfig. Comp. 2012 (2012)
- [c67]Houssem Maghrebi, Claude Carlet, Sylvain Guilley, Jean-Luc Danger: Optimal First-Order Masking with Linear and Non-linear Bijections. AFRICACRYPT 2012: 360-377
- [c66]Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cédric Murdica, David Naccache: Low-Cost Countermeasure against RPA. CARDIS 2012: 106-122
- [c65]Sébastien Briais, Stéphane Caron, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, Jacques-Henri Jourdan, Arthur Milchior, David Naccache, Thibault Porteboeuf: 3D Hardware Canaries. CHES 2012: 1-22
- [c64]Cédric Murdica, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst, David Naccache: Same Values Power Analysis Using Special Points on Elliptic Curves. COSADE 2012: 183-198
- [c63]Houssem Maghrebi, Emmanuel Prouff, Sylvain Guilley, Jean-Luc Danger: A First-Order Leak-Free Masking Countermeasure. CT-RSA 2012: 156-170
- [c62]Youssef Souissi, Shivam Bhasin, Sylvain Guilley, Maxime Nassar, Jean-Luc Danger: Towards Different Flavors of Combined Side Channel Attacks. CT-RSA 2012: 245-259
- [c61]Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger: RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs. DATE 2012: 1173-1178
- [c60]Zouha Cherif, Jean-Luc Danger, Sylvain Guilley, Lilian Bossuet: An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF. DSD 2012: 156-162
- [c59]Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba: A Small and High-Performance Coprocessor for Fingerprint Match-on-Card. DSD 2012: 915-922
- [c58]Sébastien Briais, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, David Naccache, Thibault Porteboeuf: Random Active Shield. FDTC 2012: 103-113
- [c57]Houssem Maghrebi, Sylvain Guilley, Emmanuel Prouff, Jean-Luc Danger: Register leakage masking using Gray code. HOST 2012: 37-42
- [c56]Houssem Maghrebi, Olivier Rioul, Sylvain Guilley, Jean-Luc Danger: Comparison between Side-Channel Analysis Distinguishers. ICICS 2012: 331-340
- [c55]Sylvain Guilley, Jean-Luc Danger, Robert Nguyen, Philippe Nguyen: System-Level Methods to Prevent Reverse-Engineering, Cloning, and Trojan Insertion. ICISTM 2012: 433-438
- [c54]Claude Carlet, Jean-Luc Danger, Sylvain Guilley, Houssem Maghrebi: Leakage Squeezing of Order Two. INDOCRYPT 2012: 120-139
- [c53]Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger: From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications. MICRO Workshops 2012: 1-8
- [c52]Nicolas Debande, Youssef Souissi, M. Abdelaziz Elaabid, Sylvain Guilley, Jean-Luc Danger: Wavelet transform based pre-processing for side channel analysis. MICRO Workshops 2012: 32-38
- [c51]Youssef Souissi, Nicolas Debande, Sami Mekki, Sylvain Guilley, Ali Maalaoui, Jean-Luc Danger: On the Optimality of Correlation Power Attack on Embedded Cryptographic Systems. WISTP 2012: 169-178
- [i10]Houssem Maghrebi, Emmanuel Prouff, Sylvain Guilley, Jean-Luc Danger: A First-Order Leak-Free Masking Countermeasure. IACR Cryptology ePrint Archive 2012: 28 (2012)
- [i9]Houssem Maghrebi, Claude Carlet, Sylvain Guilley, Jean-Luc Danger: Optimal First-Order Masking with Linear and Non-Linear Bijections. IACR Cryptology ePrint Archive 2012: 175 (2012)
- [i8]Sébastien Briais, Stéphane Caron, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, Jacques-Henri Jourdan, Arthur Milchior, David Naccache, Thibault Porteboeuf: 3D Hardware Canaries. IACR Cryptology ePrint Archive 2012: 324 (2012)
- [i7]Sébastien Briais, Sylvain Guilley, Jean-Luc Danger: A formal study of two physical countermeasures against side channel attacks. IACR Cryptology ePrint Archive 2012: 430 (2012)
- [i6]Claude Carlet, Jean-Luc Danger, Sylvain Guilley, Houssem Maghrebi: Leakage Squeezing of Order Two. IACR Cryptology ePrint Archive 2012: 567 (2012)
- 2011
- [j5]Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger: Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks. IET Information Security 5(4): 181-190 (2011)
- [c50]Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar: Embedded systems security: An evaluation methodology against Side Channel Attacks. DASIP 2011: 230-237
- [c49]Olivier Meynard, Denis Réal, Florent Flament, Sylvain Guilley, Naofumi Homma, Jean-Luc Danger: Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques. DATE 2011: 1004-1009
- [c48]Sébastien Thomas, Didier Regis, David Faura, Marc Gatti, Guillaume Duc, Jean-Luc Danger: Non intrusive fault detection through electromagnetism analysis. ETFA 2011: 1-8
- [c47]Houssem Maghrebi, Sylvain Guilley, Jean-Luc Danger: Formal security evaluation of hardware Boolean masking against second-order attacks. HOST 2011: 40-46
- [c46]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Denis Réal: Performance evaluation of protocols resilient to physical attacks. HOST 2011: 51-56
- [c45]Maxime Nassar, Sylvain Guilley, Jean-Luc Danger: Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. INDOCRYPT 2011: 22-39
- [c44]Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger: "Rank Correction": A New Side-Channel Approach for Secret Key Recovery. InfoSecHiComNet 2011: 128-143
- [c43]Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger: Efficient Dual-Rail Implementations in FPGA Using Block RAMs. ReConFig 2011: 261-267
- [c42]Nicolas Debande, Youssef Souissi, Maxime Nassar, Sylvain Guilley, Thanh-Ha Le, Jean-Luc Danger: "Re-synchronization by moments": An efficient solution to align Side-Channel traces. WIFS 2011: 1-6
- [c41]Sylvain Guilley, Karim Khalfallah, Victor Lomné, Jean-Luc Danger: Formal Framework for the Evaluation of Waveform Resynchronization Algorithms. WISTP 2011: 100-115
- [c40]Houssem Maghrebi, Sylvain Guilley, Jean-Luc Danger: Leakage Squeezing Countermeasure against High-Order Attacks. WISTP 2011: 208-223
- [i5]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback. CoRR abs/1103.1360 (2011)
- [i4]Houssem Maghrebi, Sylvain Guilley, Claude Carlet, Jean-Luc Danger: Classification of High-Order Boolean Masking Schemes and Improvements of their Efficiency. IACR Cryptology ePrint Archive 2011: 520 (2011)
- [i3]Maxime Nassar, Sylvain Guilley, Jean-Luc Danger: Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. IACR Cryptology ePrint Archive 2011: 534 (2011)
- 2010
- [j4]Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfig. Comp. 2010 (2010)
- [c39]Shivam Bhasin, Sylvain Guilley, Florent Flament, Nidhal Selmane, Jean-Luc Danger: Countering early evaluation: an approach towards robust dual-rail precharge logic. WESS 2010: 6
- [c38]Olivier Meynard, Denis Réal, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Frédéric Valette: Characterization of the Electromagnetic Side Channel in Frequency Domain. Inscrypt 2010: 471-486
- [c37]Shivam Bhasin, Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger: Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks. CT-RSA 2010: 195-207
- [c36]Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley: BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. DATE 2010: 849-854
- [c35]Olivier Meynard, Sylvain Guilley, Jean-Luc Danger, Laurent Sauvage: Far Correlation-based EMA with a precharacterized leakage model. DATE 2010: 977-980
- [c34]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane: Fault Injection Resilience. FDTC 2010: 51-65
- [c33]Houssem Maghrebi, Sylvain Guilley, Jean-Luc Danger, Florent Flament: Entropy-based Power Attack. HOST 2010: 1-6
- [c32]Youssef Souissi, Sylvain Guilley, Jean-Luc Danger, Sami Mekki, Guillaume Duc: Improvement of power analysis attacks using Kalman filter. ICASSP 2010: 1778-1781
- [c31]Youssef Souissi, Maxime Nassar, Sylvain Guilley, Jean-Luc Danger, Florent Flament: First Principal Components Analysis: A New Side Channel Distinguisher. ICISC 2010: 407-419
- [c30]Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: Cross-Correlation Cartography. ReConFig 2010: 268-273
- [c29]Zouha Cherif, Florent Flament, Jean-Luc Danger, Shivam Bhasin, Sylvain Guilley, Hervé Chabanne: Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA. ReConFig 2010: 310-315
- [c28]M. Abdelaziz Elaabid, Olivier Meynard, Sylvain Guilley, Jean-Luc Danger: Combined Side-Channel Attacks. WISA 2010: 175-190
2000 – 2009
- 2009
- [j3]Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst: High speed true random number generator based on open loop structures in FPGAs. Microelectronics Journal 40(11): 1650-1656 (2009)
- [j2]Sami Mekki, Jean-Luc Danger, Benoit Miscopein: On the Implementation of a Probabilistic Equalizer for Low-Cost Impulse Radio UWB in High Data Rate. Wireless Sensor Network 1(4): 245-256 (2009)
- [c27]Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar: Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE 2009: 640-645
- [c26]Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger: WDDL is Protected against Setup Time Violation Attacks. FDTC 2009: 73-83
- [c25]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Nidhal Selmane: Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs. HOST 2009: 15-21
- [c24]Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet: Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS 2009: 351-354
- [c23]Julien Bringer, Hervé Chabanne, Jean-Luc Danger: Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic Implementations. ReConFig 2009: 183-188
- [c22]Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane: Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218
- [c21]Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: DPL on Stratix II FPGA: What to Expect?. ReConFig 2009: 243-248
- [i2]Julien Bringer, Hervé Chabanne, Jean-Luc Danger: Protecting the NOEKEON Cipher Against SCARE Attacks in FPGAs by using Dynamic Implementations. IACR Cryptology ePrint Archive 2009: 239 (2009)
- 2008
- [c20]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98
- [c19]Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger: An 8x8 run-time reconfigurable FPGA embedded in a SoC. DAC 2008: 120-125
- [c18]Nidhal Selmane, Sylvain Guilley, Jean-Luc Danger: Practical Setup Time Violation Attacks on AES. EDCC 2008: 91-96
- [c17]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet: Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC 2008: 3-17
- [c16]Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley: Efficient tiling patterns for reconfigurable gate arrays. FPGA 2008: 257
- [c15]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst: Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. FPL 2008: 161-166
- [c14]Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong: Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32
- [c13]Farouk Khelil, Mohamed Hamdi, Sylvain Guilley, Jean-Luc Danger, Nidhal Selmane: Fault Analysis Attack on an FPGA AES Implementation. NTMS 2008: 1-5
- [c12]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger: Efficient tiling patterns for reconfigurable gate arrays. SLIP 2008: 11-18
- [c11]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu: Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. SSIRI 2008: 16-23
- [c10]Sami Mekki, Jean-Luc Danger, Benoit Miscopein, Jean Schwoerer, Joseph Jean Boutros: Probabilistic Equalizer for Ultra-Wideband Energy Detection. VTC Spring 2008: 1108-1112
- [i1]Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks. CoRR abs/0809.3942 (2008)
- 2007
- [j1]Frédéric Guilloud, Emmanuel Boutillon, Jacky Tousch, Jean-Luc Danger: Generic Description and Synthesis of LDPC Decoders. IEEE Transactions on Communications 55(11): 2084-2091 (2007)
- [c9]Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley: Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. FPL 2007: 665-669
- [c8]Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst: A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT 2007: 369-372
- [c7]Qing Xu, M. B. C. Silva, Jean-Luc Danger, Sylvain Guilley, Patrick Bellot, Philippe Gallion, Francisco Mendieta: Towards Quantum Key Distribution System using Homodyne Detection with Differential Time-Multiplexed Reference. RIVF 2007: 158-165
- 2006
- [c6]Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst: FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems. ReConFig 2006: 47-55
- 2004
- [c5]Ioannis Krikidis, Jean-Luc Danger, Lirida A. B. Naviner: A finger configuration algorithm for a reconfigurable Rake receiver. WCNC 2004: 311-315
- 2002
- [c4]Frédéric Guilloud, Emmanuel Boutillon, Jean-Luc Danger: Bit error rate calculation for a multiband non-coherent on-off keying demodulation. ICC 2002: 202-206
- 2000
- [c3]Andrés D. García, Jean-Luc Danger, Wayne P. Burleson: Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. FPGA 2000: 220
1990 – 1999
- 1999
- [c2]Lirida A. B. Naviner, Jean-Luc Danger, C. Laurent: High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA. FPGA 1999: 249
- [c1]Andrés D. García, Wayne P. Burleson, Jean-Luc Danger: Power Modelling in Field Programmable Gate Arrays (FPGA). FPL 1999: 396-404
Coauthor Index
[j6] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [i10] [i9] [i8] [i7] [i6] [j5] [c50] [c49] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [i5] [i4] [i3] [j4] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [j3] [c27] [c26] [c25] [c24] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [i1] [c9] [c8] [c7] [c6]
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last updated on 2013-06-13 22:23 CEST by the dblp team