Manuel Jesús Bellido Díaz

Manuel J. Bellido

	2012
c21		Jorge Juan, Julian Viejo, Manuel J. Bellido: Network Time Synchronization: A Full Hardware Approach. PATMOS 2012: 225-234
	2011
j6		David Guerrero, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electronics 7(3): 444-452 (2011)
j5		Julian Viejo, Jorge Juan, Manuel Jesús Bellido Díaz, Alejandro Millán, Paulino Ruiz-de-Clavijo: Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. IEEE T. Instrumentation and Measurement 60(12): 3961-3963 (2011)
	2010
j4		Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo: Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electronics 6(1): 93-102 (2010)
c20		Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa: Design and implementation of a suitable core for on-chip long-term verification. SIES 2010: 234-237
	2009
c19		J. I. Villar, J. Juan, Manuel J. Bellido: Efficient techniques and methodologies for embedded system design usign free hardware and open standards. FPL 2009: 719-720
	2008
c18		Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo: Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS 2008: 389-398
	2007
j3		David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electronics 3(1): 70-77 (2007)
c17		David Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo: Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS 2007: 404-412
c16		Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa, A. Munoz: Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES 2007: 337-340
	2006
j2		Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero, Enrique Ostúa, Julian Viejo: Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electronics 2(1): 87-94 (2006)
	2005
c15		Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo: Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS 2005: 337-347
c14		Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo: Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS 2005: 425-435
	2004
c13		Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa: Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS 2004: 829-837
	2003
c12		Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero, Paulino Ruiz-de-Clavijo, Enrique Ostúa: Internode: Internal Node Logic Computational Model. Annual Simulation Symposium 2003: 241-248
c11		David Guerrero, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán: Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS 2003: 501-510
	2002
c10		C. Baena, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos J. Jiménez, Manuel Valencia: Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. PATMOS 2002: 353-362
c9		Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero: Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS 2002: 400-408
c8		Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero: Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS 2002: 477-486
e1		Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido (Eds.): Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002. Lecture Notes in Computer Science 2451, Springer 2002, isbn 3-540-44143-3
	2001
c7		Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia: HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE 2001: 467-471
c6		Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia: Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) 2001: 483-486
	2000
c5		Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia: Degradation Delay Model Extension to CMOS Gates. PATMOS 2000: 149-158
c4		Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia: Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS 2000: 316-326
	1996
c3		P. Fortet, Manuel J. Bellido, F. Sivianes, A. V. Medina: Multimedia System for Instruction and Learning Electronics. CALISCE 1996: 442-444
	1995
j1		Manuel Valencia, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano: Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers 44(12): 1456-1461 (1995)
c2		Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barros, Raúl Jiménez, José L. Huertas: New CMOS VLSI linear self-timed architectures. ASYNC 1995: 14-23
	1993
c1		Manuel J. Bellido, Manuel Valencia, Antonio J. Acosta, Angel Barriga Barros, José Luis Huertas, Rafael Domínguez-Castro: A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS 1993: 2019-2022

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