Michael Ciraula

List of publications from the DBLP Bibliography Server - FAQ
Other views: by type - by year (modern) - classic-C

Ask others: ACM DL/Guide -

	2011
c2		Don Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John Wuu: An 8MB level-3 cache in 32nm SOI with column-select aliasing. ISSCC 2011: 258-260
	2009
c1		Anant Singh, Michael Ciraula, Don Weiss, John Wuu, Philippe Bauser, Paul de Champs, Hamid Daghighian, David Fisch, Philippe Graber, Michel Bron: A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology. ISSCC 2009: 460-461

Coauthor Index

Last update Wed May 22 15:35:39 2013 CET by the DBLP Team —

Data released under the ODC-BY 1.0 license — See also our legal information page