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2020 – today
- 2023
[j35]Si-Dong Roh
, Ki-Seok Chung:
DiffusionVID: Denoising Object Boxes With Spatio-Temporal Conditioning for Video Object Detection. IEEE Access 11: 121434-121444 (2023)- [c47]Jihee Kim, Sangki Park, Si-Dong Roh, Ki-Seok Chung:
An Efficient Noisy Label Learning Method with Semi-supervised Learning: An Efficient Noisy Label Learning Method with Semi-supervised Learning. ICMVA 2023 - [c46]Kwang-Soo Seol, Si-Dong Roh, Ki-Seok Chung:
Token Merging with Class Importance Score. IECON 2023: 1-6 - [c45]Dae-Eun Wi, Kwangrae Kim, Ki-Seok Chung:
Dynamic Partitioning Method for Near-Memory Parallel Processing of Sparse Matrix-Vector Multiplication. IECON 2023: 1-6 - [c44]Nayeon Kim, Kwangrae Kim, Ki-Seok Chung:
Alert Refresh System for Mitigating RowHammer. ISOCC 2023: 29-30 - [c43]Seungyeon Koo, Sangki Park, Si-Dong Roh, Ki-Seok Chung:
iNLC: Iterative Noisy Label Correction. SITIS 2023: 99-106 - 2022
- [j34]Si-Dong Roh, Ki-Seok Chung:
DAFA: Diversity-Aware Feature Aggregation for Attention-Based Video Object Detection. IEEE Access 10: 93453-93463 (2022) - [j33]Sang-Soo Park, Ki-Seok Chung:
Regularized Convolutional Neural Network for Highly Effective Parallel Processing. J. Comput. Sci. Eng. 16(2): 105-112 (2022) - [c42]Dong-Hee Kim, Jaeyoon Lee, Ki-Seok Chung:
What Matters for Out-of-Distribution Detectors using Pre-trained CNN? VISIGRAPP (4: VISAPP) 2022: 264-273 - 2021
- [j32]Kyeong-Bin Park, Ki-Seok Chung:
Iterative Pseudo-Soft-Reliability-Based Majority-Logic Decoding for NAND Flash Memory. IEEE Access 9: 74531-74538 (2021) - [j31]Kyeong-Bin Park, Ki-Seok Chung:
Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm. KSII Trans. Internet Inf. Syst. 15(2): 485-499 (2021) - [c41]Jun-Gu Kang, Si-Dong Roh, Ki-Seok Chung:
FlowNetU: Accurate Uncertainty Estimation of Optical Flow for Video Object Detection. AIPR 2021: 36-41 - [c40]Kwangrae Kim, Jeonghyun Woo, Junsu Kim, Ki-Seok Chung:
HammerFilter: Robust Protection and Low Hardware Overhead Method for RowHammer. ICCD 2021: 212-219 - [c39]Hanbyeol Kwon, Kwangrae Kim, Dongsuk Jeon, Ki-Seok Chung:
Reducing Refresh Overhead with In-DRAM Error Correction Codes. ISOCC 2021: 211-214 - [c38]Heechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki-Seok Chung, Taewhan Kim:
Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. ISOCC 2021: 215-218 - [c37]Sang-Soo Park, Dong-Hee Kim, Jun-Gu Kang, Ki-Seok Chung:
EdgeRL: A Light-Weight C/C++ Framework for On-Device Reinforcement Learning. ISOCC 2021: 235-236 - [c36]Hyuntak Lim, Si-Dong Roh, Sangki Park, Ki-Seok Chung:
Robustness-Aware Filter Pruning for Robust Neural Networks Against Adversarial Attacks. MLSP 2021: 1-6 - [c35]Jaeyoon Lee, Hyuntak Lim, Ki-Seok Chung:
CLC: Noisy Label Correction via Curriculum Learning. SSCI 2021: 1-7 - 2020
- [c34]Dong-Hee Kim, Changwoo Lee, Ki-Seok Chung:
A Confidence-Calibrated MOBA Game Winner Predictor. CoG 2020: 622-625 - [c33]Won-Hyuk Lee, Si-Dong Roh, Sangki Park, Ki-Seok Chung:
Direct Conversion: Accelerating Convolutional Neural Networks Utilizing Sparse Input Activation. IECON 2020: 441-446 - [i1]Dong-Hee Kim, Changwoo Lee, Ki-Seok Chung:
A Confidence-Calibrated MOBA Game Winner Predictor. CoRR abs/2006.15521 (2020)
2010 – 2019
- 2019
- [c32]Ki-Seok Chung, Changwoo Lee:
GRAM: Gradient Rescaling Attention Model for Data Uncertainty Estimation in Single Image Super Resolution. ICMLA 2019: 8-13 - 2018
- [j30]Dong-Ik Jeon, Kyeong-Bin Park, Ki-Seok Chung:
HMC-MAC: Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube. IEEE Comput. Archit. Lett. 17(1): 5-8 (2018) - [j29]Dong-Ik Jeon, Min-Kyu Lee, Ji-Chan Kim, Ki-Seok Chung:
Runtime Memory Controller Profiling with Performance Analysis for DRAM Memory Controllers. J. Circuits Syst. Comput. 27(8): 1850126:1-1850126:20 (2018) - [c31]Sangki Park, Sang-Soo Park, Ki-Seok Chung:
Log-quantization on GRU networks. ICCIP 2018: 112-116 - [c30]Hyun-Woong Yang, Min-Kyu Lee, Ki-Seok Chung:
Per-bank refresh with adaptive early termination for high density DRAM. ICCIP 2018: 169-173 - [c29]Sung-Jin Lee, Sang-Soo Park, Ki-Seok Chung:
Efficient SIMD implementation for accelerating convolutional neural network. ICCIP 2018: 174-179 - [c28]Geon Choi, Kyeong-Bin Park, Ki-Seok Chung:
Optimization of FPGA-based LDPC decoder using high-level synthesis. ICCIP 2018: 256-259 - [c27]Sang-Soo Park, Kyeong-Bin Park, Ki-Seok Chung:
Implementation of a CNN accelerator on an Embedded SoC Platform using SDSoC. ICDSP 2018: 161-165 - [c26]Jung Soo Kim, Min-Kyu Lee, Ki-Seok Chung:
Image Blending Techniques Based on GPU Acceleration. ICIGP 2018: 106-109 - [c25]Jae-Sung An, Sang-Hyun Han, Kyeong-Bin Park, Ju Eon Kim, Jae-Hun Ye, Seung-Hwan Lee, Ji-Yong Jeong, Jung Soo Kim, Kwang-Hyun Baek, Ki-Seok Chung, Seong-Kwan Hong, Oh-Kyong Kwon:
Multi-way interactive capacitive touch system with palm rejection of active stylus for 86" touch screen panels. ISSCC 2018: 182-184 - 2017
- [j28]Dong-Ik Jeon, Ki-Seok Chung:
CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube. IEEE Comput. Archit. Lett. 16(1): 10-13 (2017) - [j27]Keol Cho, Ki-Seok Chung:
Self-Adaptive Termination Check of Min-Sum Algorithm for LDPC Decoders Using the First Two Minima. KSII Trans. Internet Inf. Syst. 11(4): 1987-2001 (2017) - [c24]Sang-Soo Park, Jung-Hyun Hong, Ki-Seok Chung:
Modified Convolution Neural Network for Highly Effective Parallel Processing. IRI 2017: 325-331 - 2016
- [j26]Keol Cho, Ki-Seok Chung:
Self-Adaptive Scaled Min-Sum Algorithm for LDPC Decoders Based on Delta-Min. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(8): 1632-1634 (2016) - [j25]Jung-Hyun Hong, Joo-Yul Park, Ki-Seok Chung:
Parallel LDPC Decoding on a Heterogeneous Platform using OpenCL. KSII Trans. Internet Inf. Syst. 10(6): 2648-2668 (2016) - [j24]Youngho Ahn, Ki-Seok Chung:
User-Centric Power Management for Embedded CPUs Using CPU Bandwidth Control. IEEE Trans. Mob. Comput. 15(9): 2388-2397 (2016) - 2015
- [j23]Daecheol You, Ki-Seok Chung:
Quality of Service-Aware Dynamic Voltage and Frequency Scaling for Embedded GPUs. IEEE Comput. Archit. Lett. 14(1): 66-69 (2015) - [j22]Keol Cho, Ki-Seok Chung:
Conditional termination check min-sum algorithm for efficient LDPC decoders. IEICE Electron. Express 12(24): 20150738 (2015) - [c23]Jung-Hyun Hong, Ki-Seok Chung:
Parallel LDPC decoding on a GPU using OpenCL and global memory for accelerators. NAS 2015: 353-354 - [c22]Dong-Ik Jeon, Min-Kyu Lee, Ki-Seok Chung:
Analysis of various DRAM devices from power consumption's perspective. NAS 2015: 359-360 - 2014
- [j21]Jung-Hyun Hong, Youngho Ahn, Byungjin Kim, Ki-Seok Chung:
Design of OpenCL framework for embedded multi-core processors. IEEE Trans. Consumer Electron. 60(2): 233-241 (2014) - 2013
- [j20]Youngho Ahn, Joo-Yul Park, Ki-Seok Chung:
Dynamic voltage and frequency scaling scheme for an adaptive LDPC decoder using SNR estimation. EURASIP J. Wirel. Commun. Netw. 2013: 255 (2013) - [j19]Jung-Hyun Hong, Won-Jin Kim, Ki-Seok Chung:
A Parallelization Technique with Integrated Multi-Threading for Video Decoding on Multi-core Systems. KSII Trans. Internet Inf. Syst. 7(10): 2479-2496 (2013) - [j18]Young-Si Hwang, Ki-Seok Chung:
Dynamic Power Management Technique for Multicore Based Embedded Mobile Devices. IEEE Trans. Ind. Informatics 9(3): 1601-1612 (2013) - [c21]Dong-Ik Jeon, Kwang-Soo Han, Ki-Seok Chung:
Novel level-up shifters for high performance and low power mobile devices. ICCE 2013: 181-182 - 2012
- [c20]Kwang-Soo Han, Dong-Ik Jeon, Ki-Seok Chung:
Ultra low power and high speed FPGA design with CNFET. ISCIT 2012: 828-833 - 2011
- [j17]Joo-Yul Park, Ki-Seok Chung:
An adaptive low-power LDPC decoder using SNR estimation. EURASIP J. Wirel. Commun. Netw. 2011: 48 (2011) - [j16]Joo-Yul Park, Ki-Seok Chung:
Parallel LDPC decoding using CUDA and OpenMP. EURASIP J. Wirel. Commun. Netw. 2011: 172 (2011) - [j15]Byungjin Kim, Youngho Ahn, Ki-Seok Chung:
A Technique for Fast Process Creation Based on Creation Location. J. Comput. Sci. Eng. 5(4): 283-287 (2011) - [j14]Won-Jin Kim, Keol Cho, Ki-Seok Chung:
Multi-threaded syntax element partitioning for parallel entropy decoding. IEEE Trans. Consumer Electron. 57(2): 897-905 (2011) - [j13]Joo-Yul Park, Ki-Seok Chung:
Overlapped message passing technique with resource sharing for high speed CMMB LDPC decoder. IEEE Trans. Consumer Electron. 57(4): 1564-1570 (2011) - [c19]Joo-Yul Park, Ki-Seok Chung:
LDPC decoding for CMMB utilizing OpenMP and CUDA parallelization. APCC 2011: 910-914 - [c18]Hi-Seok Kim, Sea-Ho Kim, Ki-Seok Chung:
FPGA implementation of unified kernel structure for MDCT/IMDCT in audio coding schemes. ISOCC 2011: 100-103 - [c17]Daecheol You, Young-Si Hwang, Youngho Ahn, Ki-Seok Chung:
A Test Method for Power Management of SoC-based Microprocessors. MTV 2011: 28-31 - 2010
- [j12]Young-Si Hwang, Sung-Kwan Ku, Ki-Seok Chung:
A predictive dynamic power management technique for embedded mobile devices. IEEE Trans. Consumer Electron. 56(2): 713-719 (2010) - [j11]Won-Jin Kim, Keol Cho, Ki-Seok Chung:
Stage-based frame-partitioned parallelization of H.264/AVC decoding. IEEE Trans. Consumer Electron. 56(2): 1088-1096 (2010)
2000 – 2009
- 2009
- [j10]Young-Geun Lee, Han-Sam Jung, Ki-Seok Chung:
Low Power MAC Design with Variable Precision Support. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(7): 1623-1632 (2009) - [j9]Joo-Yul Park, So-Jin Lee, Ki-Seok Chung:
A novel SoC platform based multi-IP verification and performance measurement. Int. J. Inf. Commun. Technol. 2(1/2): 120-131 (2009) - [j8]So-Jin Lee, Joo-Yul Park, Ki-Seok Chung:
Optimisation of RunBefore decoder and first one detector for MPEG-4 AVC/H.264 CAVLC decoding. Int. J. Inf. Commun. Technol. 2(1/2): 132-141 (2009) - [j7]Pilok Lim, Ki-Seok Chung, Taewhan Kim:
Thermal-Aware High-Level Synthesis Based on Network Flow Method. J. Circuits Syst. Comput. 18(5): 965-984 (2009) - [j6]So-Jin Lee, Joo-Yul Park, Ki-Seok Chung:
Memory efficient multi-rate regular LDPC decoder for CMMB. IEEE Trans. Consumer Electron. 55(4): 1866-1874 (2009) - [j5]Byunghyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim:
Thermal sensor allocation and placement for reconfigurable systems. ACM Trans. Design Autom. Electr. Syst. 14(4): 50:1-50:23 (2009) - [c16]Jinwoo Song, Kee Beom Kim, Yong Ho Song, Ki-Seok Chung:
Implementation of IEEE802.11a software defined receiver on chip multi-processor architecture using OpenMP. ICHIT 2009: 598-601 - [c15]Kee Beom Kim, Seong Min Jo, Jin Woo Song, Ki-Seok Chung, Yong Ho Song:
Performance evaluation of on-chip interconnect IP using CBR traffic generator model. ICHIT 2009: 637-642 - 2008
- [c14]Sea-Ho Kim, Byung-Gyu Ahn, Ki-Seok Chung, Sung-Hwan Oh:
Timing driven force-directed floorplanning with incremental static timing analyzer. APCCAS 2008: 1000-1003 - [c13]Young-Si Hwang, Sung-Kwan Ku, Chan-Min Jung, Ki-Seok Chung:
Predictive power aware management for embedded mobile devices. ASP-DAC 2008: 36-41 - [c12]Sung-Kwan Ku, Han-Sam Jung, Ki-Seok Chung:
A unified power measurement and management platform for pipelined MPSoC executions. SoCC 2008: 13-16 - 2007
- [c11]Young-Geun Lee, Joo-Yul Park, Ki-Seok Chung:
Design of Low Power MAC Operator with Dual Precision Mode. RTCSA 2007: 309-318 - [c10]Won-Jin Kim, Ki-Seok Chung:
An incremental floorplanning algorithm for temperature reduction. SoCC 2007: 67-70 - 2004
- [c9]Jaewon Seo, Taewhan Kim, Ki-Seok Chung:
Profile-based optimal intra-task voltage scheduling for hard real-time applications. DAC 2004: 87-92 - 2003
- [c8]J. K. Kim, S. H. Won, Ki-Seok Chung, H. D. Cho, T. W. Kang, T. S. Nam, C. S. Kang, C. H. Yi, D. S. Kim:
Properties of A1/BaTa2O6/GaN MIS Structure. VLSI 2003: 240-243 - 2002
- [j4]Ki-Seok Chung, Taewhan Kim, C. L. Liu:
A Complete Model for Glitch Analysis in Logic Circuits. J. Circuits Syst. Comput. 11(2): 137-154 (2002) - [j3]Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu:
Synthesis and Optimization of Combinational Interface Circuits. J. VLSI Signal Process. 31(3): 243-261 (2002) - [c7]Unni Narayanan, Ki-Seok Chung, Taewhan Kim:
Enhanced bus invert encodings for low-power. ISCAS (5) 2002: 25-28 - 2001
- [j2]Ki-Seok Chung, Taewhan Kim, C. L. Liu:
G-vector: A New Model for Glitch Analysis in Logic Circuits. J. VLSI Signal Process. 27(3): 235-251 (2001) - [c6]Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu:
A Static Estimation Technique of Power Sensitivity in Logic Circuits. DAC 2001: 215-219 - 2000
- [j1]Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung:
Decomposition of Bus-Invert Coding for Low-Power I/O. J. Circuits Syst. Comput. 10(1-2): 101-112 (2000) - [c5]Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu:
Behavioral-level partitioning for low power design in control-dominated application. ACM Great Lakes Symposium on VLSI 2000: 156-161
1990 – 1999
- 1998
- [b1]Ki-Seok Chung:
Modeling and Synthesis of Combinational Logic Circuits: A Power Dissipation Perspective. University of Illinois Urbana-Champaign, USA, 1998 - [c4]Ki-Seok Chung, C. L. Liu:
Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. ISLPED 1998: 215-220 - 1997
- [c3]Unni Narayanan, Hon Wai Leong, Ki-Seok Chung, Chien-Liang Liu:
Low power multiplexer decomposition. ISLPED 1997: 269-274 - 1996
- [c2]Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu:
An algorithm for synthesis of system-level interface circuits. ICCAD 1996: 442-447 - 1994
- [c1]Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu:
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. EDAC-ETC-EUROASIC 1994: 586-590
Coauthor Index
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