Yi-Lin Chuang Coauthor index pubzone.org

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c8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Da-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang: Statistical thermal modeling and optimization considering leakage power variations. DATE 2012: 605-610
2011
j3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang: Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1649-1662 (2011)
j2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang: Pulsed-Latch Aware Placement for Timing-Integrity Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(12): 1856-1869 (2011)
c7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu: PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. ICCAD 2011: 85-90
c6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho: Pulsed-latch-based clock tree migration for dynamic power reduction. ISLPED 2011: 39-44
2010
c5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang: Pulsed-latch aware placement for timing-integrity optimization. DAC 2010: 280-285
c4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan: Design-hierarchy aware mixed-size placement for routability optimization. ICCAD 2010: 663-668
2009
c3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang: Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. ICCAD 2009: 666-673
2008
j1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang: Effective Wire Models for X-Architecture Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 654-658 (2008)
c2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang: Constraint graph-based macro placement for modern mixed-size circuit designs. ICCAD 2008: 218-223
2007
c1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang: X-architecture placement based on effective wire models. ISPD 2007: 87-94

Coauthor Index

1Charles J. Alpert
[c4]
2Yao-Wen Chang
[c8] [j3] [j2] [c7] [c5] [c4] [c3] [j1] [c2] [c1]
3Yung-Chung Chang
[c2]
4Hsin-Chen Chen
[c2]
5Tung-Chieh Chen
[j1] [c1]
6Tsung-Yi Ho
[c7] [c6]
7Da-Cheng Juan
[c8]
8Sangmin Kim
[j2] [c5]
9Po-Wei Lee
[j3] [c3]
10Hong-Ting Lin
[c7] [c6]
11Diana Marculescu
[c8] [c7]
12Gi-Joon Nam
[c4]
13Jarrod A. Roy
[c4]
14Youngsoo Shin
[j2] [c5]
15Natarajan Viswanathan
[c4]
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