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Hwang-Cherng Chow
2000 – 2009
- 2008
[c8]Hwang-Cherng Chow, Pu-Nan Weng: A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications. DELTA 2008: 232-235- 2007
[c7]Hwang-Cherng Chow, Jia-Yu Wang: High CMRR instrumentation amplifier for biomedical applications. ISSPA 2007: 1-4- 2005
[c6]Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng: A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications. ISCAS (1) 2005: 736-739- 2004
[c5]Hwang-Cherng Chow, Shu-Hsien Chang: High performance sense amplifier circuit for low power SRAM applications. ISCAS (2) 2004: 741-744- 2003
[c4]Hwang-Cherng Chow, I-Chyn Wey: A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. ISCAS (5) 2003: 121-124- 2002
[c3]Hwang-Cherng Chow, Yung-Kuo Ho: New pixel-shared design and split-path readout of CMOS image sensor circuits. ISCAS (4) 2002: 49-52
[c2]Hwang-Cherng Chow, I-Chyn Wey: A 3.3 V 1 GHz high speed pipelined Booth multiplier. ISCAS (1) 2002: 457-460
1990 – 1999
- 1999
[c1]
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last updated on 2012-10-12 22:05 CEST by the dblp team



