Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Mei-Fang Chiang
2010 – today
- 2012
[c5]Yiqun Wang, Yongpan Liu, Yumeng Liu, Daming Zhang, Shuangchen Li, Baiko Sai, Mei-Fang Chiang, Huazhong Yang: A compression-based area-efficient recovery architecture for nonvolatile processors. DATE 2012: 1519-1524- [c4]Yiqun Wang, Yongpan Liu, Shuangchen Li, Daming Zhang, Bo Zhao, Mei-Fang Chiang, Yanxin Yan, Baiko Sai, Huazhong Yang: A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops. ESSCIRC 2012: 149-152
- 2010
- [j3]Song Chen, Jianwei Shen, Wei Guo, Mei-Fang Chiang, Takeshi Yoshimura: Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density. IEICE Transactions 93-A(12): 2372-2379 (2010)
2000 – 2009
- 2009
- [j2]Song Chen, Liangwei Ge, Mei-Fang Chiang, Takeshi Yoshimura: Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs. IEICE Transactions 92-A(4): 1080-1087 (2009)
- [c3]Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura: Register placement for high-performance circuits. DATE 2009: 1470-1475
- [c2]Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura: Lagrangian relaxation based register placement for high-performance circuits. ISQED 2009: 511-516
- 2008
- [j1]Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han: Full-Chip Routing Considering Double-Via Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 844-857 (2008)
- 2006
- [c1]Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han: Novel full-chip gridless routing considering double-via insertion. DAC 2006: 755-760
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2012-11-16 23:54 CET by the dblp team