We are currently collecting comments, critizisms, and testimonials for the evaluation of our efforts by our public funders. If you want to share any thoughts that we may use in our report, please feel free to send us your comments!
Sourindra Chaudhuri, Niraj K. Jha: 3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations.JETC10(3): 26:1-26:19 (2014)
Sourindra M. Chaudhuri, Prateek Mishra, Niraj K. Jha: Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology.JETC11(2): 19:1-19:20 (2014)
Sourindra Chaudhuri, Niraj K. Jha: FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage.VLSI Design2014: 476-482