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 | 2012 | |
|---|---|---|
| j14 |      | Song-Nien Tang, Chi-Hsiang Liao, Tsin-Yuan Chang: An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems. J. Solid-State Circuits 47(6): 1419-1435 (2012) |
| j13 | | Yuan-Ho Chen, Tsin-Yuan Chang: A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers. IEEE Trans. on Circuits and Systems 59-I(3): 594-603 (2012) |
| j12 | | Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, Kiwing To: Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG. IEEE Trans. VLSI Syst. 20(2): 385-389 (2012) |
| j11 | | Yuan-Ho Chen, Tsin-Yuan Chang: A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy. IEEE Trans. VLSI Syst. 20(4): 655-664 (2012) |
| 2011 | ||
| j10 | | Yuan-Ho Chen, Chung-Yi Li, Tsin-Yuan Chang: Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 277-288 (2011) |
| j9 | | Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Jyun-Neng Chen: A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications. IEEE Trans. on Circuits and Systems 58-II(4): 215-219 (2011) |
| j8 | | Yuan-Ho Chen, Tsin-Yuan Chang, Chung-Yi Li: High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree. IEEE Trans. VLSI Syst. 19(4): 709-714 (2011) |
| 2010 | ||
| j7 | | Po-Lin Chen, Yu-Chieh Huang, Tsin-Yuan Chang: Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1837-1842 (2010) |
| j6 | | Song-Nien Tang, Jui-Wei Tsai, Tsin-Yuan Chang: A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications. IEEE Trans. on Circuits and Systems 57-II(6): 451-455 (2010) |
| 2009 | ||
| j5 | | Po-Lin Chen, Jhih-Wei Lin, Tsin-Yuan Chang: IEEE Standard 1500 Compatible Delay Test Framework. IEEE Trans. VLSI Syst. 17(8): 1152-1156 (2009) |
| 2008 | ||
| j4 | | Hung-Chih Lin, Hsiang-Han Wu, Tsin-Yuan Chang: An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement. IEEE Trans. on Circuits and Systems 55-II(9): 853-857 (2008) |
| c16 | | Hung-Chih Lin, Bou-Ching Fung, Tsin-Yuan Chang: A current mode adaptive on-time control scheme for fast transient DC-DC converters. ISCAS 2008: 2602-2605 |
| c15 | | Chung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang: An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES. ISVLSI 2008: 503-506 |
| 2006 | ||
| c14 | | Chung-Yi Li, Jiung-Sheng Chen, Tsin-Yuan Chang: A chaos-based pseudo random number generator using timing-based reseeding method. ISCAS 2006 |
| 2005 | ||
| c13 | | Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang: On-chip accumulated jitter measurement for phase-locked loops. ASP-DAC 2005: 1184-1187 |
| 2004 | ||
| j3 | | Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang: A Built-In Parametric Timing Measurement Unit. IEEE Design & Test of Computers 21(4): 322-330 (2004) |
| c12 | | Kae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang: Timing measurement unit with multi-stage TVC for embedded memories. ASP-DAC 2004: 565-566 |
| c11 | | Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang: A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier. Asian Test Symposium 2004: 272-276 |
| 2003 | ||
| c10 | | Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong: A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers. ISCAS (5) 2003: 365-368 |
| 2002 | ||
| c9 | | Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang: An Access Timing Measurement Unit of Embedded Memory. Asian Test Symposium 2002: 104- |
| c8 | | Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang: An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters. Asian Test Symposium 2002: 266- |
| 2001 | ||
| c7 | | Jeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang: An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters. Asian Test Symposium 2001: 423- |
| c6 | | Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A low-cost CMOS time interval measurement core. ISCAS (4) 2001: 190-193 |
| c5 | | Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A built-in timing parametric measurement unit. ITC 2001: 315-322 |
| 2000 | ||
| c4 | | Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang: A realistic fault model for flash memories. Asian Test Symposium 2000: 274-281 |
| c3 | | |
| 1999 | ||
| j2 | | Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang: A Programmable BIST Core for Embedded DRAM. IEEE Design & Test of Computers 16(1): 59-70 (1999) |
| 1990 | ||
| j1 | | Chin-Long Wey, Tsin-Yuan Chang: An efficient output phase assignment for PLA minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 9(1): 1-7 (1990) |
| c2 | | Chin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang: Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement. DAC 1990: 327-332 |
| 1988 | ||
| c1 | | Chin-Long Wey, Tsin-Yuan Chang: PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs. DAC 1988: 421-426 |
Colors in the list of coauthors
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