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Ming-Tung Chang
2010 – today
- 2011
[c5]Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li: Test clock domain optimization for peak power supply noise reduction during scan. ITC 2011: 1-8- 2010
- [c4]Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li: TSV redundancy: Architecture and design issues in 3D IC. DATE 2010: 166-171
2000 – 2009
- 2009
- [c3]Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng: BIST design optimization for large-scale embedded memory cores. ICCAD 2009: 197-200
- 2008
- [c2]Hsiu-Ting Lin, Jen-Yang Wen, James Li, Ming-Tung Chang, Min-Hsiu Tsai, Sheng-Chih Huang, Chili-Mou Tseng: Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise. ITC 2008: 1
- 2005
- [c1]Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang: UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction. ITC 2005: 8
Coauthor Index
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last updated on 2012-09-10 15:45 CEST by the dblp team