Chip-Hong Chang

Hanhua Qian, Chip-Hong Chang, Hao Yu: An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits. Integration 46(1): 57-68 (2013)

Hanhua Qian, Hao Liang, Chip-Hong Chang, Wei Zhang, Hao Yu: Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects. ASP-DAC 2013: 485-490

Pak Kwong Chan, Chip-Hong Chang, Kiat Seng Yeo: Foreword. Journal of Circuits, Systems, and Computers 21(8) (2012)

Chip-Hong Chang, Howard Luong, Shanthi Pavan: Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011). IEEE Trans. on Circuits and Systems 59-I(8): 1601-1603 (2012)

Ramya Muralidharan, Chip-Hong Chang: Area-Power Efficient Modulo 2ⁿ-1 and Modulo 2ⁿ+1 Multipliers for {2ⁿ-1, 2ⁿ, 2ⁿ+1} Based RNS. IEEE Trans. on Circuits and Systems 59-I(10): 2263-2274 (2012)

Jeremy Yung Shern Low, Chip-Hong Chang: A VLSI Efficient Programmable Power-of-Two Scaler for 2ⁿ-1, 2ⁿ, 2ⁿ+1 RNS. IEEE Trans. on Circuits and Systems 59-I(12): 2911-2919 (2012)

Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang: An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture. IEEE Trans. on Circuits and Systems 59-I(12): 2945-2955 (2012)

Fei Li, Arindam Basu, Chip-Hong Chang, Avis H. Cohen: Dynamical Systems Guided Design and Analysis of Silicon Oscillators for Central Pattern Generators. IEEE Trans. on Circuits and Systems 59-I(12): 3046-3059 (2012)

Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek, Ching-Chuen Jong, Chip-Hong Chang: A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. APCCAS 2012: 272-275

Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang: A unified {2ⁿ-1, 2ⁿ, 2ⁿ+1} RNS scaler with dual scaling constants. APCCAS 2012: 296-299

Aijiao Cui, Chip-Hong Chang: A post-processing scan-chain watermarking scheme for VLSI intellectual property protection. APCCAS 2012: 412-415

Martin Kumm, Peter Zipf, Mathias Faust, Chip-Hong Chang: Pipelined adder graph optimization for high speed multiple constant multiplication. ISCAS 2012: 49-52

Joshua Yung Lih Low, Ching-Chuen Jong, Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang: A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. ISCAS 2012: 1235-1238

Li Zhang, Chip-Hong Chang: State encoding watermarking for field authentication of sequential circuit intellectual property. ISCAS 2012: 3013-3016

Hanhua Qian, Xiwei Huang, Hao Yu, Chip-Hong Chang: Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling. J. Low Power Electronics 7(1): 110-121 (2011)

Aijiao Cui, Chip-Hong Chang, Sofiène Tahar, Amr T. Abdel-Hamid: A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design. IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 678-690 (2011)

Ramya Muralidharan, Chip-Hong Chang: Radix-8 Booth Encoded Modulo 2 ⁿ -1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System. IEEE Trans. on Circuits and Systems 58-I(5): 982-993 (2011)

Chip-Hong Chang, Jeremy Yung Shern Low: Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set 2ⁿ - 1, 2ⁿ, 2ⁿ + 1. IEEE Trans. on Circuits and Systems 58-I(11): 2686-2697 (2011)

Ruimin Huang, Chip-Hong Chang, Mathias Faust, Niklas Lotze, Yiannos Manoli: Sign-Extension Avoidance and Word-Length Optimization by Positive-Offset Representation for FIR Filter Design. IEEE Trans. on Circuits and Systems 58-II(12): 916-920 (2011)

Y. Shao, Chip-Hong Chang: Bayesian Separation With Sparsity Promotion in Perceptual Wavelet Domain for Speech Enhancement and Hybrid Speech Recognition. IEEE Transactions on Systems, Man, and Cybernetics, Part A 41(2): 284-293 (2011)

Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang: A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters. IEEE Trans. VLSI Syst. 19(10): 1733-1745 (2011)

Mathias Faust, Chip-Hong Chang: Low error bit width reduction for structural adders of FIR filters. ECCTD 2011: 713-716

Mathias Faust, Chip-Hong Chang: Bit-parallel Multiple Constant Multiplication using Look-Up Tables on FPGA. ISCAS 2011: 657-660

Ramya Muralidharan, Chip-Hong Chang: A simple radix-4 Booth encoded modulo 2ⁿ+1 multiplier. ISCAS 2011: 1163-1166

Jeremy Yung Shern Low, Chip-Hong Chang: A new RNS scaler for {2ⁿ - 1, 2ⁿ, 2ⁿ + 1}. ISCAS 2011: 1431-1434

Aijiao Cui, Chip-Hong Chang, Li Zhang: A hybrid watermarking scheme for sequential functions. ISCAS 2011: 2333-2336

Chip-Hong Chang, Mathias Faust: On "A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters". IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 844-848 (2010)

Chip-Hong Chang, Aijiao Cui: Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property. IEEE Trans. on Circuits and Systems 57-I(7): 1618-1630 (2010)

Chip-Hong Chang, Ravi Kumar Satzoda: A Low Error and High Performance Multiplexer-Based Truncated Multiplier. IEEE Trans. VLSI Syst. 18(12): 1767-1771 (2010)

Hanhua Qian, Xiwei Huang, Hao Yu, Chip-Hong Chang: Real-time thermal management of 3D multi-core system with fine-grained cooling control. 3DIC 2010: 1-6

Mathias Faust, Chip-Hong Chang: Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication. ISCAS 2010: 457-460

Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang, Jeremy Yung Shern Low: A novel counter-based low complexity inner-product architecture for high speed inputs. ISCAS 2010: 705-708

Ramya Muralidharan, Chip-Hong Chang: Fast hard multiple generators for radix-8 Booth encoded modulo 2ⁿ-1 and modulo 2ⁿ+1 multipliers. ISCAS 2010: 717-720

Jiajia Chen, Chip-Hong Chang: High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier. IEEE Trans. on CAD of Integrated Circuits and Systems 28(12): 1844-1856 (2009)

Yajuan He, Chip-Hong Chang: A New Redundant Binary Booth Encoding for Fast 2ⁿ-Bit Multiplier Design. IEEE Trans. on Circuits and Systems 56-I(6): 1192-1201 (2009)

Aijiao Cui, Chip-Hong Chang: An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering. ISCAS 2009: 29-32

Ramya Muralidharan, Chip-Hong Chang: Fixed and Variable Multi-modulus Squarer Architectures for Triple Moduli base of RNS. ISCAS 2009: 441-444

Jiajia Chen, Chip-Hong Chang, Ching-Chuen Jong: Time-multiplexed Data Flow Graph for the Design of Configurable Multiplier Block. ISCAS 2009: 1145-1148

Fei Li, Chip-Hong Chang, Liter Siek: A Compact Current Mode Neuron Circuit with Gaussian Taper Learning Capability. ISCAS 2009: 2129-2132

Mathias Faust, Chip-Hong Chang: Optimization of Structural Adders in Fixed Coefficient Transposed Direct Form FIR Filters. ISCAS 2009: 2185-2188

Jiajia Chen, Chip-Hong Chang, Hanhua Qian: New Power Index Model for Switching Power Analysis from Adder Graph of FIR filter. ISCAS 2009: 2197-2200

Aijiao Cui, Chip-Hong Chang, Sofiène Tahar: IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1565-1570 (2008)

Yajuan He, Chip-Hong Chang: A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter. IEEE Trans. on Circuits and Systems 55-I(1): 336-346 (2008)

Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: Contention Resolution - A New Approach to Versatile Subexpressions Sharing in Multiple Constant Multiplications. IEEE Trans. on Circuits and Systems 55-I(2): 559-571 (2008)

Chip-Hong Chang, Jiajia Chen, Achutavarrier Prasad Vinod: Information Theoretic Approach to Complexity Reduction of FIR Filter Design. IEEE Trans. on Circuits and Systems 55-I(8): 2310-2321 (2008)

Ravi Kumar Satzoda, Ramya Muralidharan, Chip-Hong Chang: Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2^m). ISCAS 2008: 808-811

Aijiao Cui, Chip-Hong Chang: Intellectual property authentication by watermarking scan chain in design-for-testability flow. ISCAS 2008: 2645-2648

Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: Hamming weight pyramid - A new insight into canonical signed digit representation and its applications. Computers & Electrical Engineering 33(3): 195-207 (2007)

A. Prasad Vinod, Ankita Singla, Chip-Hong Chang: Low-power differential coefficients-based FIR filters using hardware-optimised multipliers. IET Circuits, Devices & Systems 1(1): 13-20 (2007)

Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1898-1907 (2007)

Yu Shao, Chip-Hong Chang: A Generalized Time-Frequency Subtraction Method for Robust Speech Enhancement Based on Wavelet Filter Banks Modeling of Human Auditory System. IEEE Transactions on Systems, Man, and Cybernetics, Part B 37(4): 877-889 (2007)

Aijiao Cui, Chip-Hong Chang: Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. ISCAS 2007: 3687-3690

Jiajia Chen, Chip-Hong Chang, A. Prasad Vinod: Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics. APCCAS 2006: 756-759

Aijiao Cui, Chip-Hong Chang: Kernel Extraction for Watermarking Combinational Logic Networks. APCCAS 2006: 1023-1026

Shibu Menon, Chip-Hong Chang: A Reconfigurable Multi-Modulus Modulo Multiplier. APCCAS 2006: 1168-1171

A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla: Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis. APCCAS 2006: 1547-1550

A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla: Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm. APCCAS 2006: 1551-1554

Uwe Meyer-Bäse, Jiajia Chen, Chip-Hong Chang, Andrew G. Dempster: A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters. APCCAS 2006: 1555-1558

Chip-Hong Chang, Jiajia Chen, A. Prasad Vinod: Maximum likelihood disjunctive decomposition to reduced multirooted DAG for FIR filter design. ISCAS 2006

Aijiao Cui, Chip-Hong Chang: Stego-signature at logic synthesis level for digital design IP protection. ISCAS 2006

Yajuan He, Chip-Hong Chang: A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier. ISCAS 2006

Ravi Kumar Satzoda, Chip-Hong Chang: A fast kernel for unifying GF(p) and GF(2^m) Montgomery multiplications in a scalable pipelined architecture. ISCAS 2006

Yu Shao, Chip-Hong Chang: A Kalman filter based on wavelet filter-bank and psychoacoustic modeling for speech enhancement. ISCAS 2006

Yu Shao, Chip-Hong Chang: A novel hybrid neuro-wavelet system for robust speech recognition. ISCAS 2006

Yu Shao, Chip-Hong Chang: A generalized perceptual time-frequency subtraction method for speech enhancement. ISCAS 2006

A. Prasad Vinod, Ankita Singla, Chip-Hong Chang: Improved differential coefficients-based low power FIR filters. Part I. Fundamentals. ISCAS 2006

Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: A new integrated approach to the design of low-complexity FIR filters. ISCAS 2006

Zhi-Hui Kong, Kiat Seng Yeo, Chip-Hong Chang: An Ultra Low-power Current-mode Sense Amplifier for Sram Applications. Journal of Circuits, Systems, and Computers 14(5): 939-952 (2005)

Chip-Hong Chang, Zhi Ye, Mingyan Zhang: Fuzzy-ART based adaptive digital watermarking scheme. IEEE Trans. Circuits Syst. Video Techn. 15(1): 65-81 (2005)

Chip-Hong Chang, Pengfei Xu, Rui Xiao, Thambipillai Srikanthan: New adaptive color quantization method based on self-organizing maps. IEEE Transactions on Neural Networks 16(1): 237-249 (2005)

Pengfei Xu, Chip-Hong Chang, Andrew P. Paplinski: Self-organizing topological tree for online vector quantization and data clustering. IEEE Transactions on Systems, Man, and Cybernetics, Part B 35(3): 515-526 (2005)

Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang: A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. IEEE Trans. VLSI Syst. 13(6): 686-695 (2005)

Ravi Kumar Satzoda, Chip-Hong Chang: VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers. Asia-Pacific Computer Systems Architecture Conference 2005: 693-706

Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy: A novel covalent redundant binary Booth encoder. ISCAS (1) 2005: 69-72

Chip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar: A novel multiplexer based truncated array multiplier. ISCAS (1) 2005: 85-88

Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan: A new formulation of fast diminished-one multioperand modulo 2/sup n/+1 adder. ISCAS (1) 2005: 656-659

Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang: A new design method to modulo 2/sup n/-1 squaring. ISCAS (1) 2005: 664-667

Yu Shao, Chip-Hong Chang: A versatile speech enhancement system based on perceptual wavelet denoising. ISCAS (2) 2005: 864-867

Chip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan: A configurable dual moduli multi-operand modulo adder. ISCAS (2) 2005: 1630-1633

Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: I/sup 2/CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination. ISCAS (2) 2005: 1823-1826

Yu Shao, Chip-Hong Chang: Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition. ISCAS (4) 2005: 3833-3836

Yajuan He, Chip-Hong Chang, Jiangmin Gu: An area efficient 64-bit square root carry-select adder for low power applications. ISCAS (4) 2005: 4082-4085

Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang (Eds.): Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings. Lecture Notes in Computer Science 3740, Springer 2005, isbn 3-540-29643-3

Xiaoyun Deng, Chip-Hong Chang, Erwin Brandle: A New Method for Eye Extraction from Facial Image. DELTA 2004: 29-34

Zhi Ye, Chip-Hong Chang: Local Search Method for FIR Filter Coefficients Synthesis. DELTA 2004: 255-260

Zhi Ye, Ravi Kumar Satzoda, Udit Sharma, Naveen Nazimudeen, Chip-Hong Chang: Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture. DELTA 2004: 407-409

Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: HWP: a new insight into canonical signed digit. ISCAS (5) 2004: 201-204

Fei Xu, Chip-Hong Chang, Ching-Chuen Jong: A new contention resolution algorithm for the design of minimal logic depth multiplierless filters. ISCAS (3) 2004: 481-484

Pengfei Xu, Chip-Hong Chang: Self-organizing topological tree. ISCAS (5) 2004: 732-735

Chip-Hong Chang, Pengfei Xu: Frequency sensitive self-organizing maps and its application in color quantization. ISCAS (5) 2004: 804-807

Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang: Design of residue-to-binary converter for a new 5-moduli superset residue number system. ISCAS (2) 2004: 841-844

Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang: A novel hybrid pass logic with static CMOS output drive full-adder cell. ISCAS (5) 2003: 317-320

Jiangmin Gu, Chip-Hong Chang: Ultra low voltage, low power 4-2 compressor for high speed multiplications. ISCAS (5) 2003: 321-324

Shibu Menon, Chip-Hong Chang, Rui Xiao: FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging. ISCAS (2) 2003: 452-455

Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang: Design of a high speed reverse converter for a new 4-moduli set residue number system. ISCAS (4) 2003: 520-523

Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan: New efficient residue-to-binary converters for 4-moduli set {2/sup n/ - 1, 2/sup n/, 2/sup n/ + 1, 2/sup n+1/ - 1}. ISCAS (4) 2003: 536-539

Chip-Hong Chang, Hui Tian, Thambipillai Srikanthan, Chai-Soon Lim: Field programable gate array based architecture for real time image segmentation by region growing algorithm. J. Electronic Imaging 11(4): 469-478 (2002)

Chip-Hong Chang, Rui Xiao, Thambipillai Srikanthan: A MSB-biased self-organizing feature map for still color image compression. APCCAS (2) 2002: 85-88

Chip-Hong Chang, Zhi Ye, Mingyan Zhang: Fuzzy-ART based digital watermarking scheme. APCCAS (1) 2002: 423-426

Hui Tian, Siew Kei Lam, Thambipillai Srikanthan, Chip-Hong Chang: An efficient architecture for adaptive progressive thresholding. APCCAS (1) 2002: 513-516

Rui Xiao, Chip-Hong Chang, Thambipillai Srikanthan: On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization. DELTA 2002: 321-325

Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo: An interconnect optimized floorplanning of a scalar product macrocell. ISCAS (1) 2002: 465-468

Chip-Hong Chang, Bogdan J. Falkowski: Reed-Muller weight and literal vectors for NPN classification. ISCAS (1) 1999: 379-382

Bogdan J. Falkowski, Chip-Hong Chang: Optimization of partially-mixed-polarity Reed-Muller expansions. ISCAS (1) 1999: 383-386

Bogdan J. Falkowski, Chip-Hong Chang: Forward and Inverse Transformations Between Haar Spectra and Ordered Binary Decision Diagrams of Boolean Functions. IEEE Trans. Computers 46(11): 1272-1279 (1997)

Chip-Hong Chang, Bogdan J. Falkowski: Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions. ASP-DAC 1995

Bogdan J. Falkowski, Chip-Hong Chang: Generation of Multi-Polarity Arithmetic Transform from Reduced Representation of Boolean Functions. ISCAS 1995: 2168-2171

Bogdan J. Falkowski, Chip-Hong Chang: Efficient Algorithms for the Calculation of Arithmetic Spectrum from OBDD & Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean Functions. ISCAS 1994: 197-200