Anthony Chan Carusone

Tony Chan Carusone

	2013
c22		Antonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner: F5: Frequency generation and clock distribution. ISSCC 2013: 508-509
	2012
j13		Kentaro Yamamoto, Anthony Chan Carusone: A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs. J. Solid-State Circuits 47(8): 1866-1883 (2012)
j12		Shayan Shahramian, Hemesh Yasotharan, Anthony Chan Carusone: Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters. IEEE Trans. on Circuits and Systems 59-II(6): 326-330 (2012)
c21		Dustin Dunwell, Anthony Chan Carusone, Jared Zerbe, Brian S. Leibowitz, Barry Daly, John C. Eble: A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on. CICC 2012: 1-4
c20		Amer Samarah, Anthony Chan Carusone: A digital phase-locked loop with calibrated coarse and stochastic fine TDC. CICC 2012: 1-4
c19		Ken Chang, Tony Chan Carusone, Ali Sheikholeslami, Bob Payne, Miki Moyal, John Stonick, Hisakatsu Yamaguchi: 10-40 Gb/s I/O design for data communications. ISSCC 2012: 502-503
	2011
j11		Shahriar Shahramian, Adam Hart, Alexander Tomkins, Anthony Chan Carusone, Patrice Garcia, Pascal Chevalier, Sorin P. Voinigescu: Design of a Dual W- and D-Band PLL. J. Solid-State Circuits 46(5): 1011-1022 (2011)
j10		Masum Hossain, Anthony Chan Carusone: 7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS. J. Solid-State Circuits 46(6): 1337-1348 (2011)
j9		Anthony Chan Carusone, Hemesh Yasotharan, Tony Shuo-Chun Kao: CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors. J. Solid-State Circuits 46(8): 1832-1842 (2011)
c18		Kentaro Yamamoto, Anthony Chan Carusone: A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs. CICC 2011: 1-4
	2010
j8		Masum Hossain, Anthony Chan Carusone: 5-10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS. J. Solid-State Circuits 45(3): 524-537 (2010)
j7		Masum Hossain, Anthony Chan Carusone: Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial-Response Channels. IEEE Trans. on Circuits and Systems 57-I(1): 270-279 (2010)
j6		Tony Shuo-Chun Kao, Faisal A. Musa, Anthony Chan Carusone: A 5-Gbit/s CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and Equalization. IEEE Trans. on Circuits and Systems 57-I(11): 2844-2857 (2010)
c17		Anthony Chan Carusone, Hemesh Yasotharan, Tony Shuo-Chun Kao: Progress and trends in multi-Gbps optical receivers with CMOS integrated photodetectors. CICC 2010: 1-8
c16		Dustin Dunwell, Anthony Chan Carusone: Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver. CICC 2010: 1-4
c15		Dustin Dunwell, Anthony Chan Carusone: A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS. ISCAS 2010: 205-208
c14		Masum Hossain, Anthony Chan Carusone: A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS. ISSCC 2010: 158-159
	2009
j5		Anthony Chan Carusone, Yehea Ismail, Un-Ku Moon, Hanspeter Schmid, Wouter A. Serdijn, Gianluca Setti: Guest Editorial Special Issue on ISCAS 2008. IEEE Trans. on Circuits and Systems 56-I(5): 861-864 (2009)
j4		Anthony Chan Carusone, Un-Ku Moon: Introducing Jump-Start Tutorials. IEEE Trans. on Circuits and Systems 56-II(8): 613 (2009)
j3		Anthony Chan Carusone, Horace Cheng, Faisal A. Musa: A 32/16-Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology. IEEE Trans. on Circuits and Systems 56-I(8): 1794-1806 (2009)
c13		Anthony Chan Carusone, Franco Maloberti: An Anti-aliasing Multi-rate SigmaDelta Modulator. ISCAS 2009: 1329-1332
	2008
j2		Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang: Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity. IEEE Trans. on Circuits and Systems 55-II(1): 74-78 (2008)
j1		Jennifer Pham, Anthony Chan Carusone: A Time-Interleaved DeltaSigma-DAC Architecture Clocked at the Nyquist Rate. IEEE Trans. on Circuits and Systems 55-II(9): 858-862 (2008)
c12		Faisal A. Musa, Anthony Chan Carusone: A passive filter aided timing recovery scheme. ISCAS 2008: 3065-3068
	2007
c11		Mike Bichan, Anthony Chan Carusone: Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links. ISCAS 2007: 189-192
	2006
c10		Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang: A bit-serial approximate min-sum LDPC decoder and FPGA implementation. ISCAS 2006
	2005
c9		Anthony Chan Carusone: Jitter equalization for binary baseband communication. ISCAS (2) 2005: 936-939
c8		Jonathan Sewter, Anthony Chan Carusone: A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems. ISCAS (2) 2005: 1521-1524
c7		Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang: Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity. ISCAS (5) 2005: 5194-5197
	2004
c6		Shahriar Shahramian, Tony Chan Carusone: Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization. ISCAS (3) 2004: 489-492
	2003
c5		Faisal A. Musa, Anthony Chan Carusone: Clock recovery in high-speed multilevel serial links. ISCAS (5) 2003: 449-452
c4		Denis Daly, Anthony Chan Carusone: A sigma-delta based open-loop frequency modulator. ISCAS (1) 2003: 929-932
	2002
c3		Anthony Chan Carusone, David A. Johns: Analog filter adaptation using a dithered linear search algorithm. ISCAS (4) 2002: 269-272
c2		Anthony Chan Carusone, David A. Johns: A 5th order Gm-C filter in 0.25 µm CMOS with digitally programmable poles and zeroes. ISCAS (4) 2002: 635-638
	1999
c1		Anthony Chan Carusone, David A. Johns: Obtaining digital gradient signals for analog adaptive filters. ISCAS (3) 1999: 54-57

Coauthor Index

Colors in the list of coauthors

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