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 | 2007 | |
|---|---|---|
| c43 |      | Matthias F. M. Stallmann, Franc Brglez: High-contrast algorithm behavior: observation, hypothesis, and experimental design. Experimental Computer Science 2007: 12 |
| c42 | | Franc Brglez, Jason A. Osborne: Performance testing of combinatorial solvers with isomorph class instances. Experimental Computer Science 2007: 13 |
| 2005 | ||
| j10 | | Franc Brglez, Xiao Yu Li, Matthias F. M. Stallmann: On SAT instance classes and a method for reliable performance experiments with SAT solvers. Ann. Math. Artif. Intell. 43(1): 1-34 (2005) |
| c41 | | Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez: Effective bounding techniques for solving unate and binate covering problems. DAC 2005: 385-390 |
| 2003 | ||
| c40 | | Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez: A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation. SAT 2003: 53-68 |
| 2001 | ||
| j9 | | Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh: Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization. ACM Journal of Experimental Algorithmics 6: 8 (2001) |
| j8 | | Justin E. Harlow III, Franc Brglez: Design of experiments and evaluation of BDD ordering heuristics. STTT 3(2): 193-206 (2001) |
| c39 | | Franc Brglez, Hemang Lavana: A Universal Client for Distributed Networked Design and Computing. DAC 2001: 401-406 |
| 2000 | ||
| j7 | | Franc Brglez: The Scientific Method and Design and Test. IEEE Design & Test of Computers 17(3): 142-144 (2000) |
| c38 | | Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha Chandrakasan: OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. ICCD 2000: 567-570 |
| 1999 | ||
| c37 | | Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh: Heuristics and Experimental Design for Bigraph Crossing Number Minimization. ALENEX 1999: 74-93 |
| c36 | | Franc Brglez, Rolf Drechsler: Design of experiments in CAD: context and new data sets for ISCAS'99. ISCAS (6) 1999: 424-427 |
| c35 | | Debabrata Ghosh, Franc Brglez: Equivalence classes of circuit mutants for experimental design. ISCAS (6) 1999: 432-435 |
| c34 | | Hemang Lavana, Franc Brglez, Robert B. Reese: User-configurable experimental design flows on the web: the ISCAS'99 experiments. ISCAS (6) 1999: 440-443 |
| c33 | | Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh: Evaluating iterative improvement heuristics for bigraph crossing minimization. ISCAS (6) 1999: 444-447 |
| c32 | | Justin E. Harlow III, Franc Brglez: Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. ISCAS (6) 1999: 452-455 |
| 1998 | ||
| j6 | | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez: Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. ACM Trans. Design Autom. Electr. Syst. 3(2): 285-307 (1998) |
| c31 | | Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III: Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. DATE 1998: 656-663 |
| c30 | | Justin E. Harlow III, Franc Brglez: Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. FMCAD 1998: 64-81 |
| c29 | | Justin E. Harlow III, Franc Brglez: Design of experiments in BDD variable ordering: lessons learned. ICCAD 1998: 646-652 |
| 1997 | ||
| c28 | | Hemang Lavana, Amit Khetawat, Franc Brglez, Krzysztof Kozminski: Executable Workflows: A Paradigm for Collaborative Design on the Internet. DAC 1997: 553-558 |
| c27 | | Hemang Lavana, Amit Khetawat, Franc Brglez: Internet-based workflows: a paradigm for dynamically reconfigurable desktop environments. GROUP 1997: 204-213 |
| c26 | | Nevin Kapur, Debabrata Ghosh, Franc Brglez: Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions. ISPD 1997: 136-143 |
| 1996 | ||
| j5 | | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez: Fast true delay estimation during high level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1088-1105 (1996) |
| 1995 | ||
| c25 | | Clay Gloster, Franc Brglez: Partial scan selection for user-specified fault coverage. EURO-DAC 1995: 111-116 |
| c24 | | Roman Kuznar, Franc Brglez: PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. ICCAD 1995: 644-649 |
| c23 | | Andrej Zemva, Franc Brglez: Detectable perturbations: a paradigm for technology-specific multi-fault test generation. VTS 1995: 350-357 |
| 1994 | ||
| c22 | | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez: Clock Period Optimization During Resource Sharing and Assignment. DAC 1994: 195-200 |
| c21 | | Roman Kuznar, Franc Brglez, Baldomir Zajc: Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect. DAC 1994: 238-243 |
| c20 | | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez: Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. DAC 1994: 491-496 |
| c19 |  | Bernhard Rohfleisch, Franc Brglez: Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. EDAC-ETC-EUROASIC 1994: 87-93 |
| c18 | | Andrej Zemva, Franc Brglez, Krzysztof Kozminski, Baldomir Zajc: A Functionality Fault Model: Feasibility and Applications. EDAC-ETC-EUROASIC 1994: 152-158 |
| c17 | | Roman Kuznar, Baldomir Zajc, Franc Brglez: A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions. EURO-DAC 1994: 271-276 |
| c16 | | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez: Provably correct high-level timing analysis without path sensitization. ICCAD 1994: 736-742 |
| 1993 | ||
| j4 | | Franc Brglez: A D&T Special Report on ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema? IEEE Design & Test of Computers 10(3): 87-91 (1993) |
| j3 | | Subhrajit Bhattacharya, Franc Brglez, Sujit Dey: Transformations and resynthesis for testability of RT-level control-data path specifications. IEEE Trans. VLSI Syst. 1(3): 304-318 (1993) |
| c15 | | Roman Kuznar, Franc Brglez, Krzysztof Kozminski: Cost Minimization of Partitions into Multiple Devices. DAC 1993: 315-320 |
| 1992 | ||
| j2 | | John D. Calhoun, Franc Brglez: A framework and method for hierarchical test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 45-67 (1992) |
| c14 | | Ulf Schlichtmann, Franc Brglez, Michael Hermann: Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. DAC 1992: 374-379 |
| c13 | | Matthew Melton, Franc Brglez: Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults. ITC 1992: 389-398 |
| 1991 | ||
| c12 | | Sujit Dey, Franc Brglez, Gershon Kedem: Partitioning Sequential Circuits for Logic Optimization. ICCD 1991: 70-76 |
| c11 | | Sujit Dey, Franc Brglez, Gershon Kedem: Identification and Resynthesis of Pipelines in Sequential Networks. VLSI 1991: 439-449 |
| 1990 | ||
| c10 | | Sujit Dey, Franc Brglez, Gershon Kedem: Corolla Based Circuit Partitioning and Resynthesis. DAC 1990: 607-612 |
| 1989 | ||
| c9 | | Franc Brglez, Gershon Kedem, Clay Gloster: Hardware-Based Weighted Random Pattern Generation for Boundary Scan. ITC 1989: 264-274 |
| c8 | | John D. Calhoun, Franc Brglez: A Framework and Method for Hierarchical Test Generation. ITC 1989: 480-490 |
| 1988 | ||
| c7 | | |
| 1987 | ||
| j1 | | Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory: Testability-Driven Random Test-Pattern Generation. IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 1082-1087 (1987) |
| c6 | | |
| 1985 | ||
| c5 | | |
| c4 | | |
| 1984 | ||
| c3 | | Franc Brglez, Philip Pownall, Robert Hum: Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing. ITC 1984: 705-712 |
| 1981 | ||
| c2 | | G. Sakauye, Anna Lubiw, J. Royle, R. Epplett, Jeffrey Tweedale, E. S. Y. Shew, E. Attfield, Franc Brglez, Philip S. Wilcox: A set of programs for MOS design. DAC 1981: 435-442 |
| c1 | | |
Colors in the list of coauthors
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