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Gordon J. Brebner
2010 – today
- 2013
[j5]Christopher E. Neely, Gordon J. Brebner, Weijia Shang: ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems. TRETS 6(1): 5 (2013)- 2012
- [c41]
- [c40]Thilan Ganegedara, Viktor K. Prasanna, Gordon J. Brebner: Optimizing packet lookup in time and space on FPGA. FPL 2012: 270-276
- 2011
- [c39]Michael Attig, Gordon J. Brebner: 400 Gb/s Programmable Packet Parsing on a Single FPGA. ANCS 2011: 12-23
- [c38]Gordon J. Brebner: Reconfigurable Computing for High Performance Networking Applications. ARC 2011: 1
- 2010
- [c37]Christopher E. Neely, Gordon J. Brebner, Weijia Shang: ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs. FCCM 2010: 141-148
- [c36]Christopher E. Neely, Gordon J. Brebner, Weijia Shang: Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration. FPL 2010: 513-518
2000 – 2009
- 2009
- [c35]Gordon J. Brebner: Packets everywhere: The great opportunity for field programmable technology. FPT 2009: 1-10
- 2008
- [j4]Shuvra S. Bhattacharyya, Gordon J. Brebner, Jörn W. Janneck, Johan Eker, Carl von Platen, Marco Mattavelli, Mickaël Raulet: OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems. SIGARCH Computer Architecture News 36(5): 29-35 (2008)
- 2007
- [j3]Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong: Editorial for the Special Issue on Field Programmable Technology. VLSI Signal Processing 47(1): 1-2 (2007)
- 2006
- [c34]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
- [c33]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
- [c32]Chidamber Kulkarni, Gordon J. Brebner: Memory centric thread synchronization on platform FPGAs. DATE 2006: 959-964
- [c31]Michael Attig, Gordon J. Brebner: Systematic Characterization of Programmable Packet Processing Pipelines. FCCM 2006: 195-204
- [c30]Jike Chong, Chidamber Kulkarni, Gordon J. Brebner: Building a flexible and scalable DRAM interface for networking applications on FPGAs. FPGA 2006: 233
- [c29]Chidamber Kulkarni, Gordon J. Brebner: Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor. FPL 2006: 1-6
- [e3]Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich (Eds.): Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006. Dagstuhl Seminar Proceedings 06141, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006
- 2005
- [c28]Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely: Mutable Codesign for Embedded Protocol Processing. FCCM 2005: 299-300
- [c27]Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely: Mutable Codesign for Embedded Protocol Processing. FPL 2005: 51-56
- [e2]Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong (Eds.): Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, FPT 2005, 11-14 December 2005, Singagore. IEEE 2005, ISBN 0-7803-9407-0
- 2004
- [c26]Gordon J. Brebner, Philip James-Roxby, Eric Keller, Chidamber Kulkarni: Hyper-Programmable Architectures for Adaptable Networked Systems. ASAP 2004: 328-338
- [c25]Chidamber Kulkarni, Gordon J. Brebner, Graham Schelle: Mapping a domain specific language to a platform FPGA. DAC 2004: 924-927
- [c24]Philip James-Roxby, Gordon J. Brebner, Dennis Bemmann: Time-Critical Software Deceleration in an FCCM. FCCM 2004: 3-12
- [c23]Gordon J. Brebner: Programmable Logic Has More Computational Power than Fixed Logic. FPL 2004: 404-413
- [c22]Philip James-Roxby, Gordon J. Brebner: Multithreading in a Hyper-programmable Platform for Networked Systems. FPL 2004: 1017-1021
- [c21]Eric Keller, Gordon J. Brebner: Programming a hyper-programmable architecture for networked systems. FPT 2004: 1-8
- 2003
- [c20]
- [c19]
- [c18]
- 2002
- [c17]
- [c16]
- [c15]
- 2001
- [c14]
- [c13]
- [e1]Gordon J. Brebner, Roger Woods (Eds.): Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings. Lecture Notes in Computer Science 2147, Springer 2001, ISBN 3-540-42499-7
1990 – 1999
- 1999
- [c12]Gordon J. Brebner, Neil W. Bergmann: Reconfigurable Computing in Remote and Harsh Environments. FPL 1999: 195-204
- [c11]Tim Kempster, Gordon J. Brebner, Peter Thanisch: A Transactional Approach to Configuring Telecommunications Services. Databases in Telecommunications 1999: 40-53
- 1998
- [c10]Gordon J. Brebner, Rob Pooley: ECOLE: A Configurable Environment for a Local Optical Network of Workstations. CANPC 1998: 45-58
- [c9]
- [c8]
- [c7]
- [c6]
- 1997
- [c5]
- [c4]Gordon J. Brebner: Automatc identification of swappable logic units in XC6200 circuitry. FPL 1997: 173-182
- 1996
- [c3]
- 1995
- [c2]
- 1993
- [j2]Gordon J. Brebner: A CCS-based Investigation of Deadlock in a Multi-process Electronic Mail System. Formal Asp. Comput. 5(5): 467-478 (1993)
- [j1]Gordon J. Brebner: Configurable array logic circuits for computing network error detection codes. VLSI Signal Processing 6(2): 101-117 (1993)
1980 – 1989
- 1981
- [c1]Leslie G. Valiant, Gordon J. Brebner: Universal Schemes for Parallel Communication. STOC 1981: 263-277
Coauthor Index
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last updated on 2013-10-02 10:58 CEST by the dblp team