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Daniel Brand
2010 – today
- 2010
[j17]Marcio Buss, Daniel Brand, Vugranam C. Sreedhar, Stephen A. Edwards: A novel analysis space for pointer analysis and its application for bug finding. Sci. Comput. Program. 75(11): 921-942 (2010)
2000 – 2009
- 2008
- [c17]Marcio Buss, Daniel Brand, Vugranam C. Sreedhar, Stephen A. Edwards: Flexible pointer analysis using assign-fetch graphs. SAC 2008: 234-239
- 2007
- [c16]Daniel Brand, Marcio Buss, Vugranam C. Sreedhar: Evidence-Based Analysis and Inferring Preconditions for Bug Detection. ICSM 2007: 44-53
- 2002
- [j16]John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin: Early analysis tools for system-on-a-chip design. IBM Journal of Research and Development 46(6): 691-708 (2002)
- 2000
- [j15]John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan: LSS: A system for production logic synthesis. IBM Journal of Research and Development 44(1): 157-166 (2000)
- [c15]
1990 – 1999
- 1998
- [j14]Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok: Don't cares in synthesis: theoretical pitfalls and practical solutions. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 285-304 (1998)
- 1996
- [j13]Leon Stok, David S. Kung, Daniel Brand, Anthony D. Drumm, Andrew J. Sullivan, Lakshmi N. Reddy, Nathaniel Hieter, David J. Geiger, Han Hsun Chao, Peter J. Osler: BooleDozer: Logic synthesis for ASICs. IBM Journal of Research and Development 40(4): 407-430 (1996)
- [c14]Daniel Brand, Chandramouli Visweswariah: Inaccuracies in power estimation during logic synthesis. ICCAD 1996: 388-394
- 1995
- [c13]
- [c12]Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash: Efficient use of large don't cares in high-level and logic synthesis. ICCAD 1995: 272-278
- 1994
- [j12]Daniel Brand, Vijay S. Iyengar: Identification of redundant delay faults. IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 553-565 (1994)
- [c11]Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain: Incremental synthesis. ICCAD 1994: 14-18
- [c10]Daniel Brand, Robert F. Damiano, Lukas P. P. P. van Ginneken, Anthony D. Drumm: In the Driver's Seat of BooleDozer. ICCD 1994: 518-521
- 1993
- [j11]Daniel Brand, Tsutomu Sasao: Minimization of AND-EXOR Expressions Using Rewrite Rules. IEEE Trans. Computers 42(5): 568-576 (1993)
- [j10]Daniel Brand: Exhaustive simulation need not require an exponential number of tests. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1635-1641 (1993)
- [c9]
- 1992
- [c8]Daniel Brand: Exhaustive simulation need not require an exponential number of tests. ICCAD 1992: 98-101
- [c7]Daniel Brand, Vijay S. Iyengar: Identification of Single Gate Delay Fault Redundancies. ICCD 1992: 24-28
1980 – 1989
- 1989
- [c6]Daniel Brand, Vijay S. Iyengar: Synthesis of Pseudo-Random Pattern Testable Designs. ITC 1989: 501-508
- 1988
- [j9]Daniel Brand, Vijay S. Iyengar: Timing Analysis Using Functional Analysis. IEEE Trans. Computers 37(10): 1309-1315 (1988)
- 1986
- [j8]Daniel Brand: Detecting Sneak Paths in Transistor Networks. IEEE Trans. Computers 35(3): 274-278 (1986)
- [c5]William H. Joyner Jr., Louise Trevillyan, Daniel Brand, Theresa A. Nix, Steven C. Gundersen: Technology adaption in logic synthesis. DAC 1986: 94-100
- 1985
- [c4]John A. Darringer, Daniel Brand, William H. Joyner Jr., Louise Trevillyan, John V. Gerbi: Production logic synthesis. ACM Conference on Computer Science 1985: 13-16
- 1984
- [j7]John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan: LSS: A System for Production Logic Synthesis. IBM Journal of Research and Development 28(5): 537-545 (1984)
- 1983
- [j6]Daniel Brand, Pitro Zafiropulo: On Communicating Finite-State Machines. J. ACM 30(2): 323-342 (1983)
- [j5]Daniel Brand: Redundancy and Don't Cares in Logic Synthesis. IEEE Trans. Computers 32(10): 947-952 (1983)
1970 – 1979
- 1979
- [c3]William C. Carter, William H. Joyner Jr., Daniel Brand: Symbolic simulation for correct machine design. DAC 1979: 280-286
- 1978
- [j4]Daniel Brand, William H. Joyner Jr.: Verification of Protocols Using Symbolic Execution. Computer Networks 2: 351-360 (1978)
- [j3]
- [c2]William H. Joyner Jr., William C. Carter, Daniel Brand: Using Machine Descriptions in Program Verification. Jerusalem Conference on Information Technology 1978: 515-522
- 1976
- [j2]
- [c1]
- 1975
- [j1]
Coauthor Index
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last updated on 2012-09-23 01:31 CEST by the dblp team