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Jayanta Bhadra
Jay Bhadra
2010 – today
- 2013
[c34]Wen Chen, Li-C. Wang, Jay Bhadra, Magdy S. Abadir: Simulation knowledge extraction and reuse in constrained random processor verification. DAC 2013: 120- [c33]Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra: Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step. DATE 2013: 454-457
- 2012
- [j7]Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Aarti Gupta: Introduction to special section on verification challenges in the concurrent world. ACM Trans. Design Autom. Electr. Syst. 17(3): 19 (2012)
- [c32]Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra: An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology. ASP-DAC 2012: 163-168
- [c31]Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir: Novel test detection to improve simulation efficiency - A commercial experiment. ICCAD 2012: 101-108
- 2011
- [c30]Oswaldo Olivo, Sandip Ray, Jayanta Bhadra, Vivekananda M. Vedula: A Unified Formal Framework for Analyzing Functional and Speed-path Properties. MTV 2011: 44-45
- [e4]Magdy S. Abadir, Jay Bhadra, Li-C. Wang (Eds.): 12th International Workshop on Microprocessor Test and Verification, MTV 2011, Austin, TX, USA, December 5-7, 2011. IEEE 2011, ISBN 978-1-4577-2101-4
- 2010
- [c29]Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronald Syzdek: Modeling and verification of industrial flash memories. ISQED 2010: 705-712
- [c28]Po-Hsien Chang, Li-C. Wang, Jayanta Bhadra: A kernel-based approach for functional test program generation. ITC 2010: 164-173
- [c27]Sandip Ray, Jayanta Bhadra: Innovative practices session 7C: Verification and testing challenges in high-level synthesis. VTS 2010: 250
- [e3]Magdy S. Abadir, Jay Bhadra, Li-C. Wang (Eds.): 11th International Workshop on Microprocessor Test and Verification, MTV 2010, Austin, TX, USA, December 13-15, 2010. IEEE 2010, ISBN 978-0-7695-4354-3
2000 – 2009
- 2009
- [c26]Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra: Accelerating multi-party scheduling for transaction-level modeling. ACM Great Lakes Symposium on VLSI 2009: 339-344
- [c25]Huan-Kai Peng, Charles H.-P. Wen, Jayanta Bhadra: On soft error rate analysis of scaled CMOS designs - A statistical perspective. ICCAD 2009: 157-163
- [c24]Mrinal Bose, Prashant Naphade, Jayanta Bhadra, Hillel Miller: An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. ISQED 2009: 377-381
- [c23]Vyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose, Jayanta Bhadra: Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models. ISVLSI 2009: 241-246
- [c22]Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra: Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning. ITC 2009: 1-8
- [c21]Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen, Mrinal Bose, Jayanta Bhadra: Portable simulation/emulation stimulus on an industrial-strength SoC. ITC 2009: 1
- [c20]Vyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra: Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling. MTV 2009: 3-8
- 2008
- [j6]Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir: Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications. IEEE Trans. VLSI Syst. 16(4): 388-396 (2008)
- 2007
- [j5]Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang: Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. IEEE Design & Test of Computers 24(2): 110-111 (2007)
- [j4]Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray: A Survey of Hybrid Techniques for Functional Verification. IEEE Design & Test of Computers 24(2): 112-122 (2007)
- [c19]Sandip Ray, Jayanta Bhadra: A Mechanized Refinement Framework for Analysis of Custom Memories. FMCAD 2007: 239-242
- [c18]Charles H.-P. Wen, Li-C. Wang, Jayanta Bhadra: An incremental learning framework for estimating signal controllability in unit-level verification. ICCAD 2007: 250-257
- [c17]Onur Guzey, Li-C. Wang, Jayanta Bhadra: Enhancing signal controllability in functional test-benches through automatic constraint extraction. ITC 2007: 1-10
- [e2]Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra (Eds.): Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA. IEEE Computer Society 2007, ISBN 978-0-7695-3241-7
- 2006
- [c16]Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir: Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV 2006: 33-36
- [c15]Jayanta Bhadra, Ekaterina Trofimova, Leonard J. Giordano, Magdy S. Abadir: A Trace-Driven Validation Methodology for Multi-Processor SOCS. SoCC 2006: 145-148
- [e1]Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra (Eds.): Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA. IEEE Computer Society 2006, ISBN 978-0-7695-2839-7
- 2005
- [j3]Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham: A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor. Formal Methods in System Design 27(1-2): 67-112 (2005)
- [c14]Himyanshu Anand, Jayanta Bhadra, Alper Sen, Magdy S. Abadir, Kenneth G. Davis: Establishing latch correspondence for embedded circuits of PowerPC microprocessors. HLDVT 2005: 37-44
- [c13]Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova: Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. MTV 2005: 111-118
- 2004
- [j2]Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir: Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. IEEE Design & Test of Computers 21(6): 494-502 (2004)
- [c12]Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra: Formal Verification of a System-on-Chip Using Computation Slicing. ITC 2004: 810-819
- [c11]Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design 2004: 115-
- 2003
- [j1]Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri: A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. J. Electronic Testing 19(2): 149-160 (2003)
- [c10]Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir: A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. MTV 2003: 32-37
- [c9]Kyoil Kim, Jacob A. Abraham, Jayanta Bhadra: Model Checking of Security Protocols with Pre-configuration. WISA 2003: 1-15
- 2002
- [c8]Jayanta Bhadra, Narayanan Krishnamurthy: Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. ITC 2002: 213-222
- [c7]Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra: Program Slicing for Hierarchical Test Generation. VTS 2002: 237-246
- [c6]Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS 2002: 275-280
- 2001
- [c5]Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir: Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. CHARME 2001: 386-402
- [c4]Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham: Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE 2001: 514-519
- [c3]Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir: A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications. HLDVT 2001: 134-141
- 2000
- [c2]Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham: Automatic Validation Test Generation Using Extracted Control Models. VLSI Design 2000: 312-
1990 – 1999
- 1999
- [c1]Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham: Improving Witness Search Using Orders on States. ICCD 1999: 452-457
Coauthor Index
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last updated on 2013-05-29 01:54 CEST by the dblp team