Valeria Bertacco

William Arthur, Biruk Mammo, Ricardo Rodriguez, Todd M. Austin, Valeria Bertacco: Schnauzer: scalable profiling for likely security bug sites. CGO 2013: 1-11

Andrew DeOrio, Qingkun Li, Matthew Burgess, Valeria Bertacco: Machine learning-based anomaly detection for post-silicon bug diagnosis. DATE 2013: 491-496

Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, A. M. Kaushik, Hiren D. Patel: On the use of GP-GPUs for accelerating compute-intensive EDA applications. DATE 2013: 1357-1366

Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David Blaauw, Jin Hu, Gregory K. Chen: A Reliable Routing Architecture and Algorithm for NoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 31(5): 726-739 (2012)

Nicola Bombieri, Sara Vinco, Valeria Bertacco, Debapriya Chatterjee: SystemC simulation on GP-GPUs: CUDA vs. OpenCL. CODES+ISSS 2012: 343-352

Sara Vinco, Debapriya Chatterjee, Valeria Bertacco, Franco Fummi: SAGA: SystemC acceleration on GPU architectures. DAC 2012: 115-120

Valeria Bertacco: Humans for EDA and EDA for humans. DAC 2012: 729-733

Debapriya Chatterjee, Anatoly Koyfman, Ronny Morad, Avi Ziv, Valeria Bertacco: Checking architectural outputs instruction-by-instruction on acceleration platforms. DAC 2012: 955-961

Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco: Approximating checkers for simulation acceleration. DATE 2012: 153-158

Andrea Pellegrini, Robert Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita V. Adve, Todd M. Austin, Valeria Bertacco: CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions. DATE 2012: 1106-1109

Andrew DeOrio, Jialin Li, Valeria Bertacco: Bridging pre- and post-silicon debugging with BiPeD. ICCAD 2012: 95-100

Rawan Abdel-Khalek, Valeria Bertacco: Functional post-silicon diagnosis and debug for networks-on-chip. ICCAD 2012: 557-563

Andrea Pellegrini, Joseph L. Greathouse, Valeria Bertacco: Viper: Virtual pipelines for enhanced reliability. ISCA 2012: 344-355

Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, Valeria Bertacco: Comprehensive online defect diagnosis in on-chip networks. VTS 2012: 44-49

Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco: Gate-Level Simulation with GPU Computing. ACM Trans. Design Autom. Electr. Syst. 16(3): 30 (2011)

Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh, Valeria Bertacco: ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment. PACT 2011: 298-309

Joseph L. Greathouse, Chelsea LeBlanc, Todd M. Austin, Valeria Bertacco: Highly scalable distributed dataflow analysis. CGO 2011: 277-288

Andrew DeOrio, Konstantinos Aisopos, Valeria Bertacco, Li-Shiuan Peh: DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips. DAC 2011: 912-917

Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini: ReliNoC: A reliable network for priority-based on-chip communication. DATE 2011: 667-672

Andrea Pellegrini, Valeria Bertacco: Cardio: Adaptive CMPs for reliability through dynamic introspective operation. HLDVT 2011: 98-105

Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco: Simulation-based signal selection for state restoration in silicon debug. ICCAD 2011: 595-601

Andrew DeOrio, Daya Shanker Khudia, Valeria Bertacco: Post-silicon bug diagnosis with inconsistent executions. ICCAD 2011: 755-761

Rawan Abdel-Khalek, Ritesh Parikh, Andrew DeOrio, Valeria Bertacco: Functional correctness for CMP interconnects. ICCD 2011: 352-359

Ritesh Parikh, Valeria Bertacco: Formally enhanced runtime verification to ensure NoC functional correctness. MICRO 2011: 410-419

Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini: A distributed and topology-agnostic approach for on-line NoC testing. NOCS 2011: 113-120

Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko: Logic synthesis and circuit customization using extensive external don't-cares. ACM Trans. Design Autom. Electr. Syst. 15(3) (2010)

Valeria Bertacco: Post-silicon debugging for multi-core designs. ASP-DAC 2010: 255-258

Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor: Bridging pre-silicon verification and post-silicon validation. DAC 2010: 94-95

Andrew DeOrio, Valeria Bertacco: Electronic design automation for social networks. DAC 2010: 621-622

Andrea Pellegrini, Valeria Bertacco, Todd M. Austin: Fault-based attack of RSA authentication. DATE 2010: 855-860

Valeria Bertacco: Verification Failures: What to Do When Things Go Wrong. Haifa Verification Conference 2010: 23

Andrea Pellegrini, Valeria Bertacco: Application-Aware diagnosis of runtime hardware faults. ICCAD 2010: 487-492

Debapriya Chatterjee, Valeria Bertacco: EQUIPE: Parallel equivalence checking with GP-GPUs. ICCD 2010: 486-493

Rawan Abdel-Khalek, Valeria Bertacco: SoCGuard: A runtime verification solution for the functional correctness of SoCs. VLSI-SoC 2010: 49-54

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair. Lecture Notes in Electrical Engineering 32, Springer 2009, isbn 978-1-4020-9364-7, pp. 3-185

Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco: Incremental Verification with Error Detection, Diagnosis, and Visualization. IEEE Design & Test of Computers 26(2): 34-43 (2009)

Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco: A Flexible Software-Based Framework for Online Detection of Hardware Defects. IEEE Trans. Computers 58(8): 1063-1079 (2009)

Andrew DeOrio, Adam Bauserman, Valeria Bertacco, Beth Isaksen: Inferno: Streamlining Verification With Inferred Semantics. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 728-741 (2009)

Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco: Event-driven gate-level simulation with GP-GPUs. DAC 2009: 557-562

Andrew DeOrio, Valeria Bertacco: Human computing for EDA. DAC 2009: 621-622

Valeria Bertacco: Debugging strategies for mere mortals. DAC 2009: 635-638

David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester: Vicis: a reliable network for unreliable silicon. DAC 2009: 812-817

David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw: A highly resilient routing algorithm for fault-tolerant NoCs. DATE 2009: 21-26

Kai-Hui Chang, Valeria Bertacco, Igor L. Markov: Customizing IP cores for system-on-chip designs using extensive external don't-cares. DATE 2009: 582-585

Ilya Wagner, Valeria Bertacco: Caspar: Hardware patching for multicore processors. DATE 2009: 658-663

Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco: GCS: High-performance gate-level simulation with GPGPUs. DATE 2009: 1332-1337

J. Hao, Valeria Bertacco: PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis. HLDVT 2009: 54-59

Debapriya Chatterjee, Valeria Bertacco: Activity-based refinement for abstraction-guided simulation. HLDVT 2009: 146-153

Andrew DeOrio, Ilya Wagner, Valeria Bertacco: Dacota: Post-silicon validation of the memory subsystem in multi-core designs. HPCA 2009: 405-416

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Automating Postsilicon Debugging and Repair. IEEE Computer 41(7): 47-54 (2008)

Todd M. Austin, Valeria Bertacco, Scott A. Mahlke, Yu Cao: Reliable Systems on Unreliable Fabrics. IEEE Design & Test of Computers 25(4): 322-332 (2008)

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: SafeResynth: A new technique for physical synthesis. Integration 41(4): 544-556 (2008)

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Fixing Design Errors With Counterexamples and Resynthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 184-188 (2008)

Ilya Wagner, Valeria Bertacco, Todd M. Austin: Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 380-393 (2008)

Stephen Plaza, Igor L. Markov, Valeria Bertacco: Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2107-2119 (2008)

Stephen Plaza, Igor L. Markov, Valeria Bertacco: Random Stimulus Generation using Entropy and XOR Constraints. DATE 2008: 664-669

Ilya Wagner, Valeria Bertacco: MCjammer: Adaptive Verification for Multi-core Designs. DATE 2008: 670-675

Shireesh Verma, Srinath Atluri, Valeria Bertacco, Mark Glasser, Badri Gopalan, Sharon Rosenberg: Panel: Software practices for verification/testbench management. HLDVT 2008: 35-37

Ilya Wagner, Valeria Bertacco: Reversi: Post-silicon validation system for modern microprocessors. ICCD 2008: 307-314

Andrew DeOrio, Adam Bauserman, Valeria Bertacco: Post-silicon verification for cache coherence. ICCD 2008: 348-355

Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin: CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. ICCD 2008: 363-370

Stephen Plaza, Igor L. Markov, Valeria Bertacco: Optimizing non-monotonic interconnect using functional simulation and logic restructuring. ISPD 2008: 95-102

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Reap what you sow: spare cells for post-silicon metal fix. ISPD 2008: 103-110

Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie: Testudo: Heavyweight security analysis via statistical sampling. MICRO 2008: 117-128

Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky: Architecting a reliable CMP switch architecture. TACO 4(1) (2007)

Kai-Hui Chang, Valeria Bertacco, Igor L. Markov: Simulation-Based Bug Trace Minimization With BMC-Based Refinement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 152-165 (2007)

Ilya Wagner, Valeria Bertacco, Todd M. Austin: Microprocessor Verification via Feedback-Adjusted Markov Models. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1126-1138 (2007)

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Postplacement rewiring by exhaustive search for functional symmetries. ACM Trans. Design Autom. Electr. Syst. 12(3) (2007)

Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Node Mergers in the Presence of Don't Cares. ASP-DAC 2007: 414-419

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Safe Delay Optimization for Physical Synthesis. ASP-DAC 2007: 628-633

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Fixing Design Errors with Counterexamples and Resynthesis. ASP-DAC 2007: 944-949

Ilya Wagner, Valeria Bertacco: Engineering trust with semantic guardians. DATE 2007: 743-748

Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin: Low-cost protection for SER upsets and silicon defects. DATE 2007: 1146-1151

Kai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor L. Markov: Automatic error diagnosis and correction for RTL designs. HLDVT 2007: 65-72

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Automating post-silicon debugging and repair. ICCAD 2007: 91-98

Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco: InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. ISQED 2007: 487-494

Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco: Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. MICRO 2007: 97-108

Andrew DeOrio, Adam Bauserman, Valeria Bertacco: Chico: An On-chip Hardware Checker for Pipeline Control Logic. MTV 2007: 91-97

Valeria Bertacco: Scalable Hardware Verification with Symbolic Simulation. Springer 2006, isbn 978-0-387-24411-2, pp. I-XX, 1-177

Ilya Wagner, Valeria Bertacco, Todd M. Austin: Depth-driven verification of simultaneous interfaces. ASP-DAC 2006: 442-447

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin: Ultra low-cost defect protection for microprocessor pipelines. ASPLOS 2006: 73-82

Ilya Wagner, Valeria Bertacco, Todd M. Austin: Shielding against design flaws with field repairable control logic. DAC 2006: 344-347

Smitha Shyam, Valeria Bertacco: Distance-guided hybrid verification with GUIDO. DATE 2006: 1211-1216

Valeria Bertacco: Distance-Guided Hybrid Verification with GUIDO. HLDVT 2006: 151

Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky: BulletProof: a defect-tolerant CMP switch architecture. HPCA 2006: 5-16

Beth Isaksen, Valeria Bertacco: Verification through the principle of least astonishment. ICCAD 2006: 860-867

Valeria Bertacco: Formal verification for real-world designs. SBCCI 2006: 5

Valeria Bertacco: Low maintenance verification. SBCCI 2006: 12

Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge: Opportunities and challenges for better than worst-case design. ASP-DAC 2005: 2-7

Stephen Plaza, Valeria Bertacco: STACCATO: disjoint support decompositions from BDDs through symbolic kernels. ASP-DAC 2005: 276-279

Ilya Wagner, Valeria Bertacco, Todd M. Austin: StressTest: an automatic approach to test generation via activity monitors. DAC 2005: 783-788

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. ICCAD 2005: 56-63

Kai-Hui Chang, Valeria Bertacco, Igor L. Markov: Simulation-based bug trace minimization with BMC-based refinement. ICCAD 2005: 1045-1051

Todd M. Austin, Valeria Bertacco: Deployment of Better Than Worst-Case Design: Solutions and Needs. ICCD 2005: 550-558

Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge: Circuit-aware architectural simulation. DAC 2004: 305-310

Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge: Microarchitectural power modeling techniques for deep sub-micron microprocessors. ISLPED 2004: 212-217

Valeria Bertacco, Kunle Olukotun: Efficient state representation for symbolic simulation. DAC 2002: 99-104

Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long: Smart Simulation Using Collaborative Formal and Simulation Engines. ICCAD 2000: 120-126

Valeria Bertacco, Maurizio Damiani, Stefano Quer: Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits. DAC 1999: 391-396

Valeria Bertacco, Maurizio Damiani: The disjunctive decomposition of logic functions. ICCAD 1997: 78-82

Valeria Bertacco, Maurizio Damiani: Boolean Function Representation Using Parallel-Access Diagrams. Great Lakes Symposium on VLSI 1996: 112-117

Valeria Bertacco, Maurizio Damiani: Boolean Function Representation Based on Disjoint-Support Decompositions. ICCD 1996: 27-