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Jürgen Becker
2010 – today
- 2013
[j43]Massimo Conti, Elmar U. K. Melcher, Jürgen Becker, Alisson Vasconcelos De Brito, Oliver Sander: Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011). Int. J. Reconfig. Comp. 2013 (2013)- [j42]René Cumplido, Peter Athanas, Jürgen Becker: Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). Int. J. Reconfig. Comp. 2013 (2013)
- [j41]Oliver Sander, Alexander Klimm, Jürgen Becker: Hardware Support for Authentication in Cyber Physical Systems. it - Information Technology 55(1): 19- (2013)
- [j40]Diana Göhringer, Lukas Meder, Oliver Oey, Jürgen Becker: Reliable and adaptive network-on-chip architectures for cyber physical systems. ACM Trans. Embedded Comput. Syst. 12(1s): 51 (2013)
- [j39]Neil W. Bergmann, Sunil Shukla, Jürgen Becker: QUKU: A dual-layer reconfigurable architecture. ACM Trans. Embedded Comput. Syst. 12(1s): 63 (2013)
- [j38]Nikolaos S. Voros, Michael Hübner, Jürgen Becker, Matthias Kühnle, Florian Thoma, Arnaud Grasset, Paul Brelet, Philippe Bonnot, Fabio Campi, Eberhard Schüler, Henning Sahlbach, Sean Whitty, Rolf Ernst, Enrico Billich, Claudia Tischendorf, Ulrich Heinkel, Frank Ieromnimon, Dimitrios Kritharidis, Axel Schneider, Joachim Knäblein, Wolfram Putzke-Röming: MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems. ACM Trans. Embedded Comput. Syst. 12(3): 70 (2013)
- [j37]Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner, Jürgen Becker: JITPR: A framework for supporting fast application's implementation onto FPGAs. TRETS 6(2): 7 (2013)
- [j36]Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker: Virtual networks - distributed communication resource management. TRETS 6(2): 8 (2013)
- [c223]Cuong Pham-Quoc, Jan Heisswolf, Stephan Werner, Zaid Al-Ars, Jürgen Becker, Koen Bertels: Hybrid interconnect design for heterogeneous hardware accelerators. DATE 2013: 843-846
- [c222]Michael Dreschmann, Oliver Sander, Alexander Klimm, Christoph Roth, Jürgen Becker: Addiguration: Exploring configuration behavior of Spartan-3 devices. ReCoSoC 2013: 1-6
- [c221]Christoph Roth, Harald Bucher, Simon Reder, Oliver Sander, Jürgen Becker: Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction. ReCoSoC 2013: 1-8
- [c220]Ali Azarian, João M. P. Cardoso, Stephan Werner, Jürgen Becker: An FPGA-based multi-core approach for pipelining computing stages. SAC 2013: 1533-1540
- 2012
- [j35]Diana Göhringer, Lukas Meder, Stephan Werner, Oliver Oey, Jürgen Becker, Michael Hübner: Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration. Int. J. Reconfig. Comp. 2012 (2012)
- [j34]Matthias Kühnle, André Wagner, Alisson Vasconcelos De Brito, Jürgen Becker: Modeling and Implementation of a Power Estimation Methodology for SystemC. Int. J. Reconfig. Comp. 2012 (2012)
- [j33]Christoph Roth, Joachim Meyer, Michael Rückauer, Oliver Sander, Jürgen Becker: Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels. Int. J. Reconfig. Comp. 2012 (2012)
- [j32]Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker: Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices. Int. J. Reconfig. Comp. 2012 (2012)
- [j31]Alexander Thomas, Michael Rückauer, Jürgen Becker: HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture. Int. J. Reconfig. Comp. 2012 (2012)
- [c219]Giulio Corradi, Romuald Girardey, Jürgen Becker: Xilinx tools facilitate development of FPGA applications for IEC61508. AHS 2012: 54-61
- [c218]Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf König, David May: Hardware prototyping of novel invasive multicore architectures. ASP-DAC 2012: 201-206
- [c217]Max Ferger, Muhammed Al Kadi, Michael Hübner, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Gabriel Marchesan Almeida, José Rodrigo Azambuja, Jürgen Becker: Hardware / Software Virtualization for the Reconfigurable Multicore Platform. CSE 2012: 341-344
- [c216]Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Jordy Potman, Kim Sunesen, Steven Derrien, Olivier Sentieys, Jürgen Becker: A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems. CSE 2012: 383-390
- [c215]Oliver Oey, Stephan Werner, Diana Göhringer, Andreas Stuckert, Jürgen Becker, Michael Hübner: Virtualization of heterogeneous and adaptive multi-core/multi-board systems. DASIP 2012: 1-2
- [c214]Timo Stripf, Ralf König, Jürgen Becker: A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture. DATE 2012: 21-26
- [c213]Christoph Schmutzler, Martin Simons, Jürgen Becker: On demand dependent deactivation of automotive ECUs. DATE 2012: 69-74
- [c212]Stephan Werner, Oliver Oey, Diana Göhringer, Michael Hübner, Jürgen Becker: Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems. DATE 2012: 280-283
- [c211]Jürgen Becker, Timo Stripf, Oliver Oey, Michael Hübner, Steven Derrien, Daniel Menard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Göhringer: From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. DSD 2012: 114-121
- [c210]Francisco Mendoza, Joris Pascal, Philipp Nenninger, Jürgen Becker: Framework for dynamic verification of multi-domain virtual platforms in industrial automation. INDIN 2012: 935-940
- [c209]Jürgen Becker, Jinian Bian, Christophe Bobda, René Cumplido, Michael Hübner: RAW Introduction. IPDPS Workshops 2012: 208-212
- [c208]Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker: Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. IPDPS Workshops 2012: 234-241
- [c207]Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker: On Dynamic Run-time Processor Pipeline Reconfiguration. IPDPS Workshops 2012: 419-424
- [c206]Timo Stripf, Ralf König, Patrick Rieder, Jürgen Becker: A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files. IPDPS Workshops 2012: 462-469
- [c205]Jan Heisswolf, Ralf König, Jürgen Becker: A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling. ISPA 2012: 625-632
- [c204]Matthias Birk, Matthias Balzer, Nicole V. Ruiter, Jürgen Becker: Comparison of processing performance and architectural efficiency metrics for FPGAs and GPUs in 3D Ultrasound Computer Tomography. ReConFig 2012: 1-7
- [c203]Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner, Jürgen Becker: Determination of on-chip temperature gradients on reconfigurable hardware. ReConFig 2012: 1-8
- [c202]Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, Michael Hübner, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Daniel Menard, Olivier Sentieys, Diana Göhringer, Thomas Perschke: A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. ReCoSoC 2012: 1-8
- [c201]Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hübner, Jürgen Becker, Sébastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire: Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures. ICSAMOS 2012: 228-235
- [c200]Michael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel, Jürgen Becker: Adaptive processor architecture - invited paper. ICSAMOS 2012: 244-251
- [c199]George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Göhringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hübner, Timo Stripf, Oliver Oey, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas: From Scilab to multicore embedded systems: Algorithms and methodologies. ICSAMOS 2012: 268-275
- [c198]Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker: LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture. SIES 2012: 279-282
- [i2]David Hillerkuss, Rene Schmogrow, Matthias Meyer, Stefan Wolf, Meinert Jordan, Philipp Kleinow, Nicole Lindenmann, Philipp C. Schindler, Argishti Melikyan, Xin Yang, Shalva Ben-Ezra, Bernd Nebendahl, Michael Dreschmann, Joachim Meyer, Francesca Parmigiani, Periklis Petropoulos, Bojan Resan, Aandreas Oehler, Kurt Weingarten, Lars Altenhain, Tobias Ellermeyer, Matthias Moeller, Michael Hübner, Jürgen Becker, Christian Koos, Wolfgang Freude, Juerg Leuthold: Single-laser 32.5 Tbit/s Nyquist WDM transmission. CoRR abs/1203.2516 (2012)
- 2011
- [j30]Matthias Birk, Clemens Hagner, Matthias Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker: Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT. Int. J. Reconfig. Comp. 2011 (2011)
- [j29]Aravind Dasu, João M. P. Cardoso, Eli Bozorgzadeh, Jürgen Becker: Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010). Int. J. Reconfig. Comp. 2011 (2011)
- [j28]Benjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker: Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems. Int. J. Reconfig. Comp. 2011 (2011)
- [j27]Diana Göhringer, Michael Hübner, Etienne Nguepi Zeutebouo, Jürgen Becker: Operating System for Runtime Reconfigurable Multiprocessor Systems. Int. J. Reconfig. Comp. 2011 (2011)
- [j26]Diana Göhringer, Jonathan Obie, André L. S. Braga, Michael Hübner, Carlos Humberto Llanos Quintero, Jürgen Becker: Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems. Int. J. Reconfig. Comp. 2011 (2011)
- [j25]Michael Hübner, Jürgen Becker, Loïc Lagadec, Gilles Sassatelli: Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010). Int. J. Reconfig. Comp. 2011 (2011)
- [j24]Alexander Klimm, Benjamin Glas, Matthias Wachs, Sebastian Vogel, Klaus D. Müller-Glaser, Jürgen Becker: A Security Scheme for Dependable Key Insertion in Mobile Embedded Devices. Int. J. Reconfig. Comp. 2011 (2011)
- [j23]Christian Schuck, Bastian Haetzer, Jürgen Becker: Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs. Int. J. Reconfig. Comp. 2011 (2011)
- [c197]Monica Magalhães Pereira, Lars Braun, Michael Hübner, Jürgen Becker, Luigi Carro: Run-time resource instantiation for fault tolerance in FPGAs. AHS 2011: 88-95
- [c196]Peter Figuli, Michael Hübner, Romuald Girardey, Falco Bapp, Thomas Bruckschlögl, Florian Thoma, Jörg Henkel, Jürgen Becker: A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion. AHS 2011: 96-103
- [c195]Matthias Birk, Alexander Guth, Michael Zapf, Matthias Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker: Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing. DASIP 2011: 67-74
- [c194]Natalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner, Jürgen Becker: Development of a method for image-based motion estimation of a VTOL-MAV on FPGA. DASIP 2011: 201-208
- [c193]Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker: Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration. DATE 2011: 1542-1547
- [c192]Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel, Jürgen Becker: Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors. FCCM 2011: 29-32
- [c191]Joachim Meyer, Juanjo Noguera, Michael Hübner, Rodney Stewart, Jürgen Becker: Embedded Systems Start-Up under Timing Constraints on Modern FPGAs. FPL 2011: 103-109
- [c190]Diana Göhringer, Stephan Werner, Michael Hübner, Jürgen Becker: RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC. FPL 2011: 181-184
- [c189]
- [c188]Christoph Roth, Gabriel Marchesan Almeida, Oliver Sander, Luciano Ost, Nicolas Hebert, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Jürgen Becker: Modular Framework for Multi-level Multi-device MPSoC Simulation. IPDPS Workshops 2011: 136-142
- [c187]Michael Hübner, Peter Figuli, Romuald Girardey, Dimitrios Soudris, K. Siozios, Jürgen Becker: A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture. IPDPS Workshops 2011: 143-149
- [c186]Ralf König, Timo Stripf, Jan Heisswolf, Jürgen Becker: A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors. IPDPS Workshops 2011: 150-157
- [c185]Christian Schuck, Bastian Haetzer, Michael Hübner, Jürgen Becker: Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs. IPDPS Workshops 2011: 181-188
- [c184]Alexander Klimm, Sebastian Vogel, Jürgen Becker: Hyperelliptic Curve Cryptoarchitecture for Fast Execution of Schnorr and Okamoto Authentication Protocols. IPDPS Workshops 2011: 196-203
- [c183]Matthias Rümmele-Werner, Thomas Perschke, Lars Braun, Michael Hübner, Jürgen Becker: A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker. ISCAS 2011: 853-856
- [c182]Alexander von Renteln, Uwe Brinkschulte, David Kramer, Wolfgang Karl, Christian Schuck, Jürgen Becker: Digital On-demand Computing Organism - Interaction between Monitoring and Middleware. ISORC 2011: 189-196
- [c181]Matthias Kühnle, Alisson Vasconcelos De Brito, Christoph Roth, Konstantinos Dagas, Jürgen Becker: The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip. ISVLSI 2011: 13-18
- [c180]Florian Thoma, Michael Hübner, Diana Göhringer, Hasam Ümitcan Yilmaz, Jürgen Becker: Power and performance optimization through MPI supported dynamic voltage and frequency scaling. MARC Symposium 2011: 75-78
- [c179]Diana Göhringer, Lukas Meder, Michael Hübner, Jürgen Becker: Adaptive Multi-client Network-on-Chip Memory. ReConFig 2011: 7-12
- [c178]Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker: Dynamic Processor Reconfiguration. ReConFig 2011: 123-128
- [c177]Nadine Dahm, Michael Hübner, Jürgen Becker: Approach of an FPGA based adaptive stepper motor control system. ReCoSoC 2011: 1-6
- [c176]Matthias Kühnle, Alisson Vasconcelos De Brito, Christoph Roth, Matthias Krüsselin, Jürgen Becker: An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels. ReCoSoC 2011: 1-8
- [c175]Mahtab Niknahad, Oliver Sander, Jürgen Becker: A study on fine granular fault tolerance methodologies for FPGAs. ReCoSoC 2011: 1-5
- [c174]Francisco Mendoza, Christian Köllner, Jürgen Becker, Klaus D. Müller-Glaser: An automated approach to SystemC/Simulink co-simulation. International Symposium on Rapid System Prototyping 2011: 135-141
- [c173]Ralf König, Timo Stripf, Jan Heisswolf, Jürgen Becker: Architecture design space exploration of run-time scalable issue-width processors. ICSAMOS 2011: 77-84
- [c172]Timo Stripf, Ralf König, Jürgen Becker: A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors. ICSAMOS 2011: 157-164
- [c171]Diana Göhringer, Oliver Oey, Michael Hübner, Jürgen Becker: Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip. ICSAMOS 2011: 380-387
- [c170]Christoph Roth, Oliver Sander, Jürgen Becker: Flexible and efficient co-simulation of networked embedded devices. SBCCI 2011: 61-66
- [c169]Matthias Kühnle, André Wagner, Jürgen Becker: A statistical power estimation methodology embedded in a SystemC code translator. SBCCI 2011: 79-84
- [c168]José Rodrigo Azambuja, Samuel Pagliarini, Mauricio Altieri, Fernanda Lima Kastensmidt, Michael Hübner, Jürgen Becker: Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique. SBCCI 2011: 161-166
- [c167]Alexander Thomas, Michael Rückauer, Jürgen Becker: HoneyComb: an application-driven online adaptive reconfigurable hardware architecture. SBCCI 2011: 173-178
- [c166]Christoph Roth, Oliver Sander, Matthias Kühnle, Jürgen Becker: HLA-based simulation environment for distributed SystemC simulation. SimuTools 2011: 108-114
- [c165]Alexander Thomas, Michael Rückauer, Jürgen Becker: HoneyComb: A multi-grained dynamically reconfigurable runtime adaptive hardware architecture. SoCC 2011: 335-340
- [p4]Thomas Ebi, David Kramer, Christian Schuck, Alexander von Renteln, Jürgen Becker, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl: DodOrg - A Self-adaptive Organic Many-core Architecture. Organic Computing 2011: 353-368
- [p3]Diana Göhringer, Michael Hübner, Jürgen Becker: Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support. Multiprocessor System-on-Chip 2011: 127-151
- [e14]Michael Hübner, Jürgen Becker (Eds.): Multiprocessor System-on-Chip - Hardware Design and Tool Integration. Springer 2011, ISBN 978-1-4419-6459-5
- [e13]Diana Göhringer, Michael Hübner, Jürgen Becker (Eds.): 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, Ettlingen, Germany, July 5-6, 2011. KIT Scientific Publishing, Karlsruhe 2011, ISBN 978-3-86644-717-2
- [e12]Peter M. Athanas, Jürgen Becker, René Cumplido (Eds.): 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1734-5
- [e11]Antonio Carlos Cavalcanti, Elmar U. K. Melcher, Jürgen Becker (Eds.): 24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 02, 2011. ACM 2011, ISBN 978-1-4503-0828-1
- [e10]Jürgen Becker, Marcelo O. Johann, Ricardo Reis (Eds.): VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers. IFIP Advances in Information and Communication Technology 360, Springer 2011, ISBN 978-3-642-23119-3
- 2010
- [j22]Roger Woods, Jürgen Becker, Peter Athanas, Fearghal Morgan: Guest Editorial ARC 2009. TRETS 4(1): 1 (2010)
- [j21]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker: Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems. TRETS 4(1): 4 (2010)
- [c164]André L. S. Braga, Carlos H. Llanos, Diana Göhringer, Jonathan Obie, Jürgen Becker, Michael Hübner: Performance, accuracy, power consumption and resource utilization analysis for hardware / software realized Artificial Neural Networks. BIC-TA 2010: 1629-1636
- [c163]Matthias Traub, Thilo Streichert, Oleg Krasovytskyy, Jürgen Becker: Scenario extraction for a refined timing-analysis of automotive network topologies. DATE 2010: 81-86
- [c162]Ralf König, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Jürgen Becker, Jörg Henkel: KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. DATE 2010: 819-824
- [c161]Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker: A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip. FCCM 2010: 259-262
- [c160]Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker: A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only). FPGA 2010: 286
- [c159]Michael Dreschmann, Michael Hübner, Moritz Roger, Oliver Sander, Christos Klamouris, Jürgen Becker, Wolfgang Freude, Juerg Leuthold: Reconfigurable Hardware for Power-over-Fiber Applications. FPL 2010: 525-531
- [c158]Jürgen Becker, Eli Bozorgzadeh, João M. P. Cardoso, Aravind Dasu: Welcome message. IPDPS Workshops 2010: 1-2
- [c157]Diana Göhringer, Jürgen Becker: High performance reconfigurable multi-processor-based computing on FPGAs. IPDPS Workshops 2010: 1-4
- [c156]Diana Göhringer, Michael Hübner, Etienne Nguepi Zeutebouo, Jürgen Becker: CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures. IPDPS Workshops 2010: 1-8
- [c155]Michael Hübner, Diana Göhringer, Juanjo Noguera, Jürgen Becker: Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. IPDPS Workshops 2010: 1-8
- [c154]Romuald Girardey, Michael Hübner, Jürgen Becker: Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications. ISVLSI 2010: 74-79
- [c153]Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart: Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration. ISVLSI 2010: 190-194
- [c152]Mahtab Niknahad, Michael Hübner, Jürgen Becker: Reliability Analysis and Improvement in Nano Scale Design. ISVLSI 2010: 299-303
- [c151]Romuald Girardey, Michael Hübner, Jürgen Becker: Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA. ISVLSI 2010: 469-470
- [c150]Lars Braun, Jürgen Becker: Two-Dimensional Dynamic Multigrained Reconfigurable Hardware. ISVLSI 2010: 475-476
- [c149]Diana Göhringer, Jürgen Becker: FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications. ISVLSI 2010: 477-478
- [c148]Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker: Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space. ReConFig 2010: 13-18
- [c147]Diana Göhringer, Michael Hübner, Laure Hugot-Derville, Jürgen Becker: Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC. ICSAMOS 2010: 357-364
- [p2]Alexander Thomas, Jürgen Becker: Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns. Dynamically Reconfigurable Systems 2010: 3-24
- [p1]Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Michael Ullmann, Klaus D. Müller-Glaser, Jürgen Becker: Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies. Dynamically Reconfigurable Systems 2010: 245-267
- [e9]Viktor K. Prasanna, Jürgen Becker, René Cumplido (Eds.): ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings. IEEE Computer Society 2010
2000 – 2009
- 2009
- [j20]Jürgen Becker, Michael Junk, Dirk Kehrwald, Guido Thömmes, Zhaoxia Yang: A combined lattice BGK/level set method for immiscible two-phase flows. Computers & Mathematics with Applications 58(5): 950-964 (2009)
- [j19]Diana Göhringer, Thomas Perschke, Michael Hübner, Jürgen Becker: A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip. Int. J. Reconfig. Comp. 2009 (2009)
- [j18]Christian Schuck, Bastian Haetzer, Jürgen Becker: An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing. Int. J. Reconfig. Comp. 2009 (2009)
- [j17]Guido Thömmes, Jürgen Becker, Michael Junk, A. K. Vaikuntam, Dirk Kehrwald, Axel Klar, K. Steiner, A. Wiegmann: A lattice Boltzmann method for immiscible multiphase flow simulations using the level set method. J. Comput. Physics 228(4): 1139-1156 (2009)
- [j16]Lars Braun, Diana Göhringer, Thomas Perschke, Volker Schatz, Michael Hübner, Jürgen Becker: Adaptive real-time image processing exploiting two dimensional reconfigurable architecture. J. Real-Time Image Processing 4(2): 109-125 (2009)
- [j15]Katarina Paulsson, Michael Hübner, Jürgen Becker: Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems. Microprocessors and Microsystems - Embedded Hardware Design 33(1): 46-52 (2009)
- [c146]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker: FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. ARC 2009: 62-73
- [c145]Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser: Priority-based packet communication on a bus-shaped structure for FPGA-systems. DATE 2009: 178-183
- [c144]Jürgen Becker: Adaptive Multicore Systems-on-Chip (MSoC) - Design and Computing in the Nano Era. ERSA 2009: 55-66
- [c143]Diana Göhringer, Bin Liu, Michael Hübner, Jürgen Becker: Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol. FPL 2009: 320-325
- [c142]Romuald Girardey, Michael Hübner, Jürgen Becker: Dynamic reconfigurable mixed-signal architecture for safety critical applications. FPL 2009: 503-506
- [c141]Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser: Design of a Vehicle-to-Vehicle communication system on reconfigurable hardware. FPT 2009: 14-21
- [c140]Alexander Klimm, Oliver Sander, Jürgen Becker: A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs. IPDPS 2009: 1-8
- [c139]Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser: Testing of an FPGA Based C2X-Communication Prototype with a Model Based Traffic Generation. IEEE International Workshop on Rapid System Prototyping 2009: 68-71
- [c138]Benjamin Glas, Alexander Klimm, Klaus D. Müller-Glaser, Jürgen Becker: Configuration Measurement for FPGA-based Trusted Platforms. IEEE International Workshop on Rapid System Prototyping 2009: 123-129
- [c137]Oliver Sander, Christoph Roth, Vitali Stuckert, Jürgen Becker: System concept for an FPGA based real-time capable automotive ECU simulation system. SBCCI 2009
- [c136]Mahtab Niknahad, Michael Hübner, Jürgen Becker: Method for improving performance in online routing of reconfigurable nano architectures. SoCC 2009: 65-68
- [c135]Benjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker: Car-to-Car Communication Security on Reconfigurable Hardware. VTC Spring 2009
- [e8]Jürgen Becker, Roger Woods, Peter M. Athanas, Fearghal Morgan (Eds.): Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings. Lecture Notes in Computer Science 5453, Springer 2009, ISBN 978-3-642-00640-1
- 2008
- [j14]Matthias Kühnle, Michael Hübner, Jürgen Becker, Antonio Deledda, Claudio Mucci, Florian Ries, Marcello Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Tommaso DeMarco, Fabio Campi: An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC. IEEE Design & Test of Computers 25(5): 442-451 (2008)
- [j13]Jürgen Becker, Michael Hübner, Roger Woods, Philip Heng Wai Leong, Robert Esser, Lionel Torres: Current Trends on Reconfigurable Computing. Int. J. Reconfig. Comp. 2008 (2008)
- [c134]Oliver Sander, Lars Braun, Michael Hübner, Jürgen Becker: Data reallocation by exploiting FPGA configuration mechanisms. ARC 2008: 308-313
- [c133]Alexander Klimm, Oliver Sander, Jürgen Becker, Sylvain Subileau: A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA. ARCS 2008: 188-201
- [c132]Jürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer: Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. DATE 2008
- [c131]Katarina Paulsson, Michael Hübner, Jürgen Becker: Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. DATE 2008: 50-55
- [c130]Benjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker: A System Architecture for Reconfigurable Trusted Platforms. DATE 2008: 541-544
- [c129]Ralf König, Timo Stripf, Jürgen Becker: A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms. DATE 2008: 604-609
- [c128]Antonio Deledda, Claudio Mucci, Arseni Vitkovski, Philippe Bonnot, Arnaud Grasset, Philippe Millet, Matthias Kühnle, Florian Ries, Michael Hübner, Jürgen Becker, Massimo Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Fabio Campi, Tommaso DeMarco: Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. DATE 2008: 1352-1357
- [c127]Carlos Morra, João Bispo, João M. P. Cardoso, Jürgen Becker: Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures. FCCM 2008: 320-321
- [c126]Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker: Fine grain reconfigurable architectures. FPL 2008: 348
- [c125]Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner: Coarse-grained reconfiguration. FPL 2008: 349
- [c124]Diana Göhringer, Michael Hübner, Thomas Perschke, Jürgen Becker: New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach. FPL 2008: 495-498
- [c123]Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker: A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. FPL 2008: 535-538
- [c122]Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker: Data path driven waveform-like reconfiguration. FPL 2008: 607-610
- [c121]Katarina Paulsson, Michael Hübner, Jürgen Becker: Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. FPL 2008: 699-700
- [c120]Oliver Sander, Michael Hübner, Jürgen Becker, Matthias Traub: Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain. FPT 2008: 97-104
- [c119]Benjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker: A self adaptive interfacing concept for consumer device integration into automotive entities. IPDPS 2008: 1-6
- [c118]Diana Göhringer, Michael Hübner, Volker Schatz, Jürgen Becker: Runtime adaptive multi-processor system-on-chip: RAMPSoC. IPDPS 2008: 1-7
- [c117]Michael Hübner, Lars Braun, Diana Göhringer, Jürgen Becker: Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems. IPDPS 2008: 1-6
- [c116]Alexander Klimm, Lars Braun, Jürgen Becker: An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores. IPDPS 2008: 1-7
- [c115]Christian Schuck, Matthias Kühnle, Michael Hübner, Jürgen Becker: A framework for dynamic 2D placement on FPGAs. IPDPS 2008: 1-7
- [c114]
- [c113]Katarina Paulsson, Ulrich Viereck, Michael Hübner, Jürgen Becker: Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. ISVLSI 2008: 304-309
- [c112]Sunil Shukla, Neil W. Bergmann, Jürgen Becker: A Web Server Based Edge Detector Implementation in FPGA. ISVLSI 2008: 441-446
- [c111]Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker: Towards Novel Approaches in Design Automation for FPGA Power Optimization. PATMOS 2008: 419-428
- [c110]Benjamin Glas, Alexander Klimm, David Schwab, Klaus D. Müller-Glaser, Jürgen Becker: A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates. IEEE International Workshop on Rapid System Prototyping 2008: 135-141
- [c109]Carlos Morra, João M. P. Cardoso, João Bispo, Jürgen Becker: Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures. SASP 2008: 34-41
- 2007
- [j12]Sebastian Wieskotten, Stefanie Heinke, Peter Wabel, Ulrich Moissl, Jürgen Becker, Matthias Pirlich, Michael Keymling, Rolf Isermann: Modell-basierte Erkennung von Mangelernährung mittels Bioimpedanzspektroskopie (Model-based Identification of Malnutrition via Bioimpedance Spectroscopy). Automatisierungstechnik 55(10): 531-538 (2007)
- [j11]Alexander Thomas, Jürgen Becker: New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur). it - Information Technology 49(3): 165- (2007)
- [c108]Katarina Paulsson, Michael Hübner, Günther Auer, Michael Dreschmann, Jürgen Becker: Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. FPL 2007: 351-356
- [c107]Christian Schuck, Stefan Lamparth, Jürgen Becker: artNoC - A Novel Multi-Functional Router Architecture for Organic Computing. FPL 2007: 371-376
- [c106]Florian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker: MORPHEUS: Heterogeneous Reconfigurable Computing. FPL 2007: 409-414
- [c105]Katarina Paulsson, Michael Hübner, Jürgen Becker, Jean-Marc Philippe, Christian Gamrat: On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. FPL 2007: 415-422
- [c104]Mahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker: H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture. FPL 2007: 467-471
- [c103]Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach: Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. FPL 2007: 688-691
- [c102]Philipp Graf, Michael Hübner, Klaus D. Müller-Glaser, Jürgen Becker: A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures. FPL 2007: 722-725
- [c101]Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker: High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. IPDPS 2007: 1-8
- [c100]Alisson Vasconcelos De Brito, Matthias Kühnle, Elmar U. K. Melcher, Jürgen Becker: A General Purpose Partially Reconfigurable Processor Simulator (PReProS). IPDPS 2007: 1-7
- [c99]Carlos Morra, João M. P. Cardoso, Jürgen Becker: Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements. IPDPS 2007: 1-8
- [c98]Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker: Communication Architectures for Dynamically Reconfigurable FPGA Designs. IPDPS 2007: 1-8
- [c97]Sunil Shukla, Neil W. Bergmann, Jürgen Becker: QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks. IPDPS 2007: 1-7
- [c96]Alisson Vasconcelos De Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, Elmar U. K. Melcher: Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC. ISVLSI 2007: 35-40
- [c95]Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele: Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. ISVLSI 2007: 41-46
- [c94]Katarina Paulsson, Michael Hübner, Salih Bayar, Jürgen Becker: Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. ReCoSoC 2007: 1-6
- [c93]Jürgen Becker, Adam Donlin, Michael Hübner: New tool support and architectures in adaptive reconfigurable computing. VLSI-SoC 2007: 134-139
- [i1]Michael Ullmann, Wansheng Jin, Jürgen Becker: Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. CoRR abs/0710.4850 (2007)
- 2006
- [c92]Katarina Paulsson, Michael Hübner, Jürgen Becker: Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration. AHS 2006: 288-291
- [c91]Sunil Shukla, Neil W. Bergmann, Jürgen Becker: QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. ARC 2006: 93-98
- [c90]Jürgen Becker, Kurt Brändle, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl, Thorsten Köster, Michael Wenz, Heinz Wörn: Digital On-Demand Computing Organism for Real-Time Systems. ARCS Workshops 2006: 230-245
- [c89]Jürgen Becker, Michael Hübner, Katarina Paulsson: Physical 2D Morphware and Power Reduction Methods for Everyone. Dynamically Reconfigurable Architectures 2006
- [c88]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
- [c87]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
- [c86]Sunil Shukla, Neil W. Bergmann, Jürgen Becker: QUKU: A Coarse Grained Paradigm for FPGAs. Dynamically Reconfigurable Architectures 2006
- [c85]Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein: From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. FPL 2006: 1-4
- [c84]Maik Boden, Steffen Rülke, Jürgen Becker: A high-level target-precise model for designing reconfigurable HW tasks. IPDPS 2006
- [c83]Michael Hübner, Christian Schuck, Jürgen Becker: Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs. IPDPS 2006
- [c82]Michael Ullmann, Jürgen Becker: Communication concept for adaptive intelligent run-time systems supporting distributed reconfigurable embedded systems. IPDPS 2006
- [c81]Michael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker: New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits. ISVLSI 2006: 97-102
- [c80]Sunil Shukla, Neil W. Bergmann, Jürgen Becker: QUKU: A Two-Level Reconfigurable Architecture. ISVLSI 2006: 109-116
- [c79]Katarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker: Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. ISVLSI 2006: 159-166
- [c78]Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker: Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. ISVLSI 2006: 251-256
- [c77]Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein: Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. ReCoSoC 2006: 46-51
- [c76]Michael Hübner, Jürgen Becker: Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration. SBCCI 2006: 1-4
- [c75]Jürgen Becker, Michael Hübner: Run-time reconfigurabilility and other future trends. SBCCI 2006: 9-11
- [c74]Katarina Paulsson, Michael Hübner, Jürgen Becker: On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. SBCCI 2006: 173-178
- [e7]Wolfgang Karl, Jürgen Becker, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle (Eds.): ARCS 2006 - 19th International Conference on Architecture of Computing Systems, Workshops Proceedings, March 16, 2006, Frankfurt am Main, Germany. LNI 81, GI 2006, ISBN 3-88579-175-7
- [e6]Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich (Eds.): Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006. Dagstuhl Seminar Proceedings 06141, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006
- [e5]Claudionor José Nunes Coelho Jr., Ricardo P. Jacobi, Jürgen Becker (Eds.): Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006. ACM 2006
- 2005
- [j10]Jürgen Becker, Alexander Thomas: Scalable Processor Instruction Set Extension. IEEE Design & Test of Computers 22(2): 136-148 (2005)
- [j9]Michael Ullmann, Michael Hübner, Jürgen Becker: On-demand FPGA run-time system for flexible and dynamical reconfiguration. IJES 1(3/4): 193-204 (2005)
- [j8]Michael Hübner, Michael Ullmann, Jürgen Becker: Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation. IJES 1(3/4): 263-273 (2005)
- [j7]Jürgen Becker, Kurt Brändle, Michael Ullmann: Rekonfigurierbare Hardware und intelligente Laufzeitsysteme für adaptives Rechnen. it - Information Technology 47(4): 201-206 (2005)
- [c73]Michael Hübner, Katarina Paulsson, Marcus Stitz, Jürgen Becker: Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs. ARCS Workshops 2005: 39-44
- [c72]Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein: FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. FPL 2005: 25-30
- [c71]Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon: Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors. FPL 2005: 703-706
- [c70]Michael Hübner, Katarina Paulsson, Jürgen Becker: Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. IPDPS 2005
- [c69]Michael Ullmann, Wansheng Jin, Jürgen Becker: Hardware Enhanced Function Allocation Management in Reconfigurable Systems. IPDPS 2005
- [c68]Alexander Thomas, Jürgen Becker: Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures. ISVLSI 2005: 118-123
- [c67]Carsten Bieser, Klaus D. Müller-Glaser, Jürgen Becker: Hardware/Software Co-Training Lab: From VHDL Bit-Level Coding up to CASE-Tool Based System Modeling. MSE 2005: 51-52
- [c66]Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas: Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. ReCoSoC 2005: 35-42
- [c65]Alexander Thomas, Jürgen Becker: Online-adaptive Reconfigurable Hardware Architecture and Runtime Environment. SoCC 2005: 239-242
- [c64]Adam Donlin, Jürgen Becker, Michael Hübner: I Models and Tools for the Dynamic Reconfiguration of FPGAs. SoCC 2005: 313-316
- [e4]Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Christian Hochberger, Thomas Martinetz, Christian Müller-Schloer, Hartmut Schmeck, Theo Ungerer, Rolf P. Würtz (Eds.): 18th International Conference on Architecture of Computing Systems, Workshops, Innsbruck, Austria, March 2005. VDE Verlag 2005, ISBN 3-8007-2880-X
- [e3]Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic (Eds.): Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005. CSREA Press 2005, ISBN 1-932415-53-X
- 2004
- [j6]Jürgen Becker: Dagstuhl-Seminar "Dynamically and Partially Reconfigurable Architectures". it - Information Technology 46(4): 218-225 (2004)
- [c63]Alexander Thomas, Jürgen Becker: Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur. ARCS Workshops 2004: 165-174
- [c62]Michael Ullmann, Wansheng Jin, Jürgen Becker: Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. DATE 2004: 259-264
- [c61]Alexander Thomas, Jürgen Becker: Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. FPL 2004: 115-124
- [c60]Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker: On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. FPL 2004: 454-463
- [c59]Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker: Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. FPL 2004: 1037-1041
- [c58]Uwe Brinkschulte, Jürgen Becker, Klaus Dorfmüller-Ulhaas, Ralf König, Sascha Uhrig, Theo Ungerer: CARUSO - Project Goals and Principal Approach. GI Jahrestagung (2) 2004: 616-620
- [c57]Uwe Brinkschulte, Jürgen Becker, Theo Ungerer: CARUSO - An Approach Towards a Network of Low Power Autonomic Systems on Chips for Embedded Real-time Application. IPDPS 2004
- [c56]Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker: An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. IPDPS 2004
- [c55]Alexander Thomas, Jürgen Becker, Ulrich Heinkel, Klaus Winkelmann, Jörg Bormann: Formale Verifikation eines Sonet/SDH Framers. MBMV 2004: 280-288
- [c54]Michael Hübner, Tobias Becker, Jürgen Becker: Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. SBCCI 2004: 28-32
- [c53]Alexander Thomas, Thomas Zander, Jürgen Becker: Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures. SBCCI 2004: 141-146
- [c52]Jürgen Becker, Martin Vorbach: Coarse-grain reconfigurable XPP devices for adaptive high-end mobile video-processing. SoCC 2004: 165-166
- [e2]Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle, Thomas A. Runkler (Eds.): ARCS 2004 - Organic and Pervasive Computing, Workshops Proceedings, March 26, 2004, Augsburg, Germany. LNI 41, GI 2004, ISBN 3-88579-370-9
- [e1]Jürgen Becker, Marco Platzner, Serge Vernalde (Eds.): Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings. Lecture Notes in Computer Science 3203, Springer 2004, ISBN 3-540-22989-2
- 2003
- [j5]Jürgen Becker, Reiner W. Hartenstein: Configware and morphware going mainstream. Journal of Systems Architecture 49(4-6): 127-142 (2003)
- [c51]Jürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten: An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration. DATE 2003: 11120-11121
- [c50]Jürgen Becker, Martin Vorbach: PACT XPP Architecture in Adaptive System-on-Chip Integration. Engineering of Reconfigurable Systems and Algorithms 2003: 21-30
- [c49]Martin Vorbach, Jürgen Becker: Reconfigurable Processor Architectures for Mobile Phones. IPDPS 2003: 181
- [c48]Jürgen Becker, Martin Vorbach: Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC). ISVLSI 2003: 107-112
- [c47]Jens E. Becker, Carsten Bieser, Alexander Thomas, Klaus D. Müller-Glaser, Jürgen Becker: Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core. MSE 2003: 134-135
- [c46]Jürgen Becker, Alexander Thomas, Maik Scheer: Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. SBCCI 2003: 237-242
- [c45]Jürgen Becker, Michael Hübner, Michael Ullmann: Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. SBCCI 2003: 283-288
- [c44]Jürgen Becker, Michael Hübner, Michael Ullmann: Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems. VLSI-SoC (Selected Papers) 2003: 119-132
- [c43]Jürgen Becker, Michael Hübner, Michael Ullmann: Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations. VLSI-SOC 2003: 129-
- [c42]Jürgen Becker, Alexander Thomas, Maik Scheer: Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath. VLSI-SoC (Selected Papers) 2003: 263-279
- [c41]Jürgen Becker, Alexander Thomas, Maik Scheer: Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors. VLSI-SOC 2003: 288-
- 2002
- [c40]Chun Hok Ho, Monk-Ping Leong, Philip Heng Wai Leong, Jürgen Becker, Manfred Glesner: Rapid Prototyping of FPGA Based Floating Point DSP Systems. IEEE International Workshop on Rapid System Prototyping 2002: 19-24
- 2001
- [j4]Jürgen Becker, Manfred Glesner: A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication. The Journal of Supercomputing 19(1): 105-127 (2001)
- [c39]Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner: Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. FPL 2001: 584-589
- [c38]Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis: Distributed Collaborative Design over Cave2 Framework. VLSI-SOC 2001: 97-108
- [c37]Jochen Mades, Thomas Schneider, André Windisch, Thomas Hollstein, Jürgen Becker, Manfred Glesner: Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. MSE 2001: 2-3
- [c36]Amar Mukherjee, Nitin Motgi, Jürgen Becker, A. Friebe, C. Habermann, Manfred Glesner: Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems. IEEE International Workshop on Rapid System Prototyping 2001: 58-63
- 2000
- [j3]Frank-Michael Renner, Jürgen Becker, Manfred Glesner: Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. Design Autom. for Emb. Sys. 5(3-4): 351-363 (2000)
- [j2]Frank-Michael Renner, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner: Synthese von Kommunikationsstrukturen und architekturgenaues Rapid-Prototyping eingebetteter Echtzeitsysteme (Communication Synthesis and Architecture-Precise Rapid Prototyping of Embedded systems with Hard Real-Time Constraints). it+ti - Informationstechnik und Technische Informatik 42(2): 27-33 (2000)
- [c35]Ahmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner: Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems. FCCM 2000: 205-216
- [c34]Frank-Michael Renner, Jürgen Becker, Manfred Glesner: Field Programmable Communication Emulation and Optimization for Embedded System Design. FPL 2000: 58-67
- [c33]Jürgen Becker, Thilo Pionteck, Manfred Glesner: DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. FPL 2000: 312-321
- [c32]Frank-Michael Renner, Jürgen Becker, Manfred Glesner: Communication Performance Estimation and Communication Synthesis for Architecture-precise Prototyping of Real-time Embedded Systems. MBMV 2000: 227-235
- [c31]Jürgen Becker, Manfred Glesner: IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures. PDPTA 2000
- [c30]Jürgen Becker, Manfred Glesner, Ahmad Alsolaim, Janusz A. Starzyk: Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures. PDPTA 2000
- [c29]Frank-Michael Renner, Jürgen Becker, Manfred Glesner: Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping 2000: 154-159
- [c28]Jürgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner: Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications. IEEE International Workshop on Rapid System Prototyping 2000: 160-
1990 – 1999
- 1999
- [c27]Marc Theisen, Jürgen Becker, Manfred Glesner, Tri Caohuu: Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations. ARCS 1999: 143-154
- [c26]Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jürgen Becker: Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. FPL 1999: 507-513
- [c25]Andreas Kirschbaum, Jürgen Becker, Manfred Glesner: ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect. VLSI 1999: 659-670
- [c24]Matthias Meixner, Jürgen Becker, Thomas Hollstein, Manfred Glesner: Object-oriented Specification Approach for Synthesis of Hardware-/Software Systems. MBMV 1999: 182-191
- [c23]Frank-Michael Renner, Jürgen Becker, Manfred Glesner: Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping 1999: 108-113
- 1998
- [c22]Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger: Parallelization in Co-Compilation for Configurable Accelerators. ASP-DAC 1998: 23-33
- [c21]Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner: HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. CODES 1998: 29-33
- [c20]Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner: Perspectives of Reconfigurable Computing in Research, Industry and Education. FPL 1998: 39-48
- [c19]Frank-Michael Renner, Jürgen Becker, Manfred Glesner: An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications. FPL 1998: 179-188
- [c18]Andreas Kirschbaum, Jürgen Becker, Manfred Glesner: A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems. IPPS/SPDP Workshops 1998: 61-66
- [c17]Jürgen Becker, Reiner W. Hartenstein: Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. International Workshop on Rapid System Prototyping 1998: 32-38
- [c16]Andreas Kirschbaum, Jürgen Becker, Manfred Glesner: Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment. International Workshop on Rapid System Prototyping 1998: 52-57
- 1997
- [b1]Jürgen Becker: A partitioning compiler for computers with Xputer-based accelerators. Universität Kaiserslautern 1997, pp. I-X, 1-309
- [c15]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger: A Novel Universal Sequencer Hardware. ARCS 1997: 143-152
- [c14]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger: A Novel Sequencer Hardware for Application Specific Computing. ASAP 1997: 392-401
- [c13]Reiner W. Hartenstein, Jürgen Becker: Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. CODES 1997: 141-146
- [c12]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger: Data scheduling to increase performance of parallel accelerators. FPL 1997: 294-303
- [c11]Reiner W. Hartenstein, Jürgen Becker: A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. HICSS (5) 1997: 125-134
- [c10]Reiner W. Hartenstein, Jürgen Becker: Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. VLSI Design 1997: 146-150
- 1996
- [j1]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig: High-performance computing using a reconfigurable accelerator. Concurrency - Practice and Experience 8(6): 429-443 (1996)
- [c9]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger: A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP 1996: 274-283
- [c8]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress: Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES 1996: 77-84
- [c7]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress: Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS 1996: 395-
- [c6]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress: An Embedded Accelerator for Real-Time Image Processing. RTS 1996: 83-88
- [c5]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress: Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL 1996: 65-76
- [c4]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger: A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS 1996: 544-548
- [c3]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig: CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design 1996: 81-84
- 1995
- [c2]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt: A Parallelizing Compilation Method for the Map-oriented Machine. ASAP 1995: 129-132
- 1994
- [c1]Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt: Data-Procedural Languages for FPL-based Machines. FPL 1994: 183-195
Coauthor Index
[j38] [j37] [j35] [c217] [c215] [c212] [c211] [c209] [c207] [c203] [c202] [c201] [c200] [c199] [c198] [i2] [j30] [j27] [j26] [j25] [c197] [c196] [c195] [c194] [c193] [c191] [c190] [c187] [c185] [c183] [c180] [c179] [c178] [c177] [c171] [c168] [p3] [e14] [e13] [j21] [c164] [c161] [c160] [c159] [c156] [c155] [c154] [c153] [c152] [c151] [c147] [p1] [j19] [j16] [j15] [c146] [c143] [c142] [c136] [j14] [j13] [c134] [c132] [c131] [c128] [c126] [c124] [c123] [c122] [c121] [c120] [c118] [c117] [c115] [c113] [c111] [c108] [c105] [c103] [c102] [c98] [c96] [c95] [c94] [c93] [c92] [c89] [c83] [c81] [c79] [c76] [c75] [c74] [j9] [j8] [c73] [c70] [c66] [c64] [c60] [c59] [c56] [c54] [c45] [c44] [c43]