Bernd Becker

Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker: Provably optimal test cube generation using quantified boolean formula solving. ASP-DAC 2013: 533-539

Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker: Accurate QBF-based test pattern generation in presence of unknown values. DATE 2013: 436-441

Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker: Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. DATE 2013: 448-453

Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker: Equivalence Checking for Partial Implementations Revisited. MBMV 2013: 61-70

Karsten Scheibler, Stefan Kupferschmid, Bernd Becker: Recent Improvements in the SMT Solver iSAT. MBMV 2013: 231-241

Bettina Braitling, Ralf Wimmer, Bernd Becker, Erika Ábrahám: Stochastic Bounded Model Checking: Bounded Rewards and Compositionality. MBMV 2013: 243-254

Alexander Czutro, Michael E. Imhof, J. Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich: Variation-Aware Fault Grading. Asian Test Symposium 2012: 344-349

Nils Jansen, Erika Ábrahám, Matthias Volk, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker: The COMICS Tool - Computing Minimal Counterexamples for DTMCs. ATVA 2012: 349-353

Bernd Becker, Rüdiger Ehlers, Matthew D. T. Lewis, Paolo Marin: ALLQBF Solving by Computational Learning. ATVA 2012: 370-384

Linus Feiten, Manuel Buehrer, Sebastian Sester, Bernd Becker: SMILE - Smartphones in Lectures - Initiating a Smartphone-based Audience Response System as a Student Project. CSEDU (1) 2012: 288-293

Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian: On the optimality of K longest path generation algorithm under memory constraints. DATE 2012: 418-423

Paolo Marin, Christian Miller, Matthew D. T. Lewis, Bernd Becker: Verification of partial designs using incremental QBF solving. DATE 2012: 623-628

Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker: #SAT-based vulnerability analysis of security components - A case study. DFT 2012: 49-54

Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker: Multi-conditional SAT-ATPG for power-droop testing. European Test Symposium 2012: 1-6

Stefan Hillebrecht, Michael A. Kochte, Hans-Joachim Wunderlich, Bernd Becker: Exact stuck-at fault classification in presence of unknowns. European Test Symposium 2012: 1-6

Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian: On the quality of test vectors for post-silicon characterization. European Test Symposium 2012: 1-6

Nils Jansen, Erika Ábrahám, Barna Zajzon, Ralf Wimmer, Johann Schuster, Joost-Pieter Katoen, Bernd Becker: Symbolic Counterexample Generation for Discrete-Time Markov Chains. FACS 2012: 134-151

Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker: Small-delay-fault ATPG with waveform accuracy. ICCAD 2012: 30-36

Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker: TSV and DFT cost aware circuit partitioning for 3D-SOCs. ISQED 2012: 21-26

Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker: Functional test of small-delay faults using SAT and Craig interpolation. ITC 2012: 1-8

Sven Reimer, Florian Pigorsch, Christoph Scholl, Bernd Becker: Enhanced Integration of QBF Solving Techniques. MBMV 2012: 133-143

Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám, Joost-Pieter Katoen: Minimal Critical Subsystems as Counterexamples for omega-Regular DTMC Properties. MBMV 2012: 169-180

Paolo Marin, Christian Miller, Bernd Becker: Incremental QBF Preprocessing for Partial Design Verification - (Poster Presentation). SAT 2012: 473-474

Ralf Wimmer, Nils Jansen, Erika Ábrahám, Bernd Becker, Joost-Pieter Katoen: Minimal Critical Subsystems for Discrete-Time Markov Models. TACAS 2012: 299-314

Matthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker: Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation. VLSI Design 2012: 382-387

Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker: SAT-ATPG using preferences for improved detection of complex defect mechanisms. VTS 2012: 170-175

Nils Jansen, Erika Ábrahám, Maik Scheffler, Matthias Volk, Andreas Vorpahl, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker: The COMICS Tool - Computing Minimal Counterexamples for Discrete-time Markov Chains. CoRR abs/1206.0603 (2012)

Ernst Moritz Hahn, Holger Hermanns, Ralf Wimmer, Bernd Becker: Transient Reward Approximation for Grids, Crowds, and Viruses. CoRR abs/1212.1251 (2012)

Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich: Variation-aware fault modeling. SCIENCE CHINA Information Sciences 54(9): 1813-1826 (2011)

Stefan Kupferschmid, Matthew D. T. Lewis, Tobias Schubert, Bernd Becker: Incremental preprocessing methods for use in BMC. Formal Methods in System Design 39(2): 185-204 (2011)

Matthew D. T. Lewis, Tobias Schubert, Bernd Becker, Paolo Marin, Massimo Narizzano, Enrico Giunchiglia: Parallel QBF Solving with Advanced Knowledge Sharing. Fundam. Inform. 107(2-3): 139-166 (2011)

Erika Ábrahám, Tobias Schubert, Bernd Becker, Martin Fränzle, Christian Herde: Parallel SAT Solving in Bounded Model Checking. J. Log. Comput. 21(1): 5-21 (2011)

Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker: Modeling and Mitigating Transient Errors in Logic Circuits. IEEE Trans. Dependable Sec. Comput. 8(4): 537-547 (2011)

Pepijn Crouzen, Ernst Moritz Hahn, Holger Hermanns, Abhishek Dhama, Oliver E. Theel, Ralf Wimmer, Bettina Braitling, Bernd Becker: Bounded Fairness for Probabilistic Distributed Algorithms. ACSD 2011: 89-97

J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker: Fault diagnosis aware ATE assisted test response compaction. ASP-DAC 2011: 812-817

Matthias Sauer, Jie Jiang, Alejandro Czutro, Ilia Polian, Bernd Becker: Efficient SAT-Based Search for Longest Sensitisable Paths. Asian Test Symposium 2011: 108-113

Nils Jansen, Erika Ábrahám, Jens Katelaan, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker: Hierarchical Counterexamples for Discrete-Time Markov Chains. ATVA 2011: 443-452

Ernst Althaus, Bernd Becker, Daniel Dumitriu, Stefan Kupferschmid: Integration of an LP Solver into Interval Constraint Propagation. COCOA 2011: 343-356

Sven Reimer, Florian Pigorsch, Christoph Scholl, Bernd Becker: Integration of orthogonal QBF solving techniques. DATE 2011: 149-154

Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker: Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. DATE 2011: 1424-1429

Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker: SAT-based analysis of sensitisable paths. DDECS 2011: 93-98

Stefan Kupferschmid, Bernd Becker, Tino Teige, Martin Fränzle: Proof certificates and non-linear arithmetic constraints. DDECS 2011: 429-434

Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell: Towards Variation-Aware Test Methods. European Test Symposium 2011: 219-225

Stefan Kupferschmid, Bernd Becker: Craig Interpolation in the Presence of Non-linear Constraints. FORMATS 2011: 240-255

Bettina Braitling, Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám: Counterexample Generation for Markov Chains Using SMT-Based Bounded Model Checking. FMOODS/FORTE 2011: 75-89

Matthias Sauer, Alejandro Czutro, Ilia Polian, Bernd Becker: Estimation of component criticality in early design steps. IOLTS 2011: 104-110

Matthias Sauer, Victor Tomashevich, J. Muller, Matthew D. T. Lewis, A. Spilla, Ilia Polian, Bernd Becker, W. Burgard: An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. IOLTS 2011: 182-185

Bettina Braitling, Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám: SMT-based Counterexample Generation for Markov Chains. MBMV 2011: 19-28

Christian Miller, Christoph Scholl, Bernd Becker: Verifying Incomplete Networks of Timed Automata. MBMV 2011: 113-122

Stefan Kupferschmid, Bernd Becker: Craigsche Interpolation für Boolesche Kombinationen linearer und nichtlinearer Ungleichungen. MBMV 2011: 279-288

Ralf Wimmer, Ernst Moritz Hahn, Holger Hermanns, Bernd Becker: Reachability analysis for incomplete networks of Markov decision processes. MEMOCODE 2011: 151-160

Christian Miller, Karina Gitina, Bernd Becker: Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas. MTV 2011: 22-27

Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. International Journal of Parallel Programming 38(3-4): 185-202 (2010)

Ilia Polian, Bernd Becker: Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). it - Information Technology 52(4): 189-194 (2010)

Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich: Variation-Aware Fault Modeling. Asian Test Symposium 2010: 87-93

Christian Miller, Stefan Kupferschmid, Bernd Becker: Exploiting Craig Interpolants in Bounded Model Checking for Incomplete Designs. MBMV 2010: 77-86

Natalia Kalinnik, Erika Ábrahám, Tobias Schubert, Ralf Wimmer, Bernd Becker: Exploiting Different Strategies for the Parallelization of an SMT Solver. MBMV 2010: 97-106

Tobias Nopper, Christian Miller, Matthew D. T. Lewis, Bernd Becker, Christoph Scholl: SAT Modulo BDD -- A Combined Verification Approach for Incomplete Designs. MBMV 2010: 107-116

Ralf Wimmer, Bernd Becker: Correctness Issues of Symbolic Bisimulation Computation for Markov Chains. MMB/DFT 2010: 287-301

Christian Miller, Karina Gitina, Christoph Scholl, Bernd Becker: Bounded Model Checking of Incomplete Networks of Timed Automata. MTV 2010: 61-66

Ralf Wimmer, Bettina Braitling, Bernd Becker, Ernst Moritz Hahn, Pepijn Crouzen, Holger Hermanns, Abhishek Dhama, Oliver E. Theel: Symblicit Calculation of Long-Run Averages for Concurrent Probabilistic Systems. QEST 2010: 27-36

Erika Ábrahám, Nils Jansen, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker: DTMC Model Checking by SCC Reduction. QEST 2010: 37-46

Christian Miller, Stefan Kupferschmid, Matthew D. T. Lewis, Bernd Becker: Encoding Techniques, Craig Interpolants and Bounded Model Checking for Incomplete Designs. SAT 2010: 194-208

Tobias Schubert, Matthew D. T. Lewis, Bernd Becker: PaMiraXT: Parallel SAT Solving with Threads and Message Passing. JSAT 6(4): 203-222 (2009)

Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian: SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. 14(4) (2009)

Eckard Böde, Marc Herbstritt, Holger Hermanns, Sven Johr, Thomas Peikenkamp, Reza Pulungan, Jan Rakow, Ralf Wimmer, Bernd Becker: Compositional Dependability Evaluation for STATEMATE. IEEE Trans. Software Eng. 35(2): 274-292 (2009)

Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: Dynamic Compaction in SAT-Based ATPG. Asian Test Symposium 2009: 187-190

Kunal P. Ganeshpure, Ilia Polian, Sandip Kundu, Bernd Becker: Reducing temperature variability by routing heat pipes. ACM Great Lakes Symposium on VLSI 2009: 63-68

Paolo Marin, Massimo Narizzano, Enrico Giunchiglia, Matthew D. T. Lewis, Tobias Schubert, Bernd Becker: Comparison of knowledge sharing strategies in a parallel QBF solver. HPCS 2009: 161-167

Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker: ATPG-based grading of strong fault-secureness. IOLTS 2009: 269-274

Matthew D. T. Lewis, Tobias Schubert, Bernd Becker: QmiraXT - A Multithreaded QBF Solver. MBMV 2009: 7-16

Stefan Kupferschmid, Tino Teige, Bernd Becker, Martin Fränzle: Proofs of Unsatisfiability for mixed Boolean and Non-linear Arithmetic Constraint Formulae. MBMV 2009: 27-36

Natalia Kalinnik, Tobias Schubert, Erika Ábrahám, Ralf Wimmer, Bernd Becker: Picoso - A Parallel Interval Constraint Solver. PDPTA 2009: 473-479

Matthew D. T. Lewis, Paolo Marin, Tobias Schubert, Massimo Narizzano, Bernd Becker, Enrico Giunchiglia: PaQuBE: Distributed QBF Solving with Advanced Knowledge Sharing. SAT 2009: 509-523

Abhishek Dhama, Oliver E. Theel, Pepijn Crouzen, Holger Hermanns, Ralf Wimmer, Bernd Becker: Dependability Engineering of Silent Self-stabilizing Systems. SSS 2009: 238-253

Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. VLSI Design 2009: 227-232

Ralf Wimmer, Bettina Braitling, Bernd Becker: Counterexample Generation for Discrete-Time Markov Chains Using Bounded Model Checking. VMCAI 2009: 366-380

Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker: An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. VTS 2009: 21-26

Bernd Becker, Paul Molitor: Technische Informatik - eine einführende Darstellung. Oldenbourg 2008, isbn 978-3-486-58650-3, pp. I-XVI, 1-419

Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008)

Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker: Resistive Bridging Fault Simulation of Industrial Circuits. DATE 2008: 628-633

Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker: Probabilistic Model Checking and Reliability of Results. DDECS 2008: 207-212

Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen: Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS 2008: 263-266

Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker: On Reducing Circuit Malfunctions Caused by Soft Errors. DFT 2008: 245-253

Damian Nowroth, Ilia Polian, Bernd Becker: A study of cognitive resilience in a JPEG compressor. DSN 2008: 32-41

Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker: A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. European Test Symposium 2008: 113-118

Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker: Selective Hardening in Early Design Steps. European Test Symposium 2008: 185-190

Bernd Becker, Marc Herbstritt, Natalia Kalinnik, Matthew D. T. Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer: Propositional approximations for bounded model checking of partial circuit designs. ICCD 2008: 52-59

Ilia Polian, Sudhakar M. Reddy, Bernd Becker: Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. ISVLSI 2008: 257-262

Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. ITC 2008: 1-10

Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker: The Demand for Reliability in Probabilistic Verification. MBMV 2008: 99-108

Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng: Automatic Test Pattern Generation for Interconnect Open Defects. VTS 2008: 181-186

Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker: Power Droop Testing. IEEE Design & Test of Computers 24(3): 276-284 (2007)

Erika Ábrahám, Marc Herbstritt, Bernd Becker, Martin Steffen: Bounded Model Checking with Parametric Data Structures. Electr. Notes Theor. Comput. Sci. 174(3): 3-16 (2007)

Bernd Becker, Andreas Podelski, Werner Damm, Martin Fränzle, Ernst-Rüdiger Olderog, Reinhard Wilhelm: SFB/TR 14 AVACS - Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS - Automatische Verifikation und Analyse komplexer Systeme). it - Information Technology 49(2): 118-126 (2007)

Matthew D. T. Lewis, Tobias Schubert, Bernd Becker: Multithreaded SAT Solving. ASP-DAC 2007: 926-931

Bernd Becker, Christian Dax, Jochen Eisinger, Felix Klaedtke: LIRA: Handling Constraints of Linear Arithmetics over the Integers and the Reals. CAV 2007: 307-310

Marc Herbstritt, Bernd Becker, Erika Ábrahám, Christian Herde: On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata. DDECS 2007: 391-396

Marc Herbstritt, Bernd Becker: On Combining 01X-Logic and QBF. EUROCAST 2007: 531-538

Ralf Wimmer, Marc Herbstritt, Bernd Becker: Optimization techniques for BDD-based bisimulation computation. ACM Great Lakes Symposium on VLSI 2007: 405-410

Tobias Nopper, Christoph Scholl, Bernd Becker: Computation of minimal counterexamples by using black box techniques and symbolic methods. ICCAD 2007: 273-280

Ilia Polian, Damian Nowroth, Bernd Becker: Identification of Critical Errors in Imaging Applications. IOLTS 2007: 201-202

Bernd Becker: AVACS -- Automatic Verification and Analysis of Complex Systems. MBMV 2007: 79-80

Ralf Wimmer, Marc Herbstritt, Bernd Becker: Forwarding, Splitting, and Block Ordering to Optimize BDD-based Bisimulation Computation. MBMV 2007: 203-212

Marc Herbstritt, Vanessa Struve, Bernd Becker: Application of Lifting in Partial Design Analysis. MTV 2007: 33-38

John P. Hayes, Ilia Polian, Bernd Becker: An Analysis Framework for Transient-Error Tolerance. VTS 2007: 249-255

Ilia Polian, Alejandro Czutro, Bernd Becker: Evolutionary Optimization in Code-Based Test Compression. CoRR abs/0710.4670 (2007)

Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, O. Paul, Ilia Polian, R. Roth, K. Seitz, P. Ruther: Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. CoRR abs/0711.3289 (2007)

Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Automatic Test Pattern Generation for Resistive Bridging Faults. J. Electronic Testing 22(1): 61-69 (2006)

Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich: DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). it - Information Technology 48(5): 304- (2006)

Thomas Eschbach, Wolfgang Günther, Bernd Becker: Orthogonal Hypergraph Drawing for Improved Visibility. J. Graph Algorithms Appl. 10(2): 141-157 (2006)

Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive-Bridging and Stuck-At Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2181-2192 (2006)

Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke: X-masking during logic BIST and its impact on defect coverage. IEEE Trans. VLSI Syst. 14(2): 193-202 (2006)

Ralf Wimmer, Marc Herbstritt, Holger Hermanns, Kelley Strampp, Bernd Becker: Sigref- A Symbolic Bisimulation Tool Box. ATVA 2006: 477-492

Ralf Wimmer, Marc Herbstritt, Bernd Becker: Minimization of Large State Spaces using Symbolic Branching Bisimulation. DDECS 2006: 9-14

Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm: Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. DDECS 2006: 15-20

Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara: Low-Cost Hardening of Image Processing Applications Against Soft Errors. DFT 2006: 274-279

Erika Ábrahám, Tobias Schubert, Bernd Becker, Martin Fränzle, Christian Herde: Parallel SAT Solving in Bounded Model Checking. FMICS/PDMC 2006: 301-315

Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker: Power Droop Testing. ICCD 2006

Erika Ábrahám, Marc Herbstritt, Bernd Becker, Martin Steffen: Memory-aware Bounded Model Checking for Linear Hybrid Systems. MBMV 2006: 153-162

Marc Herbstritt, Bernd Becker, Christoph Scholl: Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs. MTV 2006: 37-44

Eckard Böde, Marc Herbstritt, Holger Hermanns, Sven Johr, Thomas Peikenkamp, Reza Pulungan, Ralf Wimmer, Bernd Becker: Compositional Performability Evaluation for STATEMATE. QEST 2006: 167-178

Jan Reineke, Björn Wachter, Stephan Thesing, Reinhard Wilhelm, Ilia Polian, Jochen Eisinger, Bernd Becker: A Definition and Classification of Timing Anomalies. WCET 2006

Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker: Modeling Feedback Bridging Faults with Non-Zero Resistance. J. Electronic Testing 21(1): 57-69 (2005)

Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Asian Test Symposium 2005: 266-271

Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes: A Family of Logical Fault Models for Reversible Circuits. Asian Test Symposium 2005: 422-427

Ilia Polian, Alejandro Czutro, Bernd Becker: Evolutionary Optimization in Code-Based Test Compression. DATE 2005: 1124-1129

Martina Welte, Thomas Eschbach, Bernd Becker: Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface. DeLFI Workshops 2005: 61-66

Tobias Schubert, Bernd Becker: Lemma Exchange in a Microcontroller Based Parallel SAT Solver. ISVLSI 2005: 142-147

Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker: Transient fault characterization in dynamic noisy environments. ITC 2005: 10

Marc Herbstritt, Bernd Becker: On SAT-based Bounded Invariant Checking of Blackbox Designs. MTV 2005: 23-28

Tobias Schubert, Matthew D. T. Lewis, Bernd Becker: PaMira - A Parallel SAT Solver with Knowledge Sharing. MTV 2005: 29-36

Tobias Schubert, Bernd Becker: Knowledge Sharing in a Microcontroller based Parallel SAT Solver. PDPTA 2005: 1049-1055

Jochen Eisinger, Peter Winterer, Bernd Becker: Securing Wireless Networks in a University Environment. PerCom Workshops 2005: 312-316

Matthew D. T. Lewis, Tobias Schubert, Bernd Becker: Speedup Techniques Utilized in Modern SAT Solvers. SAT 2005: 437-443

Thomas Eschbach, Wolfgang Günther, Bernd Becker: Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases. VLSI Design 2005: 433-438

Erika Ábrahám, Bernd Becker, Felix Klaedtke, Martin Steffen: Optimizing Bounded Model Checking for Linear Hybrid Systems. VMCAI 2005: 396-412

Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker: Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348

Bernd Becker, Markus Behle, Friedrich Eisenbrand, Ralf Wimmer: BDDs in a Branch and Cut Framework. WEA 2005: 452-463

Ilia Polian, Bernd Becker: Scalable Delay Fault BIST for Use with Low-Cost ATE. J. Electronic Testing 20(2): 181-197 (2004)

Tobias Schubert, Bernd Becker: Parallel SAT Solving with Microcontrollers. AACC 2004: 59-67

Tobias Schubert, Bernd Becker: A Distributed SAT Solver for Microcontroller. ARCS Workshops 2004: 338-347

John P. Hayes, Ilia Polian, Bernd Becker: Testing for Missing-Gate Faults in Reversible Circuits. Asian Test Symposium 2004: 100-105

Thomas Eschbach, Wolfgang Günther, Bernd Becker: Orthogonal hypergraph routing for improved visibility. ACM Great Lakes Symposium on VLSI 2004: 385-388

Thomas Eschbach, Rolf Drechsler, Bernd Becker: Placement and routing optimization for circuits derived from BDDs. ISCAS (5) 2004: 229-232

Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker: X-Masking During Logic BIST and Its Impact on Defect Coverage. ITC 2004: 442-451

Bernd Becker, Markus Behle, Friedrich Eisenbrand, Martin Fränzle, Marc Herbstritt, Christian Herde, Jörg Hoffmann, Daniel Kröning, Bernhard Nebel, Ilia Polian, Ralf Wimmer: Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems. MBMV 2004: 65-75

Matthew D. T. Lewis, Tobias Schubert, Bernd Becker: Early Conflict Detection Based SAT Solving. MBMV 2004: 243-249

Marc Herbstritt, Thomas Kmieciak, Bernd Becker: On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification. MTV 2004: 50-55

Tobias Schubert, Bernd Becker: PICHAFF² - A Hierarchical Parallel SAT Solver. MTV 2004: 56-61

Matthew D. T. Lewis, Tobias Schubert, Bernd Becker: Early Conflict Detection Based BCP for SAT Solving. SAT 2004

Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker: The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. VTS 2004: 171-178

Ilia Polian, Bernd Becker: Multiple Scan Chain Design for Two-Pattern Testing. J. Electronic Testing 19(1): 37-48 (2003)

Jonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker: Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting. J. Electronic Testing 19(4): 387-395 (2003)

Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor: Polynomial Formal Verification of Multipliers. Formal Methods in System Design 22(1): 39-58 (2003)

Ilia Polian, Wolfgang Günther, Bernd Becker: Pattern-based verification of connections to intellectual property cores. Integration 35(1): 25-44 (2003)

Frank Schmiedle, Rolf Drechsler, Bernd Becker: Exact Routing with Search Space Reduction. IEEE Trans. Computers 52(6): 815-825 (2003)

Ilia Polian, Bernd Becker, Sudhakar M. Reddy: Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. DATE 2003: 11184-11185

Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive Bridging and Stuck-At Faults. ITC 2003: 1051-1059

Ilia Polian, Wolfgang Günther, Bernd Becker: The Case for 2-POF. MBMV 2003: 164-173

Marc Herbstritt, Bernd Becker: Conflict-based Selection of Branching Rules in SAT-Algorithms. MBMV 2003: 189-198

Marc Herbstritt, Bernd Becker: Conflict-Based Selection of Branching Rules. SAT 2003: 441-451

Thomas Eschbach, Wolfgang Günther, Bernd Becker: Cross Reduction for Orthogonal Circuit Visualization. VLSI 2003: 107-113

Ilia Polian, Bernd Becker: Reducing ATE Cost in System-on-Chip Test. VLSI-SOC 2003: 337-342

Christoph Scholl, Bernd Becker, Thomas M. Weis: On WLCDs and the Complexity of Word-Level Decision Diagrams-A Lower Bound for Division. Formal Methods in System Design 20(3): 311-326 (2002)

Ilia Polian, Irith Pomeranz, Bernd Becker: Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. Asian Test Symposium 2002: 2-14

Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker: Crossing Reduction by Windows Optimization. Graph Drawing 2002: 285-294

Christoph Scholl, Bernd Becker: Checking Equivalence for Circuits Containing Incompletely Specified Boxes. ICCD 2002: 56-63

Ilia Polian, Bernd Becker: Stop & Go BIST. IOLTW 2002: 147-151

Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker: Sequential n -Detection Criteria: Keep It Simple. IOLTW 2002: 189

Ilia Polian, Piet Engelke, Bernd Becker: Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. ISMVL 2002: 216-

Klaus-Jürgen Englert, Bernd Becker, Rolf Drechsler: Symbolic Simulation of Algorithms Specified in HDL. MBMV 2002: 113-122

Christoph Scholl, Bernd Becker: Equivalence Checking in the Presence of Incompletely Specified Boxes. MBMV 2002: 239-248

Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. J. Electronic Testing 17(1): 37-51 (2001)

Christoph Scholl, Bernd Becker, Andreas Brogle: The multiple variable order problem for binary decision diagrams: theory and practical application. ASP-DAC 2001: 85-90

Wolfgang Günther, Andreas Hett, Bernd Becker: Application of linearly transformed BDDs in sequential verification. ASP-DAC 2001: 91-96

Ilia Polian, Wolfgang Günther, Bernd Becker: Efficient Pattern-Based Verification of Connections to IP Cores . Asian Test Symposium 2001: 443-448

Christoph Scholl, Bernd Becker: Checking Equivalence for Partial Implementations. DAC 2001: 238-243

Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther: Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. DSD 2001: 54-61

Nicole Drechsler, Rolf Drechsler, Bernd Becker: Multi-objective Optimisation Based on Relation Favour. EMO 2001: 154-166

Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker: Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. Fuzzy Days 2001: 479-491

Christoph Scholl, Marc Herbstritt, Bernd Becker: Exploiting don't cares to minimize *BMDs. ISCAS (5) 2001: 191-194

Andreas Hett, Bernd Becker: Supervised Dynamic Recording in Model Checking. MBMV (1) 2001: 21-30

Christoph Scholl, Bernd Becker: Checking Equivalence for Partial Implementations. MBMV (1) 2001: 31-43

Christoph Scholl, Marc Herbstritt, Bernd Becker: Don't Care Minimization of BMDs: Complexity and Algorithms. MBMV (1) 2001: 45-57

Ilia Polian, Wolfgang Günther, Bernd Becker: Efficient Pattern-Based Verification of Connections to Intellectual Property Cores. MBMV (1) 2001: 111-120

Ilia Polian, Bernd Becker: Multiple Scan Chain Design for Two-Pattern Testing. VTS 2001: 88-93

Rolf Drechsler, Bernd Becker, Nicole Drechsler: OKFDD minimization by genetic algorithms with application to circuit design. Integration 28(2): 121-139 (2000)

Andreas Hett, Christoph Scholl, Bernd Becker: Distance driven finite state machine traversal. DAC 2000: 39-42

Christoph Scholl, Bernd Becker: On the Generation of Multiplexer Circuits for Pass Transistor Logic. DATE 2000: 372-378

Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Verification of Designs Containing Black Boxes. EUROMICRO 2000: 1100-1105

Rolf Drechsler, Wolfgang Günther, Bernd Becker: Testability of Circuits Derived from Lattice Diagrams. EUROMICRO 2000: 1188-1192

Rolf Drechsler, Nicole Drechsler, Elke Mackensen, Tobias Schubert, Bernd Becker: Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System. EUROMICRO 2000: 1425-

Wolfgang Günther, Robby Schönfeld, Bernd Becker, Paul Molitor: k-Layer Straightline Crossing Minimization by Speeding Up Sifting. Graph Drawing 2000: 253-258

Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Specialized Hardware for Implementation of Evolutionary Algorithms. GECCO 2000: 369

Per Lindgren, Rolf Drechsler, Bernd Becker: Minimization of Ordered Pseudo Kronecker Decision Diagrams. ICCD 2000: 504-

Frank Schmiedle, Daniel Unruh, Bernd Becker: Exact switchbox routing with search space reduction. ISPD 2000: 26-32

Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Verification of Designs Containing Black Boxes. MBMV 2000: 19-26

Andreas Hett, Christoph Scholl, Bernd Becker: State Traversal guided by Hamming Distance Profiles. MBMV 2000: 57-66

Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker: Testability of 2-Level AND/EXOR Circuits. J. Electronic Testing 14(3): 219-225 (1999)

Bernd Becker, Martin Keim, Rolf Krieger: Hybrid Fault Simulation for Synchronous Sequential Circuits. J. Electronic Testing 15(3): 219-238 (1999)

Martin Keim, Nicole Drechsler, Bernd Becker: Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. ASP-DAC 1999: 315-318

Harry Hengster, Bernd Becker: Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability. FTCS 1999: 268-275

Nicole Drechsler, Rolf Drechsler, Bernd Becker: Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes. Fuzzy Days 1999: 108-117

Per Lindgren, Rolf Drechsler, Bernd Becker: Synthesis of Pseudo Kronecker Lattice Diagrams. ICCD 1999: 307-310

Frank Schmiedle, Rolf Drechsler, Bernd Becker: Exact channel routing using symbolic representation. ISCAS (6) 1999: 394-397

Rolf Drechsler, Marc Herbstritt, Bernd Becker: Grouping heuristics for word-level decision diagrams. ISCAS (1) 1999: 411-414

Rolf Drechsler, Marc Herbstritt, Bernd Becker: Grouping Heuristics for Word-Level Decision Diagrams. MBMV 1999: 41-50

Rolf Drechsler, Bernd Becker: Graphenbasierte Funktionsdarstellung - Boolesche und Pseudo-Boolesche Funktionen. Leitfäden der Informatik, Teubner 1998, isbn 978-3-519-02149-0, pp. 1-200

Rolf Drechsler, Bernd Becker: Binary Decision Diagrams - Theory and Implementation. Springer 1998, isbn 978-0-7923-8193-8, pp. I-X, 1-200

Bernd Becker: Testing with decision diagrams. Integration 26(1-2): 5-20 (1998)

Rolf Drechsler, Bernd Becker, Andrea Jahnke: On Variable Ordering and Decomposition Type Choice in OKFDDs. IEEE Trans. Computers 47(12): 1398-1403 (1998)

Rolf Drechsler, Bernd Becker: Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 965-973 (1998)

Christoph Scholl, Bernd Becker, Thomas M. Weis: Word-level decision diagrams, WLCDs and division. ICCAD 1998: 672-677

Per Lindgren, Rolf Drechsler, Bernd Becker: Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions. ISMVL 1998: 95-

Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. ISMVL 1998: 215-

Rolf Drechsler, Bernd Becker, Stefan Ruppertz: The K*BMD: A Verification Data Structure. IEEE Design & Test of Computers 14(2): 51-59 (1997)

Bernd Becker, Rolf Drechsler, Michael Theobald: On the Expressive Power of OKFDDs. Formal Methods in System Design 11(1): 5-21 (1997)

Rolf Drechsler, Bernd Becker: Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 1-5 (1997)

Bernd Becker, Rolf Drechsler, Reinhard Enders: On the representational power of bit-level and word-level decision diagrams. ASP-DAC 1997: 461-467

Nicole Göckel, Rolf Drechsler, Bernd Becker: Learning heuristics for OKFDD minimization by evolutionary algorithms. ASP-DAC 1997: 469-472

Andreas Hett, Rolf Drechsler, Bernd Becker: Fast and efficient construction of BDDs by reordering based synthesis. ED&TC 1997: 168-175

Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker: Testability of 2-level AND/EXOR circuits. ED&TC 1997: 548-553

Christoph Scholl, Rolf Drechsler, Bernd Becker: Functional simulation using binary decision diagrams. ICCAD 1997: 8-12

Rolf Drechsler, Martin Keim, Bernd Becker: Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions. ISMVL 1997: 66-

Rolf Drechsler, Martin Keim, Bernd Becker: Fault Simulation in Sequential Multi-Valued Logic Networks. ISMVL 1997: 145-

Rolf Drechsler, Bernd Becker, Stefan Ruppertz: Manipulation Algorithms for K*BMDs. TACAS 1997: 4-18

Bernd Becker, Rolf Drechsler: Decision Diagrams in Synthesis - Algorithms, Applications and Extensions. VLSI Design 1997: 46-50

Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy: (Quasi-) Linear Path Delay Fault Tests for Adders. VLSI Design 1997: 101-105

Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor: Polynomial Formal Verification of Multipliers. VTS 1997: 150-157

Can Ökmen, Martin Keim, Rolf Krieger, Bernd Becker: On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms. VTS 1997: 426-433

Rolf Drechsler, Michael Theobald, Bernd Becker: Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions. IEEE Trans. Computers 45(11): 1294-1299 (1996)

Harry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer: AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. Asian Test Symposium 1996: 148-

Harry Hengster, Uwe Sparmann, Bernd Becker, Sudhakar M. Reddy: Local Transformations and Robust Dependent Path Delay. ITC 1996: 347-356

Rolf Drechsler, Nicole Göckel, Bernd Becker: Learning Heuristics for OBDD Minimization by Evolutionary Algorithms. PPSN 1996: 730-739

Martin Keim, Bernd Becker, Birgitta Stenner: On the (non-)resetability of synchronous sequential circuits. VTS 1996: 240-245

Harry Hengster, Rolf Drechsler, Bernd Becker: On local transformations and path delay fault testability. J. Electronic Testing 7(3): 173-191 (1995)

Bernd Becker, Rolf Drechsler, Ralph Werchner: On the Relation between BDDs and FDDs. Inf. Comput. 123(2): 185-197 (1995)

Bernd Becker, Ralf Hahn, Joachim Hartmann, Uwe Sparmann: On the testability of iterative logic arrays. Integration 18(2-3): 201-218 (1995)

Bernd Becker, Rolf Drechsler, Paul Molitor: On the generation of area-time optimal testable adders. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1049-1066 (1995)

Rolf Drechsler, Bernd Becker: Learning heuristics by genetic algorithms. ASP-DAC 1995

Rolf Krieger, Bernd Becker, Martin Keim: Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy. DAC 1995: 339-344

Rolf Krieger, Bernd Becker, Can Ökmen: OBDD-based Optimization of Input Probabilities for Weighted Random Pattern Generation. FTCS 1995: 120-129

Bernd Becker, Rolf Drechsler, Michael Theobald: OKFDDs versus OBDDs and OFDDs. ICALP 1995: 475-486

Rolf Drechsler, Bernd Becker: Dynamic minimization of OKFDDs. ICCD 1995: 602-

Rolf Drechsler, Rolf Krieger, Bernd Becker: Random Pattern Fault Simulation in Multi-Valued Circuits. ISMVL 1995: 98-103

Bernd Becker, Rolf Drechsler, Ralph Werchner: On the Relation Betwen BDDs and FDDs. LATIN 1995: 72-83

Harry Hengster, Rolf Drechsler, Bernd Becker: On the application of local circuit transformations with special emphasis on path delay fault testability. VTS 1995: 387-392

Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski: Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams. DAC 1994: 415-419

Rolf Drechsler, Bernd Becker, Michael Theobald: Fast OFDD based minimization of fixed polarity Reed-Muller expressions. EURO-DAC 1994: 2-7

Ralf Hahn, Rolf Krieger, Bernd Becker: A Hierarchical Approach to Fault Collapsing. EDAC-ETC-EUROASIC 1994: 171-176

Bernd Becker, Rolf Drechsler: Testability of Circuits Derived from Functional Decision Diagrams. EDAC-ETC-EUROASIC 1994: 667

Bernd Becker, Rolf Drechsler: OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms. ICCD 1994: 106-110

Bernd Becker, Rolf Drechsler: Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms. ISMVL 1994: 65-72

Rolf Krieger, Bernd Becker, Martin Keim: A Hybrid Fault Simulator for Synchronous Sequential Circuits. ITC 1994: 614-623

Harry Hengster, Rolf Drechsler, Bernd Becker: Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model. VLSI Design 1994: 123-126

Rolf Krieger, Bernd Becker, R. Sinkovic: A BDD - based Algorithm for Computation of Exact Fault Detection Probabilities. FTCS 1993: 186-195

Bernd Becker, Rolf Krieger: FAST-SC: Fast Fault Simulation in Synchronous Sequential Circuits. VLSI Design 1993: 128-131

Bernd Becker, Joachim Hartmann: Some Remarks on the Test Complexity of Iterative Logic Arrays. MFCS 1992: 142-152

Bernd Becker: Synthesis for Testability: Binary Decision Diagrams. STACS 1992: 501-512

Bernd Becker, Uwe Sparmann: A uniform test approach for RCC-adders. Fundam. Inform. 14(2): 185-219 (1991)

Bernd Becker, Uwe Sparmann: Computations over Finite Monoids and their Test Complexity. Theor. Comput. Sci. 84(2): 225-250 (1991)

Bernd Becker, Joachim Hartmann: Optimal-Time Multipliers and C-Testability. Elektronische Informationsverarbeitung und Kybernetik 26(10): 547-561 (1990)

Bernd Becker, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor, Hans-Georg Osthof, Gisela Pitsch, Uwe Sparmann: A graphical system for hierarchical specifications and checkups of VLSI circuits. EURO-DAC 1990: 174-179

Bernd Becker, Joachim Hartmann: Optimal-Time Multipliers and C-Testability. SPAA 1990: 146-154

Bernd Becker, Uwe Sparmann: Computations over finite monoids and their test complexity. FTCS 1989: 299-306

Bernd Becker, Hans-Ulrich Simon: How Robust Is The n-Cube? Inf. Comput. 77(2): 162-178 (1988)

Bernd Becker: Efficient Testing of Optimal Time Adders. IEEE Trans. Computers 37(9): 1113-1121 (1988)

Bernd Becker, Uwe Sparmann: Regular Structures and Testing: RCC-Adders. AWOC 1988: 288-300

Bernd Becker, Reiner Kolla: On the Construction of Optimal Time Adders (Extended Abstract). STACS 1988: 18-28

Bernd Becker: An Easily Testable Optimal-Time VLSI-Multiplier. Acta Inf. 24(4): 363-380 (1987)

Bernd Becker, Hans-Georg Osthof: Layouts with Wires of Balanced Length. Inf. Comput. 73(1): 45-59 (1987)

Bernd Becker, Günter Hotz: On the Optimal Layout of Planar Graphs with Fixed Boundary. SIAM J. Comput. 16(5): 946-972 (1987)

Bernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof: Hierarchical Design Based on a Calculus of Nets. DAC 1987: 649-653

Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor: Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I. Inform., Forsch. Entwickl. 1(1): 38-47 (1986)

Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor: Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II. Inform., Forsch. Entwickl. 1(2): 72-82 (1986)

Bernd Becker, Hans-Ulrich Simon: How Robust Is the n-Cube? (Extended Abstract). FOCS 1986: 283-291

Bernd Becker: Efficient Testing of Optimal Time Adders (Extended Abstract). MFCS 1986: 218-229

Bernd Becker, Hans-Georg Osthof: Layouts with Wires of Balanced Length. STACS 1985: 21-31

Bernd Becker: On the crossing-free, rectangular embedding of weighted graphs in the plane. Theoretical Computer Science 1983: 61-72