Yoji Bando

Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho: A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. ISSCC 2013: 272-273

Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: On-Chip In-Place Measurements of V_th and Signal/Substrate Response of Differential Pair Transistors. IEICE Transactions 95-C(1): 137-145 (2012)

Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. IEICE Transactions 94-C(4): 495-503 (2011)

Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. IEICE Transactions 94-C(6): 1024-1031 (2011)

Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata: Accurate analysis of substrate sensitivity of active transistors in an analog circuit. ISQED 2011: 56-61

Daisuke Kosaka, Yoji Bando, Goichi Yokomizo, Kunihiko Tsuboi, Ying Shiun Li, Shen Lin, Makoto Nagata: A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design. CICC 2009: 219-222