R. Iris Bahar

Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera: NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. J. Electronic Testing 28(3): 349-363 (2012)

Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar: Using implications to choose tests through suspect fault identification. ACM Trans. Design Autom. Electr. Syst. 18(1): 14 (2012)

Roto Le, Joseph L. Mundy, R. Iris Bahar: High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System. ASAP 2012: 16-23

Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda: Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. FCCM 2012: 65-68

Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy: A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. ACM Great Lakes Symposium on VLSI 2012: 39-44

Desta Tadesse, R. Iris Bahar, Joel Grodstein: Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems. J. Electronic Testing 27(2): 123-136 (2011)

Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini, Maurice Herlihy: SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs. CODES+ISSS 2011: 39-48

Nuno Alves, Y. Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar: Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. European Test Symposium 2011: 211

Roto Le, R. Iris Bahar, Joseph L. Mundy: A novel parallel Tier-1 coder for JPEG2000 using GPUs. SASP 2011: 129-136

Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal: Enhancing online error detection through area-efficient multi-site implications. VTS 2011: 241-246

Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems. J. Parallel Distrib. Comput. 70(10): 1042-1052 (2010)

Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Dual-V_t assignment policies in ITD-aware synthesis. Microelectronics Journal 41(9): 547-553 (2010)

Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar: A Cost Effective Approach for Online Error Detection Using Invariant Relationships. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 788-801 (2010)

Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Temperature-Insensitive Dual- V_th Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. IEEE Trans. VLSI Syst. 18(11): 1608-1620 (2010)

Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar: Improving the testability and reliability of sequential circuits with invariant logic. ACM Great Lakes Symposium on VLSI 2010: 131-134

Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. ACM Great Lakes Symposium on VLSI 2010: 281-286

Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. HiPEAC 2010: 50-65

R. Iris Bahar, Fabrizio Lombardi, David Atienza, Erik Brunvand (Eds.): Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010. ACM 2010, isbn 978-1-4503-0012-4

R. Iris Bahar: Introduction to special section: Best of NANOARCH 2008. JETC 5(2) (2009)

Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar: Detecting errors using multi-cycle invariance information. DATE 2009: 791-796

Roto Le, Sherief Reda, R. Iris Bahar: High-performance, cost-effective heterogeneous 3D FPGA architectures. FPGA 2009: 286

Cesare Ferri, R. Iris Bahar, Mirko Loghi, Massimo Poncino: Energy-optimal synchronization primitives for single-chip multi-processors. ACM Great Lakes Symposium on VLSI 2009: 141-144

Roto Le, Sherief Reda, R. Iris Bahar: High-performance, cost-effective heterogeneous 3D FPGA architectures. ACM Great Lakes Symposium on VLSI 2009: 251-256

Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal: Compacting test vector sets via strategic use of implications. ICCAD 2009: 83-88

Sherief Reda, Aung Si, R. Iris Bahar: Reducing the leakage and timing variability of 2D ICcs using 3D ICs. ISLPED 2009: 283-286

Desta Tadesse, Joel Grodstein, R. Iris Bahar: AutoRex: An automated post-silicon clock tuning tool. ITC 2009: 1-10

Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar (Eds.): Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009. ACM 2009, isbn 978-1-60558-522-2

R. Iris Bahar, Krishnendu Chakrabarty: Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. JETC 4(2) (2008)

Cesare Ferri, Sherief Reda, R. Iris Bahar: Parametric yield management for 3D ICs: Models and strategies for improvement. JETC 4(4) (2008)

Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino: Thermal-Aware Design Techniques for Nanometer CMOS Circuits. J. Low Power Electronics 4(3): 374-384 (2008)

R. Iris Bahar, Krishnendu Chakrabarty: Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. ACM Trans. Design Autom. Electr. Syst. 13(2) (2008)

Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar: Temperature-insensitive synthesis using multi-vt libraries. ACM Great Lakes Symposium on VLSI 2008: 5-10

Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy efficient synchronization techniques for embedded architectures. ACM Great Lakes Symposium on VLSI 2008: 435-440

Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ISLPED 2008: 217-220

Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar: Using Implications for Online Error Detection. ITC 2008: 1-10

Desta Tadesse, R. Iris Bahar, Joel Grodstein: Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. VTS 2008: 339-344

R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram: Architectures for Silicon Nanoelectronics and Beyond. IEEE Computer 40(1): 25-33 (2007)

Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electronic Testing 23(2-3): 255-266 (2007)

Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy: A hardware/software framework for supporting transactional memory in a MPSoC environment. SIGARCH Computer Architecture News 35(1): 47-54 (2007)

Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE 2007: 576-581

Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein: Accurate timing analysis using SAT and pattern-dependent delay models. DATE 2007: 1018-1023

Cesare Ferri, Sherief Reda, R. Iris Bahar: Strategies for improving the parametric yield and profits of 3D ICs. ICCAD 2007: 220-226

Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. IEEE Micro 26(5): 19-27 (2006)

Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein: Timing analysis for full-custom circuits using symbolic DC formulations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1815-1830 (2006)

Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss: A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. DAC 2006: 705-708

Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing MRF based error correcting circuits for memory elements. DATE 2006: 792-793

Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Optimizing noise-immune nanoscale circuits using principles of Markov random fields. ACM Great Lakes Symposium on VLSI 2006: 149-152

R. Iris Bahar: Trends and Future Directions in Nano Structure Based Computing and Fabrication. ICCD 2006

Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy implications of multiprocessor synchronization. SPAA 2006: 329

R. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi: Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale. IEEE Design & Test of Computers 22(4): 295-297 (2005)

R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein: Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 502-515 (2005)

Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing logic circuits for probabilistic computation in the presence of noise. DAC 2005: 485-490

Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy reduction in multiprocessor systems using transactional memory. ISLPED 2005: 331-334

Yu Bai, R. Iris Bahar: A low-power in-order/out-of-order issue queue. TACO 1(2): 152-179 (2004)

Tali Moreshet, R. Iris Bahar: Effects of speculation on performance and issue queue design. IEEE Trans. VLSI Syst. 12(10): 1123-1126 (2004)

Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein: RESTA: a robust and extendable symbolic timing analysis tool. ACM Great Lakes Symposium on VLSI 2004: 407-412

Yu Bai, R. Iris Bahar: Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm. ICCD 2004: 54-57

Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss: Fetch Halting on Critical Load Misses. ICCD 2004: 244-249

Eric Chi, A. Michael Salem, R. Iris Bahar, Richard S. Weiss: Combining Software and Hardware Monitoring for Improved Power and Performance Tuning. Interaction between Compilers and Computer Architectures 2003: 57-64

Tali Moreshet, R. Iris Bahar: Power-aware issue queue design for speculative instructions. DAC 2003: 634-637

R. Iris Bahar, Joseph L. Mundy, Jie Chen: A Probabilistic-Based Design Methodology for Nanoscale Computation. ICCAD 2003: 480-486

Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein: Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. ICCD 2003: 70-75

Yu Bai, R. Iris Bahar: A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. ISVLSI 2003: 139-148

Hui-Yuan Song, R. Iris Bahar, Joel Grodstein: Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. IWLS 2002: 203-208

R. Iris Bahar, Srilatha Manne: Power and energy reduction via pipeline balancing. ISCA 2001: 218-229

R. Iris Bahar, Ernest T. Lampe, Enrico Macii: Power optimization of technology-dependent circuits based on symbolic computation of logic implications. ACM Trans. Design Autom. Electr. Syst. 5(3): 267-293 (2000)

Roberto Maro, Yu Bai, R. Iris Bahar: Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. PACS 2000: 97-111

R. Iris Bahar, Brad Calder, Dirk Grunwald: A comparison of software code reordering and victim buffers. SIGARCH Computer Architecture News 27(1): 51-54 (1999)

Brian R. Fisk, R. Iris Bahar: The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. ICCD 1999: 538-545

R. Iris Bahar, Gianluca Albera, Srilatha Manne: Power and performance tradeoffs using various caching strategies. ISLPED 1998: 64-69

R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Algebraic Decision Diagrams and Their Applications. Formal Methods in System Design 10(2/3): 171-206 (1997)

R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1101-1115 (1997)

R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi: Symbolic computation of logic implications for technology-dependent low-power synthesis. ISLPED 1996: 163-168

Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino: Computing the Maximum Power Cycles of a Sequential Circuit. DAC 1995: 23-28

R. Iris Bahar, Fabio Somenzi: Boolean techniques for low power driven re-synthesis. ICCAD 1995: 428-432

Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi: CMOS dynamic power estimation based on collapsible current source transistor modeling. ISLPD 1995: 111-116

R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: Timing Analysis of Combinational Circuits using ADD's. EDAC-ETC-EUROASIC 1994: 625-629

R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: A symbolic method to reduce power consumption of circuits containing false paths. ICCAD 1994: 368-371

R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Algebraic decision diagrams and their applications. ICCAD 1993: 188-191