Nadine Azémard

Nadine Azémard, Marc Belleville: Selected Articles from the VARI 2011 Workshop. J. Low Power Electronics 8(1): 82 (2012)

Nadine Azémard, Gilles Jacquemod: Selected Articles from the VARI 2012 Workshop. J. Low Power Electronics 8(5): 696 (2012)

Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme: Delay-correlation-aware SSTA based on conditional moments. Microelectronics Journal 43(4): 263-273 (2012)

Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard: Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectronics Journal 42(5): 718-732 (2011)

Nadine Azémard: Selected Peer-Reviewed Articles from the VARI 2010 Workshop. J. Low Power Electronics 6(4): 563 (2010)

Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson: On-Chip Process Variability Monitoring Flow. J. Low Power Electronics 6(4): 601-606 (2010)

V. Migairou, Robin Wilson, Sylvain Engels, Zequin Wu, Nadine Azémard, Philippe Maurine: Timing margin evaluation with a simple statistical timing analysis flow. J. Embedded Computing 3(3): 221-229 (2009)

Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme: Interpreting SSTA Results with Correlation. PATMOS 2009: 16-25

Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels: Product On-Chip Process Compensation for Low Power and Yield Enhancement. PATMOS 2009: 247-255

Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard: Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS 2009: 266-275

Nadine Azémard, Philippe Maurine, Johan Vounckx: Editorial. Integration 41(1): 1 (2008)

Bettina Rebaud, Marc Belleville, Christian Bernard, Zequin Wu, Michel Robert, Philippe Maurine, Nadine Azémard: Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI 2008: 316-321

B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature- and Voltage-Aware Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 801-815 (2007)

B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature and voltage aware timing analysis: application to voltage drops. DATE 2007: 1012-1017

V. Migairou, Robin Wilson, Sylvain Engels, Zequin Wu, Nadine Azémard, Philippe Maurine: A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. PATMOS 2007: 138-147

Nadine Azémard, Lars J. Svensson (Eds.): Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Lecture Notes in Computer Science 4644, Springer 2007, isbn 978-3-540-74441-2

Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol. CoRR abs/0710.4760 (2007)

Sylvain Engels, Robin Wilson, Nadine Azémard, Philippe Maurine: A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. Integration 39(4): 433-456 (2006)

B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Logical effort model extension to propagation delay representation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1677-1684 (2006)

Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard: Circuit sizing method under delay constraint. ISCAS 2006

B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Timing analysis in presence of supply voltage and temperature variations. ISPD 2006: 10-16

V. Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine: Statistical Characterization of Library Timing Performance. PATMOS 2006: 468-476

Johan Vounckx, Nadine Azémard, Philippe Maurine (Eds.): Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings. Lecture Notes in Computer Science 4148, Springer 2006, isbn 3-540-39094-4

Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol. DATE 2005: 640-645

Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard: Speed Indicators for Circuit Optimization. PATMOS 2005: 618-628

B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature Dependency in UDSM Process. PATMOS 2005: 693-703

Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Delay bound based CMOS gate sizing technique. ISCAS (5) 2004: 189-192

Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Performance Metric Based Optimization Protocol. PATMOS 2004: 100-109

B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Temperature Dependence in Low Power CMOS UDSM Process. PATMOS 2004: 110-118

A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne: Design Optimization with Automated Cell Generation. PATMOS 2004: 722-731

B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Physical Extension of the Logical Effort Model. PATMOS 2004: 838-848

Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: CMOS Gate Sizing under Delay Constraint. PATMOS 2003: 60-69

Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Metric Definition for Circuit Speed Optimization. PATMOS 2003: 451-460

Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne: Transition time modeling in deep submicron CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1352-1363 (2002)

Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne: Gate speed improvement at minimal power dissipation. APCCAS (2) 2002: 325-330

Philippe Maurine, Nadine Azémard, Daniel Auvergne: Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS 2002: 247-257

Nadine Azémard, Daniel Auvergne: POPS: A tool for delay/power performance optimization. Journal of Systems Architecture 47(3-4): 375-382 (2001)

Philippe Maurine, Nadine Azémard, Daniel Auvergne: Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312

Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne: Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335

Nadine Azémard, M. Aline, Daniel Auvergne: Delay bound determination for timing closure satisfaction. ISCAS (5) 2001: 375-378

S. Turgis, Nadine Azémard, Daniel Auvergne: Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD 1995: 129-134

Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne: Post-layout timing simulation of CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1170-1177 (1993)