Todd M. Austin

William Arthur, Biruk Mammo, Ricardo Rodriguez, Todd M. Austin, Valeria Bertacco: Schnauzer: scalable profiling for likely security bug sites. CGO 2013: 1-11

Joseph L. Greathouse, Hongyi Xin, Yixin Luo, Todd M. Austin: A case for unlimited watchpoints. ASPLOS 2012: 159-172

Andrea Pellegrini, Robert Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita V. Adve, Todd M. Austin, Valeria Bertacco: CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions. DATE 2012: 1106-1109

Joseph L. Greathouse, Chelsea LeBlanc, Todd M. Austin, Valeria Bertacco: Highly scalable distributed dataflow analysis. CGO 2011: 277-288

Jason Clemons, Andrew Jones, Robert Perricone, Silvio Savarese, Todd M. Austin: EFFEX: an embedded processor for computer vision based feature extraction. DAC 2011: 1020-1025

Jason Clemons, Haishan Zhu, Silvio Savarese, Todd M. Austin: MEVBench: A mobile computer vision benchmarking suite. IISWC 2011: 91-102

Joseph L. Greathouse, Zhiqiang Ma, Matthew I. Frank, Ramesh Peri, Todd M. Austin: Demand-driven software race detection using hardware performance counters. ISCA 2011: 165-176

Kypros Constantinides, Todd M. Austin: Using introspective software-based testing for post-silicon debug and repair. DAC 2010: 537-542

Daniel Gajski, Todd M. Austin, Steve Svoboda: What input-language is the best choice for high level synthesis (HLS)? DAC 2010: 857-858

Andrea Pellegrini, Valeria Bertacco, Todd M. Austin: Fault-based attack of RSA authentication. DATE 2010: 855-860

Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco: A Flexible Software-Based Framework for Online Detection of Hardware Defects. IEEE Trans. Computers 58(8): 1063-1079 (2009)

Bo Zhai, Sanjay Pant, Leyla Nazhandali, Scott Hanson, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Todd M. Austin, Dennis Sylvester, David Blaauw: Energy-Efficient Subthreshold Processor Design. IEEE Trans. VLSI Syst. 17(8): 1127-1137 (2009)

Todd M. Austin, Valeria Bertacco, Scott A. Mahlke, Yu Cao: Reliable Systems on Unreliable Fabrics. IEEE Design & Test of Computers 25(4): 322-332 (2008)

Mojtaba Mehrara, Todd M. Austin: Exploiting selective placement for low-cost memory protection. TACO 5(3) (2008)

Ilya Wagner, Valeria Bertacco, Todd M. Austin: Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 380-393 (2008)

Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin: CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. ICCD 2008: 363-370

Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd M. Austin: Polymorphic On-Chip Networks. ISCA 2008: 101-112

Todd M. Austin: On the rules of low-power design (and how to break them). ISLPED 2008: 381-382

Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie: Testudo: Heavyweight security analysis via statistical sampling. MICRO 2008: 117-128

Kypros Constantinides, Onur Mutlu, Todd M. Austin: Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. MICRO 2008: 282-293

Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky: Architecting a reliable CMP switch architecture. TACO 4(1) (2007)

Ilya Wagner, Valeria Bertacco, Todd M. Austin: Microprocessor Verification via Feedback-Adjusted Markov Models. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1126-1138 (2007)

Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin: Low-cost protection for SER upsets and silicon defects. DATE 2007: 1146-1151

Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd M. Austin: Architectural implications of brick and mortar silicon manufacturing. ISCA 2007: 244-253

Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco: Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. MICRO 2007: 97-108

Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. CoRR abs/0710.4679 (2007)

Mojtaba Mehrara, Todd M. Austin: Reliability-aware data placement for partial memory protection in embedded processors. Memory System Performance and Correctness 2006: 11-18

Ilya Wagner, Valeria Bertacco, Todd M. Austin: Depth-driven verification of simultaneous interfaces. ASP-DAC 2006: 442-447

Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin: Ultra low-cost defect protection for microprocessor pipelines. ASPLOS 2006: 73-82

Ilya Wagner, Valeria Bertacco, Todd M. Austin: Shielding against design flaws with field repairable control logic. DAC 2006: 344-347

Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky: BulletProof: a defect-tolerant CMP switch architecture. HPCA 2006: 5-16

Todd M. Austin: Robust low power computing in the nanoscale era. SBCCI 2006: 6

Todd M. Austin: Razor: a low-power pipeline based on circuit-level timing speculation. SBCCI 2006: 13

Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge: Opportunities and challenges for better than worst-case design. ASP-DAC 2005: 2-7

Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David Blaauw: A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. CASES 2005: 249-256

Ilya Wagner, Valeria Bertacco, Todd M. Austin: StressTest: an automatic approach to test generation via activity monitors. DAC 2005: 783-788

Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE 2005: 80-85

Todd M. Austin, Valeria Bertacco: Deployment of Better Than Worst-Case Design: Solutions and Needs. ICCD 2005: 550-558

Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw: Energy Optimization of Subthreshold-Voltage Sensor Network Processors. ISCA 2005: 197-207

David Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Error Analysis for the Support of Robust Voltage Scaling. ISQED 2005: 65-70

Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Making Typical Silicon Matter with Razor. IEEE Computer 37(3): 57-65 (2004)

Todd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf: Mobile Supercomputers. IEEE Computer 37(5): 81-83 (2004)

Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner: Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004)

Doug Burger, Todd M. Austin, Stephen W. Keckler: Recent extensions to the SimpleScalar tool suite. SIGMETRICS Performance Evaluation Review 31(4): 4-7 (2004)

Rajeev Krishna, Scott A. Mahlke, Todd M. Austin: Memory system design space exploration for low-power, real-time speech recognition. CODES+ISSS 2004: 140-145

Todd M. Austin: Designing robust microarchitectures. DAC 2004: 78

Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge: Circuit-aware architectural simulation. DAC 2004: 305-310

Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge: Microarchitectural power modeling techniques for deep sub-micron microprocessors. ISLPED 2004: 212-217

Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge: Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED 2004: 319-324

Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan: Leakage Current: Moore's Law Meets Static Power. IEEE Computer 36(12): 68-75 (2003)

Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin: Measuring Architectural Vulnerability Factors. IEEE Micro 23(6): 70-75 (2003)

Rajeev Krishna, Scott A. Mahlke, Todd M. Austin: Architectural optimizations for low-power, real-time speech recognition. CASES 2003: 220-231

Dan Ernst, Andrew Hamel, Todd M. Austin: Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay. ISCA 2003: 253-262

Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18

Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin: A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. MICRO 2003: 29-42

Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson: Performance Simulation Tools. IEEE Computer 35(2): 38-39 (2002)

Todd M. Austin, Eric Larson, Dan Ernst: SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Computer 35(2): 59-67 (2002)

Dan Ernst, Todd M. Austin: Efficient Dynamic Scheduling Through Tag Elimination. ISCA 2002: 37-46

Glenn Reinman, Brad Calder, Todd M. Austin: High Performance and Energy Efficient Serial Prefetch Architecture. ISHPC 2002: 146-159

Todd M. Austin: Design for Verification? IEEE Design & Test of Computers 18(4): 80, 77 (2001)

Glenn Reinman, Brad Calder, Todd M. Austin: Optimizations Enabled by a Decoupled Front-End Architecture. IEEE Trans. Computers 50(4): 338-355 (2001)

Christopher T. Weaver, Rajeev Krishna, Lisa Wu, Todd M. Austin: Application specific architectures: a recipe for fast, flexible and power efficient designs. CASES 2001: 181-185

Maher N. Mneimneh, Fadi A. Aloul, Christopher T. Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin: Scalable Hybrid Verification of Complex Microprocessors. DAC 2001: 41-46

Christopher T. Weaver, Todd M. Austin: A Fault Tolerant Approach to Microprocessor Design. DSN 2001: 411-420

Lisa Wu, Christopher T. Weaver, Todd M. Austin: CryptoManiac: a fast flexible architecture for secure communication. ISCA 2001: 110-119

Todd M. Austin: DIVA: A Dynamic Approach to Microprocessor Verification. J. Instruction-Level Parallelism 2 (2000)

Jerome Burke, John McDonald, Todd M. Austin: Architectural Support for Fast Symmetric-Key Cryptography. ASPLOS 2000: 178-189

Saugata Chatterjee, Christopher T. Weaver, Todd M. Austin: Efficient checker processor design. MICRO 2000: 87-97

Eric Larson, Todd M. Austin: Compiler controlled value prediction using branch predictor based confidence. MICRO 2000: 327-336

Gary S. Tyson, Todd M. Austin: Memory Renaming: Fast, Early and Accurate Processing of Memory Communication. International Journal of Parallel Programming 27(5): 357-380 (1999)

Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin: Classifying load and store instructions for memory renaming. International Conference on Supercomputing 1999: 399-407

Glenn Reinman, Todd M. Austin, Brad Calder: A Scalable Front-End Architecture for Fast Instruction Delivery. ISCA 1999: 234-245

Glenn Reinman, Brad Calder, Todd M. Austin: Fetch Directed Instruction Prefetching. MICRO 1999: 16-27

Todd M. Austin: DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. MICRO 1999: 196-207

Artur Klauser, Todd M. Austin, Dirk Grunwald, Brad Calder: Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures. IEEE PACT 1998: 278-285

Brad Calder, Chandra Krintz, Simmi John, Todd M. Austin: Cache-Conscious Data Placement. ASPLOS 1998: 139-149

Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin: On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO 1997: 46-56

Gary S. Tyson, Todd M. Austin: Improving the Accuracy and Performance of Memory Communication Through Renaming. MICRO 1997: 218-227

Todd M. Austin, Gurindar S. Sohi: High-Bandwidth Address Translation for Multiple-Issue Processors. ISCA 1996: 158-167

Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi: Streamlining Data Cache Access with Fast Address Calculation. ISCA 1995: 369-380

Todd M. Austin, Gurindar S. Sohi: Zero-cycle loads: microarchitecture support for reducing load latency. MICRO 1995: 82-92

Todd M. Austin, Scott E. Breach, Gurindar S. Sohi: Efficient Detection of All Pointer and Array Access Errors. PLDI 1994: 290-301

Todd M. Austin, Gurindar S. Sohi: Dynamic Dependency Analysis of Ordinary Programs. ISCA 1992: 342-351