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Peter M. Athanas
Peter Athanas
2010 – today
- 2013
[j18]René Cumplido, Peter Athanas, Jürgen Becker: Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). Int. J. Reconfig. Comp. 2013 (2013)- [c67]Kavya Shagrithaya, Krzysztof Kepa, Peter Athanas: Enabling development of OpenCL applications on FPGA platforms. ASAP 2013: 26-30
- [c66]David Uliana, Krzysztof Kepa, Peter Athanas: FPGA-based HPC application design for non-experts. ASAP 2013: 261-264
- [c65]Andrew Love, Peter Athanas: FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only). FPGA 2013: 269
- [c64]David Uliana, Krzysztof Kepa, Peter Athanas: FPGA-based HPC application design for non-experts (abstract only). FPGA 2013: 274
- 2012
- [j17]Jorge Alberto Surís, Adolfo Recio, Peter Athanas: RapidRadio: Signal Classification and Radio Deployment Framework. ACM Trans. Embedded Comput. Syst. 11(S2): 41 (2012)
- [c63]Tannous Frangieh, Richard Stroop, Peter Athanas, Teresa Cervero: A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems. ARC 2012: 314-319
- [c62]Tannous Frangieh, Peter Athanas: A design assembly framework for FPGA back-end acceleration. ReConFig 2012: 1-6
- [e5]Oliver C. S. Choy, Ray C. C. Cheung, Peter M. Athanas, Kentaro Sano (Eds.): Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings. Lecture Notes in Computer Science 7199, Springer 2012, ISBN 978-3-642-28364-2
- 2011
- [j16]Jorge Alberto Surís, Adolfo Recio, Peter M. Athanas: On the Implementation of a Quasi-Generic Synchronization Architecture for Linear Digital Modulations. Signal Processing Systems 64(3): 469-481 (2011)
- [c61]Neil Steiner, Aaron Wood, Hamid Shojaei, Jacob Couch, Peter Athanas, Matthew French: Torc: towards an open-source tool flow. FPGA 2011: 41-44
- [c60]Abhay Tavaragiri, Jacob Couch, Peter Athanas: Exploration of FPGA interconnect for the design of unconventional antennas. FPGA 2011: 219-226
- [c59]Krzysztof Kepa, Fearghal Morgan, Peter Athanas: ERDB: An Embedded Routing Database for Reconfigurable Systems. FPL 2011: 195-200
- [c58]Ali Asgar Sohanghpurwala, Peter Athanas, Tannous Frangieh, Aaron Wood: OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs. IPDPS Workshops 2011: 228-235
- [c57]
- [c56]Teresa Cervero, Sebastián López, Roberto Sarmiento, Tannous Frangieh, Peter Athanas: Scalable Models for Autonomous Self-Assembled Reconfigurable Systems. ReConFig 2011: 410-415
- [c55]Karl Pereira, Peter Athanas, Heshan Lin, Wu Feng: Spectral Method Characterization on FPGA and GPU Accelerators. ReConFig 2011: 487-492
- [e4]Peter M. Athanas, Jürgen Becker, René Cumplido (Eds.): 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1734-5
- 2010
- [j15]Matthew Shelburne, Cameron D. Patterson, Peter Athanas, Mark Jones, Brian S. Martin, Ryan Fong: MetaWire: Using FPGA configuration circuitry to emulate a network-on-chip. IET Computers & Digital Techniques 4(3): 159-169 (2010)
- [j14]Jorge Alberto Surís, Adolfo Recio, Peter M. Athanas: RapidRadio: A Domain-Specific Productivity Enhancing Framework. Int. J. Reconfig. Comp. 2010 (2010)
- [j13]Roger Woods, Jürgen Becker, Peter Athanas, Fearghal Morgan: Guest Editorial ARC 2009. TRETS 4(1): 1 (2010)
- [c54]Adolfo Recio, Peter M. Athanas: Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA. DSD 2010: 321-327
- [c53]Adolfo Recio, Jorge Alberto Surís, Peter Athanas: Automatic modulation classification for rapid radio deployment. International Symposium on Rapid System Prototyping 2010: 1-7
- [e3]Jinian Bian, Qiang Zhou, Peter Athanas, Yajun Ha, Kang Zhao (Eds.): Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China. IEEE 2010, ISBN 978-1-4244-8981-7
2000 – 2009
- 2009
- [j12]Cameron D. Patterson, Peter Athanas, Matthew Shelburne, J. Bowen, Jorge Surís, T. Dunham, J. Rice: Slotless module-based reconfiguration of embedded FPGAs. ACM Trans. Embedded Comput. Syst. 9(1) (2009)
- [c52]Nicholas J. Macias, Peter M. Athanas: Architecturally-Enforced InfoSec in a General-Purpose Self-Configurable System. BLISS 2009: 71-76
- [c51]
- [c50]
- [c49]Jorge Surís, Adolfo Recio, Peter Athanas: Enhancing the Productivity of Radio Designers with RapidRadio. ReConFig 2009: 350-355
- [e2]Jürgen Becker, Roger Woods, Peter M. Athanas, Fearghal Morgan (Eds.): Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings. Lecture Notes in Computer Science 5453, Springer 2009, ISBN 978-3-642-00640-1
- 2008
- [j11]Stephen D. Craven, Peter M. Athanas: Dynamic Hardware Development. Int. J. Reconfig. Comp. 2008 (2008)
- [c48]Brent E. Nelson, Michael J. Wirthlin, Brad L. Hutchings, Peter M. Athanas, Shawn Bohner: Design Productivity for Configurable Computing. ERSA 2008: 57-66
- [c47]Jorge Surís, Cameron D. Patterson, Peter Athanas: An efficient run-time router for connecting modules in FPGAS. FPL 2008: 125-130
- [c46]Matthew Shelburne, Cameron D. Patterson, Peter Athanas, Mark Jones, Brian S. Martin, Ryan Fong: Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip. FPL 2008: 257-262
- 2007
- [j10]Todd B. Fleming, Peter M. Athanas: Collaborative Synchronization for Signal Reinforcement in Sensor Networks. Ad Hoc & Sensor Wireless Networks 4(3): 179-198 (2007)
- [j9]Stephen D. Craven, Peter Athanas: Examining the Viability of FPGA Supercomputing. EURASIP J. Emb. Sys. 2007 (2007)
- [c45]Nicholas J. Macias, Peter M. Athanas: Application of Self-Configurability for Autonomous, Highly-Localized Self-Regulation. AHS 2007: 397-404
- [c44]Tingting Meng, Peter M. Athanas: Collaborative Signal Reinforcement in Sensor Networks. AINA 2007: 519-524
- [c43]Todd B. Fleming, Peter M. Athanas: Collaborative Synchronization for Signal Reinforcement in Sensor Networks. AINA 2007: 861-868
- [c42]
- [c41]Alex Marschner, Stephen D. Craven, Peter M. Athanas: A Sandbox for Exploring the OpenFire Processor. ERSA 2007: 248-251
- [c40]Stephen D. Craven, Peter M. Athanas: High-Level Specification of Runtime Reconfigurable Designs. ERSA 2007: 280-283
- [c39]
- [c38]Peter M. Athanas, J. Bowen, T. Dunham, Cameron D. Patterson, J. Rice, Matthew Shelburne, Jorge Surís, Mark B. Bucciero, Jonathan Graf: Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing. FPL 2007: 513-516
- 2006
- [c37]Peter M. Athanas: The (empty?) Promise of FPGA Supercomputing. Dynamically Reconfigurable Architectures 2006
- [c36]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
- [c35]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
- [c34]Stephen D. Craven, Cameron D. Patterson, Peter M. Athanas: A Methodology for Generating Application-Specific Heterogeneous Processor Arrays. HICSS 2006
- [c33]Anthony J. Mahar, Peter M. Athanas, Stephen D. Craven, Joshua N. Edmison, Jonathan Graf: Design and Characterization of a Hardware Encryption Management Unit for Secure Computing Platforms. HICSS 2006
- [c32]Jorge Alberto Surís, Peter M. Athanas: Exploring Non-Traditional Hardware-Software Interaction. ReConFig 2006: 78-85
- [e1]Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich (Eds.): Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006. Dagstuhl Seminar Proceedings 06141, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006
- 2005
- [j8]Jing Ma, Peter M. Athanas, Xin-Ming Huang: Incremental Design Methodology for Multimillion-gate Fpgas. Journal of Circuits, Systems, and Computers 14(5): 1015-1026 (2005)
- [c31]
- [c30]Deepak Argarwal, Christopher Robert Anderson, Peter M. Athanas: An 8-GHz Ultra Wideband Transceiver Prototyping Testbed. IEEE International Workshop on Rapid System Prototyping 2005: 121-127
- 2004
- [c29]Jesse Hunter, Peter Athanas, Cameron D. Patterson: VTSim: A Virtex-II Device Simulator. ERSA 2004: 297-298
- [c28]
- [c27]Jonathan Graf, Peter M. Athanas: A Key Management Architecture for Securing Off-Chip Data Transfers. FPL 2004: 33-42
- [c26]Alexandra Poetter, Jesse Hunter, Cameron D. Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner: JHDLBits: The Merging of Two Worlds. FPL 2004: 414-423
- [c25]
- 2003
- [j7]Toomas P. Plaks, Peter M. Athanas: Engineering of Configurable Systems: Guest Editors Foreword. The Journal of Supercomputing 26(2): 107-108 (2003)
- [j6]Toomas P. Plaks, Peter M. Athanas: Engineering of Configurable Systems, II Guest Editor's Foreword. The Journal of Supercomputing 26(3): 219-220 (2003)
- [j5]Kiran Puttegowda, David I. Lehn, Jae H. Park, Peter M. Athanas, Mark T. Jones: Context Switching in a Run-Time Reconfigurable System. The Journal of Supercomputing 26(3): 239-257 (2003)
- [c24]Jing Ma, Peter Athanas: A JBits-Based Incremental Design Environment with Non-Preemptive Refinement for Multi-Million Gate FPGAs. Engineering of Reconfigurable Systems and Algorithms 2003: 118-126
- [c23]Kiran Puttegowda, Peter Athanas: RSA encryption using Extended Modular Arithmetic on the Quicksilver COSM Adaptive Computing Machine. FCCM 2003: 305-307
- [c22]Ryan J. Fong, Scott J. Harper, Peter M. Athanas: A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguation. IEEE International Workshop on Rapid System Prototyping 2003: 117-123
- [c21]Kiran Puttegowda, William Worek, Nicholas Pappas, Anusha Dandapani, Peter Athanas, Allan Dickerman: A Run-Time Reconfigurable System for Gene-Sequence Searching. VLSI Design 2003: 561-566
- 2002
- [c20]Peter M. Athanas: Physical Support for Evolution in Reconfigurable Devices. Evolvable Hardware 2002: 7
- [c19]Jonathan E. Scalera, Creed F. Jones III, Maneesh Soni, Mark B. Bucciero, Peter M. Athanas, A. Lynn Abbott, Amitabh Mishra: Reconfigurable Object Detection in FLIR Image Sequences. FCCM 2002: 284-285
- 2000
- [j4]Fadi J. Kurdahi, Nader Bagherzadeh, Peter Athanas, Jose L. Muñoz: Guest Editors' Introduction: Configurable Computing. IEEE Design & Test of Computers 17(1): 17-19 (2000)
- [c18]Euripides Sotiriades, Apostolos Dollas, Peter Athanas: Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine. FCCM 2000: 227-235
1990 – 1999
- 1999
- [c17]Jason R. Hess, David C. Lee, Scott J. Harper, Mark T. Jones, Peter M. Athanas: Implementation and Evaluation of a Prototype Reconfigurable Router. FCCM 1999: 44-
- [c16]Mark Jones, Luke Scharf, Jonathan Scott, Chris Twaddle, Matthew Yaconis, Kuan Yao, Peter Athanas, Brian Schott: Implementing an API for Distributed Adaptive Computing Systems. FCCM 1999: 222-
- [c15]Steven Swanchara, Peter M. Athanas: A Methodical Approach for Stream-Oriented Configurable Signal Processing. HICSS 1999
- [c14]David C. Lee, Mark T. Jones, Scott F. Midkiff, Peter M. Athanas: Towards Active Hardware. IWAN 1999: 180-187
- 1998
- [c13]Steven Swanchara, Scott J. Harper, Peter M. Athanas: A Stream-Based Configurable Computing Radio Testbed. FCCM 1998: 40-47
- [c12]Rhett D. Hudson, David I. Lehn, Peter M. Athanas: A Run-Time Reconfigurable Engine for Image Interpolation. FCCM 1998: 88-95
- [c11]Al Walters, Peter Athanas: A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine. FCCM 1998: 333-334
- [c10]Bharadwaj Pudipeddi, A. Lynn Abbott, Peter M. Athanas: A Configurable Computing Approach Towards Real-Time Target Tracking. IPPS/SPDP Workshops 1998: 79-84
- 1997
- [c9]Ray Bittner, Peter M. Athanas: Computing kernels implemented with a wormhole RTR CCM. FCCM 1997: 98-105
- [c8]
- [c7]Brian Kahne, Peter M. Athanas: Stream synthesis for a wormhole run-time reconfigurable platform. FPL 1997: 101-110
- 1996
- [j3]James B. Peterson, Peter M. Athanas: High-speed 2-D convolution with a custom computing machine. VLSI Signal Processing 12(1): 7-19 (1996)
- 1995
- [j2]Peter M. Athanas, A. Lynn Abbott: Real-Time Image Processing on a Custom Computing Platform. IEEE Computer 28(2): 16-24 (1995)
- [c6]Nabeel Shirazi, Al Walters, Peter M. Athanas: Quantitative analysis of floating point arithmetic on FPGA based custom computing machines. FCCM 1995: 155-163
- [c5]Ramana V. Rachakonda, Peter M. Athanas, A. Lynn Abbott: High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform. FPL 1995: 86-93
- [c4]Nabeel Shirazi, Peter M. Athanas, A. Lynn Abbott: Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine. FPL 1995: 282-292
- 1994
- [c3]Peter M. Athanas, A. Lynn Abbott: Image Processing on a Custom Computing Platform. FPL 1994: 156-167
- 1993
- [j1]Peter M. Athanas, Harvey F. Silverman: Processor Reconfiguration Through Instruction-Set Metamorphosis. IEEE Computer 26(3): 11-18 (1993)
- 1991
- [c2]Peter M. Athanas, Harvey F. Silverman: An Adaptive Hardware Machine Architecture and Compiler for Dynamic Processor Reconfiguration. ICCD 1991: 397-400
- [c1]Peter M. Athanas, Harvey F. Silverman: Amstrong II: A Loosely Coupled Multiprocessor with a Reconfigurable Communications Architecture. IPPS 1991: 385-388
Coauthor Index
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last updated on 2013-10-02 11:10 CEST by the dblp team