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Kunihiro Asada
2010 – today
- 2013
[j35]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments. IEICE Transactions 96-C(4): 518-527 (2013)- [j34]Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. IEICE Transactions 96-C(4): 560-567 (2013)
- [c65]Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada: High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC 2013: 255-260
- [c64]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD 2013: 69-76
- 2012
- [j33]Toru Nakura, Kunihiro Asada: Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. IEICE Transactions 95-C(2): 297-302 (2012)
- [j32]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling. IEICE Transactions 95-C(4): 546-554 (2012)
- [j31]Tetsuya Iizuka, Kunihiro Asada: All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. IEICE Transactions 95-C(4): 627-634 (2012)
- [j30]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Transactions 95-C(4): 643-650 (2012)
- [j29]Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada: A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. IEICE Transactions 95-C(4): 661-667 (2012)
- [j28]Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada: Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Transactions 95-C(12): 1857-1863 (2012)
- [j27]Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada: All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction. IEICE Transactions 95-A(12): 2234-2241 (2012)
- [c63]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes. ASYNC 2012: 150-157
- [c62]Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira: A New Procedure for Measuring High-Accuracy Probability Density Functions. Asian Test Symposium 2012: 185-190
- [c61]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada: Impact of All-Digital PLL on SoC Testing. Asian Test Symposium 2012: 252-257
- [c60]Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada: 7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC 2012: 1-4
- [c59]James S. Tandon, Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada: A design-for-test apparatus for measuring on-chip temperature with fine granularity. ISQED 2012: 27-32
- [c58]Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada: Power integrity control of ATE for emulating power supply fluctuations on customer environment. ITC 2012: 1-10
- 2011
- [j26]Shingo Mandai, Taihei Momma, Makoto Ikeda, Kunihiro Asada: Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method. IEICE Transactions 94-C(1): 124-127 (2011)
- [j25]Salih Ergün, Ülkühan Güler, Kunihiro Asada: A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform. IEICE Transactions 94-A(1): 180-190 (2011)
- [j24]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Transactions 94-C(4): 487-494 (2011)
- [j23]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Transactions 94-C(4): 511-519 (2011)
- [j22]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada: A 0.18-µm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability. IEICE Transactions 94-C(4): 627-634 (2011)
- [j21]Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Transactions 94-C(4): 654-662 (2011)
- [j20]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada: 1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Transactions 94-C(6): 1098-1104 (2011)
- [j19]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada: A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging. IEICE Transactions 94-C(10): 1626-1633 (2011)
- [j18]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada: A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application. IEICE Transactions 94-A(12): 2554-2562 (2011)
- [j17]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. J. Solid-State Circuits 46(11): 2500-2513 (2011)
- [c57]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. ASP-DAC 2011: 75-76
- [c56]Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC 2011: 79-80
- [c55]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada: A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS. ASP-DAC 2011: 107-108
- [c54]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS 2011: 111-114
- [c53]Tetsuya Iizuka, Kunihiro Asada: An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. DDECS 2011: 115-120
- [c52]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC 2011: 183-186
- [c51]Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada: A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. ESSCIRC 2011: 399-402
- [c50]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system. ICECS 2011: 53-56
- [c49]Mohamed Abbas, Takahiro J. Yamaguchi, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada: Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology. ICECS 2011: 220-223
- [c48]Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada: All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS. ICECS 2011: 607-610
- [c47]Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada: An equivalent-time and clocked approach for continuous-time quantization. ISCAS 2011: 2529-2532
- [c46]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. ISLPED 2011: 3-8
- [c45]Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu: Application of a continuous-time level crossing quantization method for timing noise measurements. ITC 2011: 1-10
- 2010
- [j16]Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada: Time Difference Amplifier with Robust Gain Using Closed-Loop Control. IEICE Transactions 93-C(3): 303-308 (2010)
- [j15]Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada: A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Transactions 93-A(7): 1319-1328 (2010)
- [c44]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Cascaded time difference amplifier using differential logic delay cell. ASP-DAC 2010: 355-356
- [c43]Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada: An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. DATE 2010: 1755-1760
- [c42]Tetsuya Iizuka, Toru Nakura, Kunihiro Asada: Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS 2010: 167-172
- [c41]Shingo Mandai, Makoto Ikeda, Kunihiro Asada: A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary. ISSCC 2010: 404-405
2000 – 2009
- 2009
- [j14]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. IEICE Transactions 92-C(6): 798-805 (2009)
- [c40]Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada: Circuit design using stripe-shaped PMELA TFTs on glass. ASP-DAC 2009: 105-106
- [c39]Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda: Measurement of power supply noise tolerance of self-timed processor. DDECS 2009: 128-131
- [c38]Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS 2009: 206-209
- [c37]Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada: Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. European Test Symposium 2009: 107-112
- [c36]MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. ACM Great Lakes Symposium on VLSI 2009: 177-180
- 2007
- [j13]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. IEEE Trans. VLSI Syst. 15(6): 716-720 (2007)
- [c35]Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. ASP-DAC 2007: 100-101
- [c34]Zhicheng Liang, Makoto Ikeda, Kunihiro Asada: Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology. DDECS 2007: 81-86
- [c33]Yusuke Yachide, Makoto Ikeda, Kunihiro Asada: FPGA-Based 3-D engine for high-speed 3-D measurement based on light-section method. FPT 2007: 293-296
- [c32]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. ISQED 2007: 776-781
- 2006
- [j12]Toru Nakura, Makoto Ikeda, Kunihiro Asada: Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply. IEICE Transactions 89-C(3): 364-369 (2006)
- [j11]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada: On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function. IEICE Transactions 89-C(3): 370-376 (2006)
- [j10]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada: Noise Immunity Investigation of Low Power Design Schemes. IEICE Transactions 89-C(8): 1238-1247 (2006)
- [j9]Toru Nakura, Makoto Ikeda, Kunihiro Asada: Autonomous di/dt Control of Power Supply for Margin Aware Operation. IEICE Transactions 89-C(11): 1689-1694 (2006)
- [j8]Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada: A Structural Approach for Transistor Circuit Synthesis. IEICE Transactions 89-A(12): 3529-3537 (2006)
- [j7]Taisuke Kazama, Makoto Ikeda, Kunihiro Asada: LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil. IEICE Transactions 89-A(12): 3546-3550 (2006)
- [c31]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada: On-chip 8GHz non-periodic high-swing noise detector. DATE 2006: 670-671
- [c30]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Timing-driven cell layout de-compaction for yield optimization by critical area minimization. DATE 2006: 884-889
- [c29]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada: Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. DDECS 2006: 147-148
- [c28]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. ISCAS 2006
- 2005
- [j6]Toru Nakura, Makoto Ikeda, Kunihiro Asada: Stub vs. Capacitor for Power Supply Noise Reduction. IEICE Transactions 88-C(1): 125-132 (2005)
- [j5]Toru Nakura, Makoto Ikeda, Kunihiro Asada: On-chip di/dt Detector Circuit. IEICE Transactions 88-C(5): 782-787 (2005)
- [j4]Ulkuhan Ekinciel, Hiroaki Yamaoka, Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada: A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells. IEICE Transactions 88-D(6): 1159-1167 (2005)
- [j3]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Transactions 88-A(7): 1957-1963 (2005)
- [j2]Toru Nakura, Makoto Ikeda, Kunihiro Asada: Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs. IEICE Transactions 88-C(8): 1734-1739 (2005)
- [j1]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. IEICE Transactions 88-A(12): 3485-3491 (2005)
- [c27]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact minimum-width transistor placement without dual constraint for CMOS cells. ACM Great Lakes Symposium on VLSI 2005: 74-77
- [c26]Yusuke Yachide, Yusuke Oike, Makoto Ikeda, Kunihiro Asada: Real-time 3-D measurement system based on light-section method using smart image sensor. ICIP (3) 2005: 1008-1111
- 2004
- [c25]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. ASP-DAC 2004: 149-154
- [c24]Yusuke Oike, Makoto Ikeda, Kunihiro Asada: Design of real-time VGA 3-D image sensor using mixed-signal techniques. ASP-DAC 2004: 523-524
- [c23]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada: Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime. DFT 2004: 87-95
- [c22]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. ISQED 2004: 377-380
- 2003
- [c21]Yusuke Oike, Makoto Ikeda, Kunihiro Asada: High-speed position detector using new row-parallel architecture for fast collision prevention system. ISCAS (4) 2003: 788-791
- [c20]Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada: Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE 2003: 41-42
- 2002
- [c19]Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada: Logic synthesis for PLA with 2-input logic elements. ISCAS (3) 2002: 373-376
- [c18]Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada: Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. VLSI Design 2002: 166-171
- [c17]Tohru Ishihara, Kunihiro Asada: An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. VLSI Design 2002: 282-287
- 2001
- [c16]Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada: A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. ASP-DAC 2001: 3-4
- [c15]Tomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada: A smart position sensor for 3-D measurement. ASP-DAC 2001: 21-22
- [c14]Jian Qiao, Makoto Ikeda, Kunihiro Asada: Finding an optimal functional decomposition for LUT-based FPGA synthesis. ASP-DAC 2001: 225-230
- [c13]Tohru Ishihara, Kunihiro Asada: A system level memory power optimization technique using multiple supply and threshold voltages. ASP-DAC 2001: 456-461
- [c12]Yusuke Nakashima, Makoto Ikeda, Kunihiro Asada: Computational Cost Reduction in Extracting Inductance. ISQED 2001: 179-184
- 2000
- [c11]Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada: A binary image sensor with flexible motion vector detection using block matching method. ASP-DAC 2000: 21-22
- [c10]Jian Qiao, Makoto Ikeda, Kunihiro Asada: Optimum Functional Decomposition for LUT-Based FPGA Synthesis. FPL 2000: 555-564
- [c9]Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada: DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path. ISQED 2000: 305-308
1990 – 1999
- 1999
- [c8]Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada: Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. Great Lakes Symposium on VLSI 1999: 368-371
- [c7]Makoto Ikeda, Kunihiro Asada: Standard design flows of Logic LSIs in Japanese universities and VDEC. MSE 1999: 8-9
- 1998
- [c6]Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada: Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. ASP-DAC 1998: 323-324
- [c5]Tetsuhisa Mido, Kunihiro Asada: An Analysis on VLSI Interconnection Considering Skin Effect. ASP-DAC 1998: 403-408
- 1997
- [c4]Tetsuhisa Mido, Kunihiro Asada: Crosstalk noise in high density and high speed interconnections due to inductive coupling. ASP-DAC 1997: 215-220
- 1995
- [c3]Minkyu Song, Kunihiro Asada: Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54X54 Bit Multiplier. ISCAS 1995: 1568-1571
- 1994
- [c2]Makoto Ikeda, Kunihiro Asada: A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs. EDAC-ETC-EUROASIC 1994: 546-550
- 1992
- [c1]H. Zhang, Kunihiro Asada: A general and efficient mask pattern generator for non-series-parallel CMOS transistor network. Synthesis for Control Dominated Circuits 1992: 323-333
Coauthor Index
[j35] [j34] [c65] [c64] [j32] [j30] [j27] [c63] [c59] [j26] [j24] [j23] [j21] [j20] [j17] [c57] [c56] [c54] [c52] [c50] [c48] [c46] [j16] [j15] [c44] [c41] [j14] [c40] [c39] [c38] [c36] [j13] [c35] [c34] [c33] [c32] [j12] [j11] [j10] [j9] [j8] [j7] [c31] [c30] [c29] [c28] [j6] [j5] [j4] [j3] [j2] [j1] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c16] [c15] [c14] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c2]
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last updated on 2013-05-26 01:49 CEST by the dblp team