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 | 2012 | |
|---|---|---|
| j18 |      | Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois: Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Computers & Digital Techniques 6(6): 372-383 (2012) |
| 2011 | ||
| c29 | | Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini: Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs. ICECS 2011: 137-140 |
| c28 | | Jacques L. Athow, Come Rozon, Dhamin Al-Khalili, J. M. Pierre Langlois: A CNFET-based characterization framework for digital circuits. ICECS 2011: 681-684 |
| c27 | | Hisham El-Masry, Dhamin Al-Khalili: Cell stack length using an enhanced logical effort model for a library-free paradigm. ICECS 2011: 703-706 |
| c26 | | Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini: Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs. IPDPS Workshops 2011: 271-277 |
| 2010 | ||
| j17 | | Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois: FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers. Signal Processing Systems 58(1): 3-15 (2010) |
| c25 | | Ali M. Farhangi, Asim J. Al-Khalili, Dhamin Al-Khalili: Pattern-Driven Clock Tree Routing with Via Minimization. ISVLSI 2010: 216-221 |
| 2009 | ||
| j16 | | Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini: Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs. Int. J. Reconfig. Comp. 2009 (2009) |
| c24 | | Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini: Two level decomposition based matrix multiplication for FPGAs. ICECS 2009: 427-430 |
| 2008 | ||
| j15 | | Hussam Al-Hertani, Dhamin Al-Khalili, Come Rozon: UDSM subthreshold leakage model for NMOS transistor stacks. Microelectronics Journal 39(12): 1809-1816 (2008) |
| c23 | | Man Yan Kong, J. M. Pierre Langlois, Dhamin Al-Khalili: Efficient FPGA implementation of complex multipliers using the logarithmic number system. ISCAS 2008: 3154-3157 |
| 2007 | ||
| j14 | | Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois: Optimised realisations of large integer multipliers and squarers using embedded blocks. IET Computers & Digital Techniques 1(1): 9-16 (2007) |
| c22 | | Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois: FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. ASAP 2007: 18-23 |
| 2006 | ||
| j13 | | Donald B. Shaw, Dhamin Al-Khalili, Come Rozon: Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries. Integration 39(4): 382-406 (2006) |
| c21 | | Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois: An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. AICCSA 2006: 248-254 |
| c20 | | Hussam Al-Hertani, Dhamin Al-Khalili, Come Rozon: Accurate Total Static Leakage Current Estimation in Transistor Stacks. AICCSA 2006: 262-265 |
| c19 | | Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois: Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers. SoCC 2006: 21-24 |
| 2005 | ||
| j12 | | Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili: Delay analysis of CMOS gates using modified logical effort model. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 937-947 (2005) |
| j11 | | Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili: Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1637-1643 (2005) |
| c18 |  | Hussam Al-Hertani, Dhamin Al-Khalili, Come Rozon: Leakage power dissipation in UDSM logic gates. Circuits, Signals, and Systems 2005: 132-136 |
| 2004 | ||
| c17 | | Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili: Clock tree tuning using shortest paths polygon. SoCC 2004: 59-62 |
| 2003 | ||
| j10 | | Donald B. Shaw, Dhamin Al-Khalili, Come Rozon: IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs. IEEE Trans. Computers 52(10): 1285-1297 (2003) |
| j9 | | Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili: Technology-portable analytical model for DSM CMOS inverter transition-time estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1177-1187 (2003) |
| c16 | | Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili: Adaptive wire adjustment for bounded skew Clock Distribution Network. ASP-DAC 2003: 243-248 |
| 2002 | ||
| j8 | | Donald B. Shaw, Dhamin Al-Khalili, Come Rozon: Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models. Integration 32(1-2): 77-97 (2002) |
| j7 | | J. M. Pierre Langlois, Dhamin Al-Khalili, Robert J. Inkol: Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation. VLSI Signal Processing 32(3): 237-254 (2002) |
| c15 | | J. M. Pierre Langlois, Dhamin Al-Khalili: A low power direct digital frequency synthesizer with 60 dBc spectral purity. ACM Great Lakes Symposium on VLSI 2002: 166-171 |
| c14 | | J. M. Pierre Langlois, Dhamin Al-Khalili: Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity. ISCAS (5) 2002: 361-364 |
| c13 | | Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili: Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 119-125 |
| 2001 | ||
| j6 | | R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah: A Low Power Approach to Floating Point Adder Design for DSP Applications. VLSI Signal Processing 27(3): 195-213 (2001) |
| c12 | | Donald B. Shaw, Dhamin Al-Khalili, Come Rozon: Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs. ICCAD 2001: 531-536 |
| c11 | | Donald B. Shaw, Dhamin Al-Khalili, Come Rozon: Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation. ISCAS (5) 2001: 263-266 |
| 1999 | ||
| j5 | | Michael Gallant, Dhamin Al-Khalili: Synthesis of low-power CMOS circuits using hybrid topologies. Integration 27(2): 143-163 (1999) |
| c10 | | R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: An IEEE Compliant Floating Point MAF. VLSI 1999: 149-160 |
| c9 | | R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: Power implications of precision limited arithmetic in floating point FIR filters. ISCAS (1) 1999: 165-168 |
| 1998 | ||
| c8 | | Jason Coppens, Dhamin Al-Khalili, Come Rozon: VHDL Modelling and Analysis of Fault Secure Systems. DATE 1998: 148-152 |
| c7 | | Dhamin Al-Khalili, Saman Adham, Come Rozon, Moazzem Hossain, D. Racz: Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. DFT 1998: 84-92 |
| c6 | | R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili: A Low Power Floating Point Accumulator. VLSI Design 1998: 330- |
| 1997 | ||
| c5 | | R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: A Low Power Approach to Floating Point Adder Design. ICCD 1997: 178-185 |
| c4 | | R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. ISLPED 1997: 235-238 |
| 1996 | ||
| c3 | | R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: Energy delay analysis of partial product reduction methods for parallel multiplier implementation. ISLPED 1996: 201-204 |
| 1995 | ||
| j4 | | Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili: Design techniques for fault-tolerant systolic arrays. VLSI Signal Processing 11(1-2): 151-168 (1995) |
| 1994 | ||
| j3 | | T. C. Davies, Dhamin Al-Khalili, Valek Szwarc: A floating-point systolic array processing element with serial communication and built-in self-test. VLSI Signal Processing 8(3): 241-251 (1994) |
| 1993 | ||
| c2 | | Michael Ogbonna Esonu, Dhamin Al-Khalili, Come Rozon: Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits. ISCAS 1993: 1714-1717 |
| 1992 | ||
| j2 | | Dhamin Al-Khalili, Come Rozon, B. Stewart: Testability analysis and fault modeling of BiCMOS circuits. J. Electronic Testing 3(3): 207-217 (1992) |
| 1990 | ||
| j1 | | Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili: A module generator for optimized CMOS buffers. IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 1028-1046 (1990) |
| 1989 | ||
| c1 | | Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili: A Module Generator for Optimized CMOS Buffers. DAC 1989: 245-250 |
Colors in the list of coauthors
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