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BibTeX records: Matthew M. Ziegler
@inproceedings{DBLP:conf/isscc/KarSVSFRLLCZCWAZCGGHJJJJKKLMMNRRRRSSS24, author = {Monodeep Kar and Joel Silberman and Swagath Venkataramani and Viji Srinivasan and Bruce M. Fleischer and Joshua Rubin and JohnDavid Lancaster and Sae Kyu Lee and Matthew Cohen and Matthew M. Ziegler and Nianzheng Cao and Sandra Woodward and Ankur Agrawal and Ching Zhou and Prasanth Chatarasi and Thomas Gooding and Michael Guillorn and Bahman Hekmatshoartabari and Philip Jacob and Radhika Jain and Shubham Jain and Jinwook Jung and Kyu{-}Hyoun Kim and Siyu Koswatta and Martin Lutz and Alberto Mannari and Abey Mathew and Indira Nair and Ashish Ranjan and Zhibin Ren and Scot Rider and Thomas Roewer and David L. Satterfield and Marcel Schaal and Sanchari Sen and Gustavo Tellez and Hung Tran and Wei Wang and Vidhi Zalani and Jintao Zhang and Xin Zhang and Vinay Shah and Robert M. Senger and Arvind Kumar and Pong{-}Fei Lu and Leland Chang}, title = {14.1 {A} Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm {AI} SoC}, booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024, San Francisco, CA, USA, February 18-22, 2024}, pages = {254--256}, publisher = {{IEEE}}, year = {2024}, url = {https://doi.org/10.1109/ISSCC49657.2024.10454301}, doi = {10.1109/ISSCC49657.2024.10454301}, timestamp = {Tue, 19 Mar 2024 09:04:31 +0100}, biburl = {https://dblp.org/rec/conf/isscc/KarSVSFRLLCZCWAZCGGHJJJJKKLMMNRRRRSSS24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/LeeASZKVCFGCMOL22, author = {Sae Kyu Lee and Ankur Agrawal and Joel Silberman and Matthew M. Ziegler and Mingu Kang and Swagath Venkataramani and Nianzheng Cao and Bruce M. Fleischer and Michael Guillorn and Matthew Cohen and Silvia M. Mueller and Jinwook Oh and Martin Lutz and Jinwook Jung and Siyu Koswatta and Ching Zhou and Vidhi Zalani and Monodeep Kar and James Bonanno and Robert Casatuta and Chia{-}Yu Chen and Jungwook Choi and Howard Haynie and Alyssa Herbert and Radhika Jain and Kyu{-}Hyoun Kim and Yulong Li and Zhibin Ren and Scot Rider and Marcel Schaal and Kerstin Schelm and Michael Scheuermann and Xiao Sun and Hung Tran and Naigang Wang and Wei Wang and Xin Zhang and Vinay Shah and Brian W. Curran and Vijayalakshmi Srinivasan and Pong{-}Fei Lu and Sunil Shukla and Kailash Gopalakrishnan and Leland Chang}, title = {A 7-nm Four-Core Mixed-Precision {AI} Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS {INT4} Inference, and Workload-Aware Throttling}, journal = {{IEEE} J. Solid State Circuits}, volume = {57}, number = {1}, pages = {182--197}, year = {2022}, url = {https://doi.org/10.1109/JSSC.2021.3120113}, doi = {10.1109/JSSC.2021.3120113}, timestamp = {Sat, 19 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/LeeASZKVCFGCMOL22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/ZieglerRF22, author = {Matthew M. Ziegler and Lakshmi N. Reddy and Robert L. Franch}, editor = {Laleh Behjat and Stephen Yang}, title = {Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning}, booktitle = {{ISPD} 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27 - 30, 2022}, pages = {29--37}, publisher = {{ACM}}, year = {2022}, url = {https://doi.org/10.1145/3505170.3506727}, doi = {10.1145/3505170.3506727}, timestamp = {Thu, 14 Apr 2022 14:53:52 +0200}, biburl = {https://dblp.org/rec/conf/ispd/ZieglerRF22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ZieglerKLC21, author = {Matthew M. Ziegler and Jihye Kwon and Hung{-}Yi Liu and Luca P. Carloni}, title = {Online and Offline Machine Learning for Industrial Design Flow Tuning: (Invited - {ICCAD} Special Session Paper)}, booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD} 2021, Munich, Germany, November 1-4, 2021}, pages = {1--9}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/ICCAD51958.2021.9643577}, doi = {10.1109/ICCAD51958.2021.9643577}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/ZieglerKLC21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/VenkataramaniSW21, author = {Swagath Venkataramani and Vijayalakshmi Srinivasan and Wei Wang and Sanchari Sen and Jintao Zhang and Ankur Agrawal and Monodeep Kar and Shubham Jain and Alberto Mannari and Hoang Tran and Yulong Li and Eri Ogawa and Kazuaki Ishizaki and Hiroshi Inoue and Marcel Schaal and Mauricio J. Serrano and Jungwook Choi and Xiao Sun and Naigang Wang and Chia{-}Yu Chen and Allison Allain and James Bonanno and Nianzheng Cao and Robert Casatuta and Matthew Cohen and Bruce M. Fleischer and Michael Guillorn and Howard Haynie and Jinwook Jung and Mingu Kang and Kyu{-}Hyoun Kim and Siyu Koswatta and Sae Kyu Lee and Martin Lutz and Silvia M. Mueller and Jinwook Oh and Ashish Ranjan and Zhibin Ren and Scot Rider and Kerstin Schelm and Michael Scheuermann and Joel Silberman and Jie Yang and Vidhi Zalani and Xin Zhang and Ching Zhou and Matthew M. Ziegler and Vinay Shah and Moriyoshi Ohara and Pong{-}Fei Lu and Brian W. Curran and Sunil Shukla and Leland Chang and Kailash Gopalakrishnan}, title = {RaPiD: {AI} Accelerator for Ultra-low Precision Training and Inference}, booktitle = {48th {ACM/IEEE} Annual International Symposium on Computer Architecture, {ISCA} 2021, Virtual Event / Valencia, Spain, June 14-18, 2021}, pages = {153--166}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/ISCA52012.2021.00021}, doi = {10.1109/ISCA52012.2021.00021}, timestamp = {Mon, 19 Feb 2024 07:32:07 +0100}, biburl = {https://dblp.org/rec/conf/isca/VenkataramaniSW21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/AgrawalLSZKVCFG21, author = {Ankur Agrawal and Sae Kyu Lee and Joel Silberman and Matthew M. Ziegler and Mingu Kang and Swagath Venkataramani and Nianzheng Cao and Bruce M. Fleischer and Michael Guillorn and Matt Cohen and Silvia M. Mueller and Jinwook Oh and Martin Lutz and Jinwook Jung and Siyu Koswatta and Ching Zhou and Vidhi Zalani and James Bonanno and Robert Casatuta and Chia{-}Yu Chen and Jungwook Choi and Howard Haynie and Alyssa Herbert and Radhika Jain and Monodeep Kar and Kyu{-}Hyoun Kim and Yulong Li and Zhibin Ren and Scot Rider and Marcel Schaal and Kerstin Schelm and Michael Scheuermann and Xiao Sun and Hung Tran and Naigang Wang and Wei Wang and Xin Zhang and Vinay Shah and Brian W. Curran and Vijayalakshmi Srinivasan and Pong{-}Fei Lu and Sunil Shukla and Leland Chang and Kailash Gopalakrishnan}, title = {A 7nm 4-Core {AI} Chip with 25.6TFLOPS Hybrid {FP8} Training, 102.4TOPS {INT4} Inference and Workload-Aware Throttling}, booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021, San Francisco, CA, USA, February 13-22, 2021}, pages = {144--146}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/ISSCC42613.2021.9365791}, doi = {10.1109/ISSCC42613.2021.9365791}, timestamp = {Sat, 19 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isscc/AgrawalLSZKVCFG21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/pieee/VenkataramaniSW20, author = {Swagath Venkataramani and Xiao Sun and Naigang Wang and Chia{-}Yu Chen and Jungwook Choi and Mingu Kang and Ankur Agarwal and Jinwook Oh and Shubham Jain and Tina Babinsky and Nianzheng Cao and Thomas W. Fox and Bruce M. Fleischer and George Gristede and Michael Guillorn and Howard Haynie and Hiroshi Inoue and Kazuaki Ishizaki and Michael J. Klaiber and Shih{-}Hsien Lo and Gary W. Maier and Silvia M. Mueller and Michael Scheuermann and Eri Ogawa and Marcel Schaal and Mauricio J. Serrano and Joel Silberman and Christos Vezyrtzis and Wei Wang and Fanchieh Yee and Jintao Zhang and Matthew M. Ziegler and Ching Zhou and Moriyoshi Ohara and Pong{-}Fei Lu and Brian W. Curran and Sunil Shukla and Vijayalakshmi Srinivasan and Leland Chang and Kailash Gopalakrishnan}, title = {Efficient {AI} System Design With Cross-Layer Approximate Computing}, journal = {Proc. {IEEE}}, volume = {108}, number = {12}, pages = {2232--2250}, year = {2020}, url = {https://doi.org/10.1109/JPROC.2020.3029453}, doi = {10.1109/JPROC.2020.3029453}, timestamp = {Sat, 19 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/pieee/VenkataramaniSW20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsic/OhLKZSAVFGCWMBB20, author = {Jinwook Oh and Sae Kyu Lee and Mingu Kang and Matthew M. Ziegler and Joel Silberman and Ankur Agrawal and Swagath Venkataramani and Bruce M. Fleischer and Michael Guillorn and Jungwook Choi and Wei Wang and Silvia M. Mueller and Shimon Ben{-}Yehuda and James Bonanno and Nianzheng Cao and Robert Casatuta and Chia{-}Yu Chen and Matt Cohen and Ophir Erez and Thomas W. Fox and George Gristede and Howard Haynie and Vicktoria Ivanov and Siyu Koswatta and Shih{-}Hsien Lo and Martin Lutz and Gary W. Maier and Alex Mesh and Yevgeny Nustov and Scot Rider and Marcel Schaal and Michael Scheuermann and Xiao Sun and Naigang Wang and Fanchieh Yee and Ching Zhou and Vinay Shah and Brian W. Curran and Vijayalakshmi Srinivasan and Pong{-}Fei Lu and Sunil Shukla and Kailash Gopalakrishnan and Leland Chang}, title = {A 3.0 {TFLOPS} 0.62V Scalable Processor Core for High Compute Utilization {AI} Training and Inference}, booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu, HI, USA, June 16-19, 2020}, pages = {1--2}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162917}, doi = {10.1109/VLSICIRCUITS18222.2020.9162917}, timestamp = {Sat, 19 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/vlsic/OhLKZSAVFGCWMBB20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/dt/BurgZM19, author = {Andreas Burg and Matthew M. Ziegler and Saibal Mukhopdhyay}, title = {Conference Report from the 2019 International Symposium on Low Power Electronics and Design {(ISLPED)}}, journal = {{IEEE} Des. Test}, volume = {36}, number = {6}, pages = {82--83}, year = {2019}, url = {https://doi.org/10.1109/MDAT.2019.2941713}, doi = {10.1109/MDAT.2019.2941713}, timestamp = {Fri, 13 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/dt/BurgZM19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/esticas/ZieglerKZJ19, author = {Matthew M. Ziegler and Krishnan Kailas and Xin Zhang and Rajiv V. Joshi}, title = {Research From the {IEEE} {IBM} {AI} Compute and Emerging Technology Symposia}, journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.}, volume = {9}, number = {3}, pages = {435--438}, year = {2019}, url = {https://doi.org/10.1109/JETCAS.2019.2938901}, doi = {10.1109/JETCAS.2019.2938901}, timestamp = {Thu, 21 Nov 2019 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/esticas/ZieglerKZJ19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/KwonZC19, author = {Jihye Kwon and Matthew M. Ziegler and Luca P. Carloni}, title = {A Learning-Based Recommender System for Autotuning Design Flows of Industrial High-Performance Processors}, booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019, {DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019}, pages = {218}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3316781.3323919}, doi = {10.1145/3316781.3323919}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/KwonZC19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/ChandramoorthyS19, author = {Nandhini Chandramoorthy and Karthik Swaminathan and Martin Cochet and Arun Paidimarri and Schuyler Eldridge and Rajiv V. Joshi and Matthew M. Ziegler and Alper Buyuktosunoglu and Pradip Bose}, title = {Resilient Low Voltage Accelerators for High Energy Efficiency}, booktitle = {25th {IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2019, Washington, DC, USA, February 16-20, 2019}, pages = {147--158}, publisher = {{IEEE}}, year = {2019}, url = {https://doi.org/10.1109/HPCA.2019.00034}, doi = {10.1109/HPCA.2019.00034}, timestamp = {Wed, 16 Oct 2019 14:14:50 +0200}, biburl = {https://dblp.org/rec/conf/hpca/ChandramoorthyS19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/mixdes/JoshiZ19, author = {Rajiv V. Joshi and Matthew M. Ziegler}, editor = {Andrzej Napieralksi}, title = {Low Power Design From Moore to {AI} for nm Era : Invited Paper}, booktitle = {26th International Conference on Mixed Design of Integrated Circuits and Systems, {MIXDES} 2019, Rzesz{\'{o}}w, Poland, June 27-29, 2019}, pages = {59--64}, publisher = {{IEEE}}, year = {2019}, url = {https://doi.org/10.23919/MIXDES.2019.8787172}, doi = {10.23919/MIXDES.2019.8787172}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/mixdes/JoshiZ19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cicc/JoshiZSC18, author = {Rajiv V. Joshi and Matthew M. Ziegler and Karthik Swaminathan and Nandhini Chandramoorthy}, title = {Cascaded and resonant {SRAM} supply boosting for ultra-low voltage cognitive IoT applications}, booktitle = {2018 {IEEE} Custom Integrated Circuits Conference, {CICC} 2018, San Diego, CA, USA, April 8-11, 2018}, pages = {1--4}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/CICC.2018.8357067}, doi = {10.1109/CICC.2018.8357067}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/cicc/JoshiZSC18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/islped/SrinivasanFSZSO18, author = {Vijayalakshmi Srinivasan and Bruce M. Fleischer and Sunil Shukla and Matthew M. Ziegler and Joel Silberman and Jinwook Oh and Jungwook Choi and Silvia M. Mueller and Ankur Agrawal and Tina Babinsky and Nianzheng Cao and Chia{-}Yu Chen and Pierce Chuang and Thomas W. Fox and George Gristede and Michael Guillorn and Howard Haynie and Michael J. Klaiber and Dongsoo Lee and Shih{-}Hsien Lo and Gary W. Maier and Michael Scheuermann and Swagath Venkataramani and Christos Vezyrtzis and Naigang Wang and Fanchieh Yee and Ching Zhou and Pong{-}Fei Lu and Brian W. Curran and Leland Chang and Kailash Gopalakrishnan}, title = {Across the Stack Opportunities for Deep Learning Acceleration}, booktitle = {Proceedings of the International Symposium on Low Power Electronics and Design, {ISLPED} 2018, Seattle, WA, USA, July 23-25, 2018}, pages = {35:1--35:2}, publisher = {{ACM}}, year = {2018}, url = {https://doi.org/10.1145/3218603.3241339}, doi = {10.1145/3218603.3241339}, timestamp = {Tue, 22 Feb 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/islped/SrinivasanFSZSO18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsic/FleischerSZSOSC18, author = {Bruce M. Fleischer and Sunil Shukla and Matthew M. Ziegler and Joel Silberman and Jinwook Oh and Vijayalakshmi Srinivasan and Jungwook Choi and Silvia M. Mueller and Ankur Agrawal and Tina Babinsky and Nianzheng Cao and Chia{-}Yu Chen and Pierce Chuang and Thomas W. Fox and George Gristede and Michael Guillorn and Howard Haynie and Michael J. Klaiber and Dongsoo Lee and Shih{-}Hsien Lo and Gary W. Maier and Michael Scheuermann and Swagath Venkataramani and Christos Vezyrtzis and Naigang Wang and Fanchieh Yee and Ching Zhou and Pong{-}Fei Lu and Brian W. Curran and Leland Chang and Kailash Gopalakrishnan}, title = {A Scalable Multi- TeraOPS Deep Learning Processor Core for {AI} Trainina and Inference}, booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June 18-22, 2018}, pages = {35--36}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/VLSIC.2018.8502276}, doi = {10.1109/VLSIC.2018.8502276}, timestamp = {Tue, 22 Feb 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsic/FleischerSZSOSC18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ibmrd/ZieglerMBB17, author = {Matthew M. Ziegler and Ramon Bertran Monfort and Alper Buyuktosunoglu and Pradip Bose}, title = {Machine learning techniques for taming the complexity of modern hardware design}, journal = {{IBM} J. Res. Dev.}, volume = {61}, number = {4-5}, pages = {13:1--13:14}, year = {2017}, url = {https://doi.org/10.1147/JRD.2017.2721699}, doi = {10.1147/JRD.2017.2721699}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ibmrd/ZieglerMBB17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/JoshiZW17, author = {Rajiv V. Joshi and Matthew M. Ziegler and Holger Wetter}, title = {A Low Voltage {SRAM} Using Resonant Supply Boosting}, journal = {{IEEE} J. Solid State Circuits}, volume = {52}, number = {3}, pages = {634--644}, year = {2017}, url = {https://doi.org/10.1109/JSSC.2016.2628772}, doi = {10.1109/JSSC.2016.2628772}, timestamp = {Sun, 30 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/JoshiZW17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cicc/JoshiZ17, author = {Rajiv V. Joshi and Matthew M. Ziegler}, title = {Programmable supply boosting techniques for near threshold and wide operating voltage {SRAM}}, booktitle = {2017 {IEEE} Custom Integrated Circuits Conference, {CICC} 2017, Austin, TX, USA, April 30 - May 3, 2017}, pages = {1--4}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/CICC.2017.7993686}, doi = {10.1109/CICC.2017.7993686}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/cicc/JoshiZ17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/BertranBBBBCCCE17, author = {Ramon Bertran and Pradip Bose and David M. Brooks and Jeff Burns and Alper Buyuktosunoglu and Nandhini Chandramoorthy and Eric Cheng and Martin Cochet and Schuyler Eldridge and Daniel Friedman and Hans M. Jacobson and Rajiv V. Joshi and Subhasish Mitra and Robert K. Montoye and Arun Paidimarri and Pritish Parida and Kevin Skadron and Mircea Stan and Karthik Swaminathan and Augusto Vega and Swagath Venkataramani and Christos Vezyrtzis and Gu{-}Yeon Wei and John{-}David Wellman and Matthew M. Ziegler}, title = {Very Low Voltage {(VLV)} Design}, booktitle = {2017 {IEEE} International Conference on Computer Design, {ICCD} 2017, Boston, MA, USA, November 5-8, 2017}, pages = {601--604}, publisher = {{IEEE} Computer Society}, year = {2017}, url = {https://doi.org/10.1109/ICCD.2017.105}, doi = {10.1109/ICCD.2017.105}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/BertranBBBBCCCE17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ZieglerLGONC16a, author = {Matthew M. Ziegler and Hung{-}Yi Liu and George Gristede and Bruce Owens and Ricardo Nigaglioni and Luca P. Carloni}, editor = {Cristina Silvano and Walter Stechele and Stephan Wong and Jer{\'{o}}nimo Castrill{\'{o}}n and Michael H{\"{u}}bner and Amir Hossein Ashouri}, title = {A Scalable Black-Box Optimization System for Auto-Tuning {VLSI} Synthesis Programs}, booktitle = {Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, Automation And Test In Europe {(DATE} 2016), Dresden, Germany, March 18th, 2016}, series = {{CEUR} Workshop Proceedings}, volume = {1643}, pages = {8--12}, publisher = {CEUR-WS.org}, year = {2016}, url = {https://ceur-ws.org/Vol-1643/paper-02.pdf}, timestamp = {Fri, 10 Mar 2023 16:22:47 +0100}, biburl = {https://dblp.org/rec/conf/date/ZieglerLGONC16a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ZieglerLGONC16, author = {Matthew M. Ziegler and Hung{-}Yi Liu and George Gristede and Bruce Owens and Ricardo Nigaglioni and Luca P. Carloni}, editor = {Luca Fanucci and J{\"{u}}rgen Teich}, title = {A synthesis-parameter tuning system for autonomous design-space exploration}, booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016}, pages = {1148--1151}, publisher = {{IEEE}}, year = {2016}, url = {https://ieeexplore.ieee.org/document/7459483/}, timestamp = {Mon, 09 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/date/ZieglerLGONC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/islped/ZieglerLC16, author = {Matthew M. Ziegler and Hung{-}Yi Liu and Luca P. Carloni}, title = {Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors}, booktitle = {Proceedings of the 2016 International Symposium on Low Power Electronics and Design, {ISLPED} 2016, San Francisco Airport, CA, USA, August 08 - 10, 2016}, pages = {180--185}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2934583.2934620}, doi = {10.1145/2934583.2934620}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/islped/ZieglerLC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/AnwarSZR16, author = {Mohd Anwar and Sourav Saha and Matthew M. Ziegler and Lakshmi N. Reddy}, title = {Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis}, booktitle = {29th International Conference on {VLSI} Design and 15th International Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January 4-8, 2016}, pages = {116--121}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/VLSID.2016.94}, doi = {10.1109/VLSID.2016.94}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/AnwarSZR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ibmrd/ZyubanFDPPRDZCI15, author = {Victor V. Zyuban and Joshua Friedrich and Daniel M. Dreps and J{\"{u}}rgen Pille and Donald W. Plass and Phillip J. Restle and Zeynep Toprak Deniz and Matthew M. Ziegler and Sam G. Chu and Md. Saiful Islam and James D. Warnock and Bob Philhower and Rahul M. Rao and Gregory S. Still and David Shan and Eric Fluhr and Jose Paredes and Dieter F. Wendel and Christopher J. Gonzalez and D. Hogenmiller and Ruchir Puri and Scott A. Taylor and Stephen D. Posluszny}, title = {{IBM} {POWER8} circuit design and energy optimization}, journal = {{IBM} J. Res. Dev.}, volume = {59}, number = {1}, year = {2015}, url = {https://doi.org/10.1147/JRD.2014.2380200}, doi = {10.1147/JRD.2014.2380200}, timestamp = {Fri, 13 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/ibmrd/ZyubanFDPPRDZCI15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ibmrd/WarnockBWSMMMCM15, author = {James D. Warnock and Christopher J. Berry and Michael H. Wood and Leon J. Sigal and Yun{-}Chan Myung and Guenter Mayer and Mark D. Mayo and Y. Chan and Frank Malgioglio and Gerald Strevig and Charudhattan Nagarajan and Sean M. Carey and Gerard Salem and Friedrich Schroeder and Howard H. Smith and Di Phan and Ricardo Nigaglioni and Thomas Strach and Matthew M. Ziegler and Niels Fricke and K. Lind and Jos{\'{e}} Neves and Sridhar H. Rangarajan and J. P. Surprise and John Isakson and John Badar and Doug Malone and Donald W. Plass and A. Aipperspach and Dieter F. Wendel and Robert M. Averill III and Ruchir Puri}, title = {{IBM} z13 circuit design and methodology}, journal = {{IBM} J. Res. Dev.}, volume = {59}, number = {4/5}, year = {2015}, url = {https://doi.org/10.1147/JRD.2015.2446871}, doi = {10.1147/JRD.2015.2446871}, timestamp = {Fri, 13 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/ibmrd/WarnockBWSMMMCM15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/JoshiKKBZOKWHSR15, author = {Rajiv V. Joshi and Keunwoo Kim and Rouwaida Kanj and Ajay N. Bhoj and Matthew M. Ziegler and Phil Oldiges and Pranita Kerber and Robert Wong and Terence Hook and Sudesh Saroop and Carl Radens and Chun{-}Chen Yeh}, title = {Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {23}, number = {3}, pages = {534--543}, year = {2015}, url = {https://doi.org/10.1109/TVLSI.2014.2313815}, doi = {10.1109/TVLSI.2014.2313815}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/JoshiKKBZOKWHSR15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/WarnockCBFPCCSS15, author = {James D. Warnock and Brian W. Curran and John Badar and Gregory Fredeman and Donald W. Plass and Yuen H. Chan and Sean M. Carey and Gerard Salem and Friedrich Schroeder and Frank Malgioglio and Guenter Mayer and Christopher J. Berry and Michael H. Wood and Yiu{-}Hing Chan and Mark D. Mayo and John Isakson and Charudhattan Nagarajan and Tobias Werner and Leon J. Sigal and Ricardo Nigaglioni and Mark Cichanowski and Jeffrey A. Zitz and Matthew M. Ziegler and Tim Bronson and Gerald Strevig and Daniel Dreps and Ruchir Puri and Douglas Malone and Dieter F. Wendel and Pak{-}kin Mak and Michael A. Blake}, title = {4.1 22nm Next-generation {IBM} System z microprocessor}, booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC} 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015}, pages = {1--3}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/ISSCC.2015.7062930}, doi = {10.1109/ISSCC.2015.7062930}, timestamp = {Wed, 22 Jun 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isscc/WarnockCBFPCCSS15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsic/JoshiZWWA15, author = {Rajiv V. Joshi and Matthew M. Ziegler and Holger Wetter and C. Wandel and Herschel A. Ainspan}, title = {14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation}, booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19, 2015}, pages = {268}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/VLSIC.2015.7231283}, doi = {10.1109/VLSIC.2015.7231283}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/vlsic/JoshiZWWA15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cicc/ZieglerPPFLLVFGFZ14, author = {Matthew M. Ziegler and Ruchir Puri and Bob Philhower and Robert L. Franch and Wing K. Luk and Jens Leenstra and Peter Verwegen and Niels Fricke and George Gristede and Eric Fluhr and Victor V. Zyuban}, title = {{POWER8} design methodology innovations for improving productivity and reducing power}, booktitle = {Proceedings of the {IEEE} 2014 Custom Integrated Circuits Conference, {CICC} 2014, San Jose, CA, USA, September 15-17, 2014}, pages = {1--9}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/CICC.2014.6946042}, doi = {10.1109/CICC.2014.6946042}, timestamp = {Sun, 14 Nov 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/cicc/ZieglerPPFLLVFGFZ14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/icicdt/FriedrichLSSSFD14, author = {Joshua Friedrich and Hung Q. Le and William J. Starke and Jeff Stuecheli and Balaram Sinharoy and Eric J. Fluhr and Daniel M. Dreps and Victor V. Zyuban and Gregory S. Still and Christopher J. Gonzalez and David Hogenmiller and Frank Malgioglio and Ryan Nett and Ruchir Puri and Phillip J. Restle and David Shan and Zeynep Toprak Deniz and Dieter F. Wendel and Matthew M. Ziegler and Dave W. Victor}, title = {The POWER8\({}^{\mbox{TM}}\) processor: Designed for big data, analytics, and cloud environments}, booktitle = {2014 {IEEE} International Conference on {IC} Design {\&} Technology, {ICICDT} 2014, Austin, TX, USA, May 28-30, 2014}, pages = {1--4}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ICICDT.2014.6838618}, doi = {10.1109/ICICDT.2014.6838618}, timestamp = {Fri, 25 Feb 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/icicdt/FriedrichLSSSFD14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/islped/PuriCQZ14, author = {Ruchir Puri and Mihir R. Choudhury and Haifeng Qian and Matthew M. Ziegler}, editor = {Yuan Xie and Tanay Karnik and Muhammad M. Khellah and Renu Mehra}, title = {Bridging high performance and low power in processor design}, booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, {USA} - August 11 - 13, 2014}, pages = {183--188}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2627369.2631642}, doi = {10.1145/2627369.2631642}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/islped/PuriCQZ14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/FluhrFDZSGHHMNP14, author = {Eric J. Fluhr and Joshua Friedrich and Daniel M. Dreps and Victor V. Zyuban and Gregory S. Still and Christopher J. Gonzalez and Allen Hall and David Hogenmiller and Frank Malgioglio and Ryan Nett and Jose Paredes and Juergen Pille and Donald W. Plass and Ruchir Puri and Phillip J. Restle and David Shan and Kevin Stawiasz and Zeynep Toprak Deniz and Dieter F. Wendel and Matthew M. Ziegler}, title = {5.1 POWER8\({}^{\mbox{TM}}\): {A} 12-core server-class processor in 22nm {SOI} with 7.6Tb/s off-chip bandwidth}, booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference, {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014}, pages = {96--97}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ISSCC.2014.6757353}, doi = {10.1109/ISSCC.2014.6757353}, timestamp = {Fri, 25 Feb 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isscc/FluhrFDZSGHHMNP14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChoXRZP13, author = {Minsik Cho and Hua Xiang and Haoxing Ren and Matthew M. Ziegler and Ruchir Puri}, editor = {J{\"{o}}rg Henkel}, title = {LatchPlanner: latch placement algorithm for datapath-oriented high-performance {VLSI} designs}, booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013}, pages = {342--348}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/ICCAD.2013.6691141}, doi = {10.1109/ICCAD.2013.6691141}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iccad/ChoXRZP13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/islped/ZieglerGZ13, author = {Matthew M. Ziegler and George Gristede and Victor V. Zyuban}, editor = {Pai H. Chou and Ru Huang and Yuan Xie and Tanay Karnik}, title = {Power reduction by aggressive synthesis design space exploration}, booktitle = {International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013}, pages = {421--426}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/ISLPED.2013.6629335}, doi = {10.1109/ISLPED.2013.6629335}, timestamp = {Wed, 16 Oct 2019 14:14:56 +0200}, biburl = {https://dblp.org/rec/conf/islped/ZieglerGZ13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/XiangCRZP13, author = {Hua Xiang and Minsik Cho and Haoxing Ren and Matthew M. Ziegler and Ruchir Puri}, editor = {Cheng{-}Kok Koh and Cliff C. N. Sze}, title = {Network flow based datapath bit slicing}, booktitle = {International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013}, pages = {139--146}, publisher = {{ACM}}, year = {2013}, url = {https://doi.org/10.1145/2451916.2451954}, doi = {10.1145/2451916.2451954}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/XiangCRZP13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/islped/ZieglerZGVF09, author = {Matthew M. Ziegler and Victor V. Zyuban and George Gristede and Milena Vratonjic and Joshua Friedrich}, editor = {J{\"{o}}rg Henkel and Ali Keshavarzi and Naehyuck Chang and Tahir Ghani}, title = {The opportunity cost of low power design: a case study in circuit tuning}, booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009}, pages = {133--138}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1594233.1594265}, doi = {10.1145/1594233.1594265}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/islped/ZieglerZGVF09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/patmos/VratonjicZGZMCVO09, author = {Milena Vratonjic and Matthew M. Ziegler and George Gristede and Victor V. Zyuban and Thomas Mitchell and Ee Cho and Chandu Visweswariah and Vojin G. Oklobdzija}, editor = {Jos{\'{e}} Monteiro and Rene van Leuken}, title = {A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery {(FPR)}}, booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, {PATMOS} 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers}, series = {Lecture Notes in Computer Science}, volume = {5953}, pages = {307--316}, publisher = {Springer}, year = {2009}, url = {https://doi.org/10.1007/978-3-642-11802-9\_35}, doi = {10.1007/978-3-642-11802-9\_35}, timestamp = {Tue, 13 Sep 2022 21:45:42 +0200}, biburl = {https://dblp.org/rec/conf/patmos/VratonjicZGZMCVO09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/BhavnagarwalaKR08, author = {Azeez J. Bhavnagarwala and Stephen Kosonocky and Carl Radens and Yuen H. Chan and Kevin Stawiasz and Uma Srinivasan and Steven P. Kowalczyk and Matthew M. Ziegler}, title = {A Sub-600-mV, Fluctuation Tolerant 65-nm {CMOS} {SRAM} Array With Dynamic Cell Biasing}, journal = {{IEEE} J. Solid State Circuits}, volume = {43}, number = {4}, pages = {946--955}, year = {2008}, url = {https://doi.org/10.1109/JSSC.2008.917506}, doi = {10.1109/JSSC.2008.917506}, timestamp = {Tue, 19 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/BhavnagarwalaKR08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/ZieglerDKQS07, author = {Matthew M. Ziegler and Gary S. Ditlow and Stephen V. Kosonocky and Zhenyu Qi and Mircea R. Stan}, editor = {Hai Zhou and Enrico Macii and Zhiyuan Yan and Yehia Massoud}, title = {Structured and tuned array generation {(STAG)} for high-performance random logic}, booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007}, pages = {257--262}, publisher = {{ACM}}, year = {2007}, url = {https://doi.org/10.1145/1228784.1228849}, doi = {10.1145/1228784.1228849}, timestamp = {Wed, 16 Aug 2023 21:16:32 +0200}, biburl = {https://dblp.org/rec/conf/glvlsi/ZieglerDKQS07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/QiZKRS07, author = {Zhenyu Qi and Matthew M. Ziegler and Stephen V. Kosonocky and Jan M. Rabaey and Mircea R. Stan}, title = {Multi-Dimensional Circuit and Micro-Architecture Level Optimization}, booktitle = {8th International Symposium on Quality of Electronic Design {(ISQED} 2007), 26-28 March 2007, San Jose, CA, {USA}}, pages = {275--280}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/ISQED.2007.105}, doi = {10.1109/ISQED.2007.105}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/QiZKRS07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/StanRZ06, author = {Mircea R. Stan and Garrett S. Rose and Matthew M. Ziegler}, title = {Hybrid CMOS/Molecular Electronic Circuits}, booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006), 3-7 January 2006, Hyderabad, India}, pages = {703--708}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/VLSID.2006.99}, doi = {10.1109/VLSID.2006.99}, timestamp = {Sun, 12 Nov 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/StanRZ06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/RoseZS04, author = {Garrett S. Rose and Matthew M. Ziegler and Mircea R. Stan}, title = {Large-signal two-terminal device model for nanoelectronic circuit analysis}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {12}, number = {11}, pages = {1201--1208}, year = {2004}, url = {https://doi.org/10.1109/TVLSI.2004.836291}, doi = {10.1109/TVLSI.2004.836291}, timestamp = {Mon, 13 Jun 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/RoseZS04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ZieglerS04, author = {Matthew M. Ziegler and Mircea R. Stan}, title = {A Unified Design Space for Regular Parallel Prefix Adders}, booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2004), 16-20 February 2004, Paris, France}, pages = {1386--1387}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/DATE.2004.1269100}, doi = {10.1109/DATE.2004.1269100}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/ZieglerS04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/pieee/StanFGLZ03, author = {Mircea R. Stan and Paul D. Franzon and Seth Copen Goldstein and John C. Lach and Matthew M. Ziegler}, title = {Molecular electronics: from devices and interconnect to circuits and architecture}, journal = {Proc. {IEEE}}, volume = {91}, number = {11}, pages = {1940--1957}, year = {2003}, url = {https://doi.org/10.1109/JPROC.2003.818327}, doi = {10.1109/JPROC.2003.818327}, timestamp = {Thu, 23 Sep 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/pieee/StanFGLZ03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/ZieglerS03, author = {Matthew M. Ziegler and Mircea R. Stan}, title = {The CMOS/nano interface from a circuits perspective}, booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems, {ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003}, pages = {904--907}, publisher = {{IEEE}}, year = {2003}, url = {https://doi.org/10.1109/ISCAS.2003.1206367}, doi = {10.1109/ISCAS.2003.1206367}, timestamp = {Sun, 25 Oct 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iscas/ZieglerS03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ZieglerS02, author = {Matthew M. Ziegler and Mircea R. Stan}, editor = {Lawrence T. Pileggi and Andreas Kuehlmann}, title = {A Case for CMOS/nano co-design}, booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002}, pages = {348--352}, publisher = {{ACM} / {IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1145/774572.774624}, doi = {10.1145/774572.774624}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/ZieglerS02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/ZieglerS01, author = {Matthew M. Ziegler and Mircea Stan}, title = {Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product}, booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems, {ISCAS} 2001, Sydney, Australia, May 6-9, 2001}, pages = {657--660}, publisher = {{IEEE}}, year = {2001}, url = {https://doi.org/10.1109/ISCAS.2001.921156}, doi = {10.1109/ISCAS.2001.921156}, timestamp = {Sun, 12 Nov 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iscas/ZieglerS01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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