BibTeX records: Chung-Jay Yang

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@article{DBLP:journals/tcas/UengYYLY13,
  author       = {Yeong{-}Luh Ueng and
                  Bo{-}Jhang Yang and
                  Chung{-}Jay Yang and
                  Huang{-}Chang Lee and
                  Jeng{-}Da Yang},
  title        = {An Efficient Multi-Standard {LDPC} Decoder Design Using Hardware-Friendly
                  Shuffled Decoding},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {60-I},
  number       = {3},
  pages        = {743--756},
  year         = {2013},
  url          = {https://doi.org/10.1109/TCSI.2012.2215746},
  doi          = {10.1109/TCSI.2012.2215746},
  timestamp    = {Fri, 22 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/UengYYLY13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tsp/UengLCY13,
  author       = {Yeong{-}Luh Ueng and
                  Kuo{-}Hsuan Liao and
                  Hsueh{-}Chih Chou and
                  Chung{-}Jay Yang},
  title        = {A High-Throughput Trellis-Based Layered Decoding Architecture for
                  Non-Binary {LDPC} Codes Using Max-Log-QSPA},
  journal      = {{IEEE} Trans. Signal Process.},
  volume       = {61},
  number       = {11},
  pages        = {2940--2951},
  year         = {2013},
  url          = {https://doi.org/10.1109/TSP.2013.2256905},
  doi          = {10.1109/TSP.2013.2256905},
  timestamp    = {Tue, 10 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tsp/UengLCY13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/UengLYCLC12,
  author       = {Yeong{-}Luh Ueng and
                  Chen{-}Yap Leong and
                  Chung{-}Jay Yang and
                  Chung{-}Chao Cheng and
                  Kuo{-}Hsuan Liao and
                  Shu{-}Wei Chen},
  title        = {An Efficient Layered Decoding Architecture for Nonbinary {QC-LDPC}
                  Codes},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {59-I},
  number       = {2},
  pages        = {385--398},
  year         = {2012},
  url          = {https://doi.org/10.1109/TCSI.2011.2163889},
  doi          = {10.1109/TCSI.2011.2163889},
  timestamp    = {Fri, 22 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/UengLYCLC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tsp/UengWKYS12,
  author       = {Yeong{-}Luh Ueng and
                  Yu{-}Luen Wang and
                  Li{-}Sheng Kan and
                  Chung{-}Jay Yang and
                  Yung{-}Hsiang Su},
  title        = {Jointly Designed Architecture-Aware {LDPC} Convolutional Codes and
                  Memory-Based Shuffled Decoder Architecture},
  journal      = {{IEEE} Trans. Signal Process.},
  volume       = {60},
  number       = {8},
  pages        = {4387--4402},
  year         = {2012},
  url          = {https://doi.org/10.1109/TSP.2012.2197749},
  doi          = {10.1109/TSP.2012.2197749},
  timestamp    = {Tue, 10 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tsp/UengWKYS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/WangUPY11,
  author       = {Yu{-}Luen Wang and
                  Yeong{-}Luh Ueng and
                  Chien{-}Lien Peng and
                  Chung{-}Jay Yang},
  title        = {Processing-Task Arrangement for a Low-Complexity Full-Mode WiMAX {LDPC}
                  Codec},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {58-I},
  number       = {2},
  pages        = {415--428},
  year         = {2011},
  url          = {https://doi.org/10.1109/TCSI.2010.2071910},
  doi          = {10.1109/TCSI.2010.2071910},
  timestamp    = {Fri, 22 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/WangUPY11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isocc/UengYCW11,
  author       = {Yeong{-}Luh Ueng and
                  Chung{-}Jay Yang and
                  Shu{-}Wei Chen and
                  Wei{-}Xuan Wu},
  title        = {A selective-input non-binary {LDPC} decoder architecture},
  booktitle    = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
                  November 17-18, 2011},
  pages        = {40--43},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/ISOCC.2011.6138641},
  doi          = {10.1109/ISOCC.2011.6138641},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isocc/UengYCW11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/UengYWC10,
  author       = {Yeong{-}Luh Ueng and
                  Chung{-}Jay Yang and
                  Kuan{-}Chieh Wang and
                  Chun{-}Jung Chen},
  title        = {A Multimode Shuffled Iterative Decoder Architecture for High-Rate
                  {RS-LDPC} Codes},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {57-I},
  number       = {10},
  pages        = {2790--2803},
  year         = {2010},
  url          = {https://doi.org/10.1109/TCSI.2010.2046964},
  doi          = {10.1109/TCSI.2010.2046964},
  timestamp    = {Fri, 22 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/UengYWC10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/UengYC09,
  author       = {Yeong{-}Luh Ueng and
                  Chung{-}Jay Yang and
                  Chun{-}Jung Chen},
  title        = {A Shuffled Message-passing Decoding Method for Memory-based {LDPC}
                  Decoders},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2009), 24-17
                  May 2009, Taipei, Taiwan},
  pages        = {892--895},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/ISCAS.2009.5117900},
  doi          = {10.1109/ISCAS.2009.5117900},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/UengYC09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/UengYWWW08,
  author       = {Yeong{-}Luh Ueng and
                  Chung{-}Jay Yang and
                  Zong{-}Cheng Wu and
                  Chen{-}Eng Wu and
                  Yu{-}Lun Wang},
  title        = {{VLSI} decoding architecture with improved convergence speed and reduced
                  decoding latency for irregular {LDPC} codes in WiMAX},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
                  May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
  pages        = {520--523},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISCAS.2008.4541469},
  doi          = {10.1109/ISCAS.2008.4541469},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/UengYWWW08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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