BibTeX records: Koji Yamakawa

download as .bib file

@article{DBLP:journals/jssc/TakashimaSHMSHOTDFWFOKSYKHN11,
  author       = {Daisaburo Takashima and
                  Hidehiro Shiga and
                  Daisuke Hashimoto and
                  Tadashi Miyakawa and
                  Shinichiro Shiratake and
                  Katsuhiko Hoya and
                  Ryu Ogiwara and
                  Ryosuke Takizawa and
                  Ryosuke Doumae and
                  Ryo Fukuda and
                  Yohji Watanabe and
                  Shuso Fujii and
                  Tohru Ozaki and
                  Hiroyuki Kanaya and
                  Susumu Shuto and
                  Koji Yamakawa and
                  Iwao Kunishima and
                  Takeshi Hamamoto and
                  Akihiro Nitayama},
  title        = {A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 {V} Chain
                  FeRAMs},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {46},
  number       = {9},
  pages        = {2171--2179},
  year         = {2011},
  url          = {https://doi.org/10.1109/JSSC.2011.2159053},
  doi          = {10.1109/JSSC.2011.2159053},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/TakashimaSHMSHOTDFWFOKSYKHN11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF10,
  author       = {Hidehiro Shiga and
                  Daisaburo Takashima and
                  Shinichiro Shiratake and
                  Katsuhiko Hoya and
                  Tadashi Miyakawa and
                  Ryu Ogiwara and
                  Ryo Fukuda and
                  Ryosuke Takizawa and
                  Kosuke Hatsuda and
                  Fumiyoshi Matsuoka and
                  Yasushi Nagadomi and
                  Daisuke Hashimoto and
                  Hisaaki Nishimura and
                  Takeshi Hioka and
                  Sumiko M. Doumae and
                  Shoichi Shimizu and
                  Mitsumo Kawano and
                  Toyoki Taguchi and
                  Yohji Watanabe and
                  Shuso Fujii and
                  Tohru Ozaki and
                  Hiroyuki Kanaya and
                  Yoshinori Kumura and
                  Yoshiro Shimojo and
                  Yuki Yamada and
                  Yoshihiro Minami and
                  Susumu Shuto and
                  Koji Yamakawa and
                  Soichi Yamazaki and
                  Iwao Kunishima and
                  Takeshi Hamamoto and
                  Akihiro Nitayama and
                  Tohru Furuyama},
  title        = {A 1.6 GB/s {DDR2} 128 Mb Chain FeRAM With Scalable Octal Bitline and
                  Sensing Schemes},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {45},
  number       = {1},
  pages        = {142--152},
  year         = {2010},
  url          = {https://doi.org/10.1109/JSSC.2009.2034414},
  doi          = {10.1109/JSSC.2009.2034414},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/HoyaTSOMSDOKSOYKNF10,
  author       = {Katsuhiko Hoya and
                  Daisaburo Takashima and
                  Shinichiro Shiratake and
                  Ryu Ogiwara and
                  Tadashi Miyakawa and
                  Hidehiro Shiga and
                  Sumiko M. Doumae and
                  Sumito Ohtsuki and
                  Yoshinori Kumura and
                  Susumu Shuto and
                  Tohru Ozaki and
                  Koji Yamakawa and
                  Iwao Kunishima and
                  Akihiro Nitayama and
                  Shuso Fujii},
  title        = {A 64-Mb Chain FeRAM With Quad {BL} Architecture and 200 MB/s Burst
                  Mode},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {18},
  number       = {12},
  pages        = {1745--1752},
  year         = {2010},
  url          = {https://doi.org/10.1109/TVLSI.2009.2034380},
  doi          = {10.1109/TVLSI.2009.2034380},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HoyaTSOMSDOKSOYKNF10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/TakashimaSHMSHOTDFWFOKSYKHN10,
  author       = {Daisaburo Takashima and
                  Hidehiro Shiga and
                  Daisuke Hashimoto and
                  Tadashi Miyakawa and
                  Shinichiro Shiratake and
                  Katsuhiko Hoya and
                  Ryu Ogiwara and
                  Ryosuke Takizawa and
                  Ryosuke Doumae and
                  Ryo Fukuda and
                  Yohji Watanabe and
                  Shuso Fujii and
                  Tohru Ozaki and
                  Hiroyuki Kanaya and
                  Susumu Shuto and
                  Koji Yamakawa and
                  Iwao Kunishima and
                  Takeshi Hamamoto and
                  Akihiro Nitayama},
  title        = {A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
                  Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
                  2010},
  pages        = {262--263},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSCC.2010.5433950},
  doi          = {10.1109/ISSCC.2010.5433950},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/TakashimaSHMSHOTDFWFOKSYKHN10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF09,
  author       = {Hidehiro Shiga and
                  Daisaburo Takashima and
                  Shinichiro Shiratake and
                  Katsuhiko Hoya and
                  Tadashi Miyakawa and
                  Ryu Ogiwara and
                  Ryo Fukuda and
                  Ryosuke Takizawa and
                  Kosuke Hatsuda and
                  Fumiyoshi Matsuoka and
                  Yasushi Nagadomi and
                  Daisuke Hashimoto and
                  Hisaaki Nishimura and
                  Takeshi Hioka and
                  Sumiko M. Doumae and
                  Shoichi Shimizu and
                  Mitsumo Kawano and
                  Toyoki Taguchi and
                  Yohji Watanabe and
                  Shuso Fujii and
                  Tohru Ozaki and
                  Hiroyuki Kanaya and
                  Yoshinori Kumura and
                  Yoshiro Shimojo and
                  Yuki Yamada and
                  Yoshihiro Minami and
                  Susumu Shuto and
                  Koji Yamakawa and
                  Soichi Yamazaki and
                  Iwao Kunishima and
                  Takeshi Hamamoto and
                  Akihiro Nitayama and
                  Tohru Furuyama},
  title        = {A 1.6GB/s {DDR2} 128Mb chain FeRAM with scalable octal bitline and
                  sensing schemes},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
                  Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
                  2009},
  pages        = {464--465},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/ISSCC.2009.4977509},
  doi          = {10.1109/ISSCC.2009.4977509},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/HoyaTSOMSDOKSOY06,
  author       = {Katsuhiko Hoya and
                  Daisaburo Takashima and
                  Shinichiro Shiratake and
                  Ryu Ogiwara and
                  Tadashi Miyakawa and
                  Hidehiro Shiga and
                  Sumiko M. Doumae and
                  Sumito Ohtsuki and
                  Yoshinori Kumura and
                  Susumu Shuto and
                  Tohru Ozaki and
                  Koji Yamakawa and
                  Iwao Kunishima and
                  Akihiro Nitayama and
                  Shuso Fujii},
  title        = {A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode},
  booktitle    = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
                  2006, Digest of Technical Papers, an Francisco, CA, USA, February
                  6-9, 2006},
  pages        = {459--466},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ISSCC.2006.1696078},
  doi          = {10.1109/ISSCC.2006.1696078},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/HoyaTSOMSDOKSOY06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ShiratakeMTOKHO03,
  author       = {Shinichiro Shiratake and
                  Tadashi Miyakawa and
                  Yoshiaki Takeuchi and
                  Ryu Ogiwara and
                  Masahiro Kamoshida and
                  Katsuhiko Hoya and
                  Kohei Oikawa and
                  Tohru Ozaki and
                  Iwao Kunishima and
                  Koji Yamakawa and
                  Shigeki Sugimoto and
                  Daisaburo Takashima and
                  Hans{-}Oliver Joachim and
                  Norbert Rehm and
                  Joerg Wohlfahrt and
                  Nicolas Nagel and
                  Gerhard Beitel and
                  Michael Jacob and
                  Thomas Roehr},
  title        = {A 32-Mb chain FeRAM with segment/stitch array architecture},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {38},
  number       = {11},
  pages        = {1911--1919},
  year         = {2003},
  url          = {https://doi.org/10.1109/JSSC.2003.818161},
  doi          = {10.1109/JSSC.2003.818161},
  timestamp    = {Wed, 20 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ShiratakeMTOKHO03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/TakashimaTMIOKH01,
  author       = {Daisaburo Takashima and
                  Yoshiaki Takeuchi and
                  Tadashi Miyakawa and
                  Yasuo Itoh and
                  Ryu Ogiwara and
                  Masahiro Kamoshida and
                  Katsuhiko Hoya and
                  Sumiko Mano Doumae and
                  Tohru Ozaki and
                  Hiroyuki Kanaya and
                  Koji Yamakawa and
                  Iwao Kunishima and
                  Yukihito Oowaki},
  title        = {A 76-mm\({}^{\mbox{2}}\) 8-Mb chain ferroelectric memory},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {36},
  number       = {11},
  pages        = {1713--1720},
  year         = {2001},
  url          = {https://doi.org/10.1109/4.962293},
  doi          = {10.1109/4.962293},
  timestamp    = {Wed, 06 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/TakashimaTMIOKH01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.