BibTeX records: Tomoaki Yabe

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@article{DBLP:journals/jssc/TachibanaHTSKKSNSYU14,
  author       = {Fumihiko Tachibana and
                  Osamu Hirabayashi and
                  Yasuhisa Takeyama and
                  Miyako Shizuno and
                  Atsushi Kawasumi and
                  Keiichi Kushida and
                  Azuma Suzuki and
                  Yusuke Niki and
                  Shinichi Sasaki and
                  Tomoaki Yabe and
                  Yasuo Unekawa},
  title        = {A 27{\%} Active and 85{\%} Standby Power Reduction in Dual-Power-Supply
                  {SRAM} Using {BL} Power Calculator and Digitally Controllable Retention
                  Circuit},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {49},
  number       = {1},
  pages        = {118--126},
  year         = {2014},
  url          = {https://doi.org/10.1109/JSSC.2013.2280312},
  doi          = {10.1109/JSSC.2013.2280312},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/TachibanaHTSKKSNSYU14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/TachibanaHTSKKSNSYU13,
  author       = {Fumihiko Tachibana and
                  Osamu Hirabayashi and
                  Yasuhisa Takeyama and
                  Miyako Shizuno and
                  Atsushi Kawasumi and
                  Keiichi Kushida and
                  Azuma Suzuki and
                  Yusuke Niki and
                  Shinichi Sasaki and
                  Tomoaki Yabe and
                  Yasuo Unekawa},
  title        = {A 27{\%} active and 85{\%} standby power reduction in dual-power-supply
                  {SRAM} using {BL} power calculator and digitally controllable retention
                  circuit},
  booktitle    = {2013 {IEEE} International Solid-State Circuits Conference - Digest
                  of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
                  17-21, 2013},
  pages        = {320--321},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISSCC.2013.6487752},
  doi          = {10.1109/ISSCC.2013.6487752},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/TachibanaHTSKKSNSYU13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/icicdt/KawasumiTHKTNSY12,
  author       = {Atsushi Kawasumi and
                  Yasuhisa Takeyama and
                  Osamu Hirabayashi and
                  Keiichi Kushida and
                  Fumihiko Tachibana and
                  Yusuke Niki and
                  Shinichi Sasaki and
                  Tomoaki Yabe},
  title        = {Energy efficiency deterioration by variability in {SRAM} and circuit
                  techniques for energy saving without voltage reduction},
  booktitle    = {{IEEE} International Conference on {IC} Design {\&} Technology,
                  {ICICDT} 2012, Austin, TX, USA, May 30 - June 1, 2012},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ICICDT.2012.6232859},
  doi          = {10.1109/ICICDT.2012.6232859},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/icicdt/KawasumiTHKTNSY12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/KawasumiTHKTNSY12,
  author       = {Atsushi Kawasumi and
                  Yasuhisa Takeyama and
                  Osamu Hirabayashi and
                  Keiichi Kushida and
                  Fumihiko Tachibana and
                  Yusuke Niki and
                  Shinichi Sasaki and
                  Tomoaki Yabe},
  title        = {A 47{\%} access time reduction with a worst-case timing-generation
                  scheme utilizing a statistical method for ultra low voltage SRAMs},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
                  13-15, 2012},
  pages        = {100--101},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/VLSIC.2012.6243809},
  doi          = {10.1109/VLSIC.2012.6243809},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/KawasumiTHKTNSY12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/NikiKSTHKTFY11,
  author       = {Yusuke Niki and
                  Atsushi Kawasumi and
                  Azuma Suzuki and
                  Yasuhisa Takeyama and
                  Osamu Hirabayashi and
                  Keiichi Kushida and
                  Fumihiko Tachibana and
                  Yuki Fujimura and
                  Tomoaki Yabe},
  title        = {A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant
                  Timing Generation of {SRAM} Sense Amplifiers},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {46},
  number       = {11},
  pages        = {2545--2551},
  year         = {2011},
  url          = {https://doi.org/10.1109/JSSC.2011.2164294},
  doi          = {10.1109/JSSC.2011.2164294},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/NikiKSTHKTFY11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asscc/KushidaHTHKSTFN11,
  author       = {Keiichi Kushida and
                  Osamu Hirabayashi and
                  Fumihiko Tachibana and
                  Hiroyuki Hara and
                  Atsushi Kawasumi and
                  Azuma Suzuki and
                  Yasuhisa Takeyama and
                  Yuki Fujimura and
                  Yusuke Niki and
                  Miyako Shizuno and
                  Shinichi Sasaki and
                  Tomoaki Yabe},
  title        = {A trimless, 0.5V-1.0V wide voltage operation, high density {SRAM}
                  macro utilizing dynamic cell stability monitor and multiple memory
                  cell access},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
                  South Korea, November 14-16, 2011},
  pages        = {161--164},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/ASSCC.2011.6123627},
  doi          = {10.1109/ASSCC.2011.6123627},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/asscc/KushidaHTHKSTFN11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/KawasumiTHKFY10,
  author       = {Atsushi Kawasumi and
                  Yasuhisa Takeyama and
                  Osamu Hirabayashi and
                  Keiichi Kushida and
                  Yuki Fujimura and
                  Tomoaki Yabe},
  title        = {A Low-Supply-Voltage-Operation {SRAM} With {HCI} Trimmed Sense Amplifiers},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {45},
  number       = {11},
  pages        = {2341--2347},
  year         = {2010},
  url          = {https://doi.org/10.1109/JSSC.2010.2065750},
  doi          = {10.1109/JSSC.2010.2065750},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KawasumiTHKFY10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/FujimuraHSSKTKFKNY10,
  author       = {Yuki Fujimura and
                  Osamu Hirabayashi and
                  Takahiko Sasaki and
                  Azuma Suzuki and
                  Atsushi Kawasumi and
                  Yasuhisa Takeyama and
                  Keiichi Kushida and
                  Gou Fukano and
                  Akira Katayama and
                  Yusuke Niki and
                  Tomoaki Yabe},
  title        = {A configurable {SRAM} with constant-negative-level write buffer for
                  low-voltage operation with 0.149{\(\mathrm{\mu}\)}m\({}^{\mbox{2}}\)
                  cell in 32nm high-k metal-gate {CMOS}},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
                  Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
                  2010},
  pages        = {348--349},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSCC.2010.5433813},
  doi          = {10.1109/ISSCC.2010.5433813},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/FujimuraHSSKTKFKNY10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/KushidaSFKHTSKF09,
  author       = {Keiichi Kushida and
                  Azuma Suzuki and
                  Gou Fukano and
                  Atsushi Kawasumi and
                  Osamu Hirabayashi and
                  Yasuhisa Takeyama and
                  Takahiko Sasaki and
                  Akira Katayama and
                  Yuki Fujimura and
                  Tomoaki Yabe},
  title        = {A 0.7 {V} Single-Supply {SRAM} With 0.495 {\(\mathrm{\mu}\)}m\({}^{\mbox{2}}\)
                  Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier
                  and Cascaded Bit Line Scheme},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {44},
  number       = {4},
  pages        = {1192--1198},
  year         = {2009},
  url          = {https://doi.org/10.1109/JSSC.2009.2014009},
  doi          = {10.1109/JSSC.2009.2014009},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KushidaSFKHTSKF09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/HirabayashiKSTKSKFFNSKY09,
  author       = {Osamu Hirabayashi and
                  Atsushi Kawasumi and
                  Azuma Suzuki and
                  Yasuhisa Takeyama and
                  Keiichi Kushida and
                  Takahiko Sasaki and
                  Akira Katayama and
                  Gou Fukano and
                  Yuki Fujimura and
                  Takaaki Nakazato and
                  Yasushi Shizuki and
                  Natsuki Kushiyama and
                  Tomoaki Yabe},
  title        = {A process-variation-tolerant dual-power-supply {SRAM} with 0.179{\(\mathrm{\mu}\)}m\({}^{\mbox{2}}\)
                  Cell in 40nm {CMOS} using level-programmable wordline driver},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
                  Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
                  2009},
  pages        = {458--459},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/ISSCC.2009.4977506},
  doi          = {10.1109/ISSCC.2009.4977506},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/HirabayashiKSTKSKFFNSKY09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/KawasumiYTHKTSKFFO08,
  author       = {Atsushi Kawasumi and
                  Tomoaki Yabe and
                  Yasuhisa Takeyama and
                  Osamu Hirabayashi and
                  Keiichi Kushida and
                  Akihito Tohata and
                  Takahiko Sasaki and
                  Akira Katayama and
                  Gou Fukano and
                  Yuki Fujimura and
                  Nobuaki Otsuka},
  title        = {A Single-Power-Supply 0.7V 1GHz 45nm {SRAM} with An Asymmetrical Unit-{\texttimes}-ratio
                  Memory Cell},
  booktitle    = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2008, Digest of Technical Papers, San Francisco, CA, USA, February
                  3-7, 2008},
  pages        = {382--383},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISSCC.2008.4523217},
  doi          = {10.1109/ISSCC.2008.4523217},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/KawasumiYTHKTSKFFO08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/itc/KatayamaYHTKSO08,
  author       = {Akira Katayama and
                  Tomoaki Yabe and
                  Osamu Hirabayashi and
                  Yasuhisa Takeyama and
                  Keiichi Kushida and
                  Takahiko Sasaki and
                  Nobuaki Otsuka},
  editor       = {Douglas Young and
                  Nur A. Touba},
  title        = {Direct Cell-Stability Test Techniques for an {SRAM} Macro with Asymmetric
                  Cell-Bias-Voltage Modulation},
  booktitle    = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara,
                  California, USA, October 26-31, 2008},
  pages        = {1--7},
  publisher    = {{IEEE} Computer Society},
  year         = {2008},
  url          = {https://doi.org/10.1109/TEST.2008.4700616},
  doi          = {10.1109/TEST.2008.4700616},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/itc/KatayamaYHTKSO08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/itc/HirabayashiSYKTKTO02,
  author       = {Osamu Hirabayashi and
                  Azuma Suzuki and
                  Tomoaki Yabe and
                  Atsushi Kawasumi and
                  Yasuhisa Takeyama and
                  Keiichi Kushida and
                  Akihito Tohata and
                  Nobuaki Otsuka},
  title        = {{DFT} Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs},
  booktitle    = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
                  MD, USA, October 7-10, 2002},
  pages        = {164--169},
  publisher    = {{IEEE} Computer Society},
  year         = {2002},
  url          = {https://doi.org/10.1109/TEST.2002.1041757},
  doi          = {10.1109/TEST.2002.1041757},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/itc/HirabayashiSYKTKTO02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/YabeMSWHWEHMTON98,
  author       = {Tomoaki Yabe and
                  Shinji Miyano and
                  Katsuhiko Sato and
                  Masaharu Wada and
                  Ryo Haga and
                  Osamu Wada and
                  Motohiro Enkaku and
                  Takehiko Hojyo and
                  Kenichiro Mimoto and
                  Masaaki Tazawa and
                  Tsutomu Ohkubo and
                  Kenji Numata},
  title        = {A configurable {DRAM} macro design for 2112 derivative organizations
                  to be synthesized using a memory generator},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {33},
  number       = {11},
  pages        = {1752--1757},
  year         = {1998},
  url          = {https://doi.org/10.1109/4.726570},
  doi          = {10.1109/4.726570},
  timestamp    = {Tue, 05 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/YabeMSWHWEHMTON98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cicc/TakeuchiYMHEYM98,
  author       = {Hideki Takeuchi and
                  Tomoaki Yabe and
                  Shinji Miyano and
                  Takehiko Hojo and
                  Motohiro Enkaku and
                  Masaaki Yamada and
                  Masami Murakata},
  title        = {A {DRAM} module generator with an expandable cell array scheme},
  booktitle    = {Proceedings of the {IEEE} 1998 Custom Integrated Circuits Conference,
                  {CICC} 1998, Santa Clara, CA, USA, May 11-14, 1998},
  pages        = {287--290},
  publisher    = {{IEEE}},
  year         = {1998},
  url          = {https://doi.org/10.1109/CICC.1998.694982},
  doi          = {10.1109/CICC.1998.694982},
  timestamp    = {Fri, 07 Jul 2023 11:00:51 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/TakeuchiYMHEYM98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/MiyanoNSYWHESKIOKYSKYSFHHNNR95,
  author       = {Shinji Miyano and
                  Kenji Numata and
                  Katsuhiko Sato and
                  Tomoaki Yabe and
                  Masaharu Wada and
                  Ryo Haga and
                  Motohiro Enkaku and
                  Masazumi Shiochi and
                  Yutaka Kawashima and
                  Masayuki Iwase and
                  Masahisa Ohgata and
                  Junpei Kumagai and
                  Takeshi Yoshida and
                  Masaomi Sakurai and
                  Seiji Kaki and
                  Narutoshi Yanagiya and
                  Hiroshi Shinya and
                  Tohm Fumyama and
                  Paul Hansen and
                  Marc Hannah and
                  Michael Nagy and
                  Anan Nagarajan and
                  Mana Rungsea},
  title        = {A 1.6 Gbyte/s data transfer rate 8 Mb embedded {DRAM}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {30},
  number       = {11},
  pages        = {1281--1285},
  year         = {1995},
  url          = {https://doi.org/10.1109/4.475717},
  doi          = {10.1109/4.475717},
  timestamp    = {Wed, 03 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/MiyanoNSYWHESKIOKYSKYSFHHNNR95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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