BibTeX records: Yohji Watanabe

download as .bib file

@inproceedings{DBLP:conf/vlsi-dat/HoyaHTWSK19,
  author       = {Katsuhiko Hoya and
                  Kosuke Hatsuda and
                  Kenji Tsuchida and
                  Yohji Watanabe and
                  Yusuke Shirota and
                  Tatsunori Kanai},
  title        = {A perspective on {NVRAM} technology for future computing system},
  booktitle    = {International Symposium on {VLSI} Design, Automation and Test, {VLSI-DAT}
                  2019, Hsinchu, Taiwan, April 22-25, 2019},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/VLSI-DAT.2019.8741675},
  doi          = {10.1109/VLSI-DAT.2019.8741675},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi-dat/HoyaHTWSK19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/TakashimaNHWF11,
  author       = {Daisaburo Takashima and
                  Yasushi Nagadomi and
                  Kosuke Hatsuda and
                  Yohji Watanabe and
                  Shuso Fujii},
  title        = {A 128 Mb Chain FeRAM and System Design for {HDD} Application and Enhanced
                  {HDD} Performance},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {46},
  number       = {2},
  pages        = {530--536},
  year         = {2011},
  url          = {https://doi.org/10.1109/JSSC.2010.2091324},
  doi          = {10.1109/JSSC.2010.2091324},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/TakashimaNHWF11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/TakashimaSHMSHOTDFWFOKSYKHN11,
  author       = {Daisaburo Takashima and
                  Hidehiro Shiga and
                  Daisuke Hashimoto and
                  Tadashi Miyakawa and
                  Shinichiro Shiratake and
                  Katsuhiko Hoya and
                  Ryu Ogiwara and
                  Ryosuke Takizawa and
                  Ryosuke Doumae and
                  Ryo Fukuda and
                  Yohji Watanabe and
                  Shuso Fujii and
                  Tohru Ozaki and
                  Hiroyuki Kanaya and
                  Susumu Shuto and
                  Koji Yamakawa and
                  Iwao Kunishima and
                  Takeshi Hamamoto and
                  Akihiro Nitayama},
  title        = {A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 {V} Chain
                  FeRAMs},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {46},
  number       = {9},
  pages        = {2171--2179},
  year         = {2011},
  url          = {https://doi.org/10.1109/JSSC.2011.2159053},
  doi          = {10.1109/JSSC.2011.2159053},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/TakashimaSHMSHOTDFWFOKSYKHN11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF10,
  author       = {Hidehiro Shiga and
                  Daisaburo Takashima and
                  Shinichiro Shiratake and
                  Katsuhiko Hoya and
                  Tadashi Miyakawa and
                  Ryu Ogiwara and
                  Ryo Fukuda and
                  Ryosuke Takizawa and
                  Kosuke Hatsuda and
                  Fumiyoshi Matsuoka and
                  Yasushi Nagadomi and
                  Daisuke Hashimoto and
                  Hisaaki Nishimura and
                  Takeshi Hioka and
                  Sumiko M. Doumae and
                  Shoichi Shimizu and
                  Mitsumo Kawano and
                  Toyoki Taguchi and
                  Yohji Watanabe and
                  Shuso Fujii and
                  Tohru Ozaki and
                  Hiroyuki Kanaya and
                  Yoshinori Kumura and
                  Yoshiro Shimojo and
                  Yuki Yamada and
                  Yoshihiro Minami and
                  Susumu Shuto and
                  Koji Yamakawa and
                  Soichi Yamazaki and
                  Iwao Kunishima and
                  Takeshi Hamamoto and
                  Akihiro Nitayama and
                  Tohru Furuyama},
  title        = {A 1.6 GB/s {DDR2} 128 Mb Chain FeRAM With Scalable Octal Bitline and
                  Sensing Schemes},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {45},
  number       = {1},
  pages        = {142--152},
  year         = {2010},
  url          = {https://doi.org/10.1109/JSSC.2009.2034414},
  doi          = {10.1109/JSSC.2009.2034414},
  timestamp    = {Fri, 15 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/TsuchidaIFUSAKISIKKASYW10,
  author       = {Kenji Tsuchida and
                  Tsuneo Inaba and
                  Katsuyuki Fujita and
                  Yoshihiro Ueda and
                  Takafumi Shimizu and
                  Yoshiaki Asao and
                  Takeshi Kajiyama and
                  Masayoshi Iwayama and
                  Kuniaki Sugiura and
                  Sumio Ikegawa and
                  Tatsuya Kishi and
                  Tadashi Kai and
                  Minoru Amano and
                  Naoharu Shimomura and
                  Hiroaki Yoda and
                  Yohji Watanabe},
  title        = {A 64Mb {MRAM} with clamped-reference and adequate-reference schemes},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
                  Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
                  2010},
  pages        = {258--259},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSCC.2010.5433948},
  doi          = {10.1109/ISSCC.2010.5433948},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/TsuchidaIFUSAKISIKKASYW10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/TakashimaSHMSHOTDFWFOKSYKHN10,
  author       = {Daisaburo Takashima and
                  Hidehiro Shiga and
                  Daisuke Hashimoto and
                  Tadashi Miyakawa and
                  Shinichiro Shiratake and
                  Katsuhiko Hoya and
                  Ryu Ogiwara and
                  Ryosuke Takizawa and
                  Ryosuke Doumae and
                  Ryo Fukuda and
                  Yohji Watanabe and
                  Shuso Fujii and
                  Tohru Ozaki and
                  Hiroyuki Kanaya and
                  Susumu Shuto and
                  Koji Yamakawa and
                  Iwao Kunishima and
                  Takeshi Hamamoto and
                  Akihiro Nitayama},
  title        = {A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
                  Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
                  2010},
  pages        = {262--263},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSCC.2010.5433950},
  doi          = {10.1109/ISSCC.2010.5433950},
  timestamp    = {Wed, 17 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/TakashimaSHMSHOTDFWFOKSYKHN10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF09,
  author       = {Hidehiro Shiga and
                  Daisaburo Takashima and
                  Shinichiro Shiratake and
                  Katsuhiko Hoya and
                  Tadashi Miyakawa and
                  Ryu Ogiwara and
                  Ryo Fukuda and
                  Ryosuke Takizawa and
                  Kosuke Hatsuda and
                  Fumiyoshi Matsuoka and
                  Yasushi Nagadomi and
                  Daisuke Hashimoto and
                  Hisaaki Nishimura and
                  Takeshi Hioka and
                  Sumiko M. Doumae and
                  Shoichi Shimizu and
                  Mitsumo Kawano and
                  Toyoki Taguchi and
                  Yohji Watanabe and
                  Shuso Fujii and
                  Tohru Ozaki and
                  Hiroyuki Kanaya and
                  Yoshinori Kumura and
                  Yoshiro Shimojo and
                  Yuki Yamada and
                  Yoshihiro Minami and
                  Susumu Shuto and
                  Koji Yamakawa and
                  Soichi Yamazaki and
                  Iwao Kunishima and
                  Takeshi Hamamoto and
                  Akihiro Nitayama and
                  Tohru Furuyama},
  title        = {A 1.6GB/s {DDR2} 128Mb chain FeRAM with scalable octal bitline and
                  sensing schemes},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
                  Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
                  2009},
  pages        = {464--465},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/ISSCC.2009.4977509},
  doi          = {10.1109/ISSCC.2009.4977509},
  timestamp    = {Fri, 15 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/KirihataWDWHYWF97,
  author       = {Toshiaki Kirihata and
                  Hing Wong and
                  John K. DeBrosse and
                  Yohji Watanabe and
                  Takahiko Hara and
                  Munehiro Yoshida and
                  Matthew R. Wordeman and
                  Shuso Fujii and
                  Yoshiaki Asao and
                  Bo Krsnik},
  title        = {Flexible test mode approach for 256-Mb {DRAM}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {32},
  number       = {10},
  pages        = {1525--1534},
  year         = {1997},
  url          = {https://doi.org/10.1109/4.634660},
  doi          = {10.1109/4.634660},
  timestamp    = {Thu, 07 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KirihataWDWHYWF97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/KirihataWWDYKFW96,
  author       = {Toshiaki Kirihata and
                  Yohji Watanabe and
                  Hing Wong and
                  John K. DeBrosse and
                  Munehiro Yoshida and
                  Daisuke Kato and
                  Shuso Fujii and
                  Matthew R. Wordeman and
                  Peter Poechmueller and
                  Stephen A. Parke and
                  Yoshiaki Asao},
  title        = {Fault-tolerant designs for 256 Mb {DRAM}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {31},
  number       = {4},
  pages        = {558--566},
  year         = {1996},
  url          = {https://doi.org/10.1109/4.499733},
  doi          = {10.1109/4.499733},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KirihataWWDYKFW96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/WatanabeWKKDRYM96,
  author       = {Yohji Watanabe and
                  Ring Wong and
                  Toshiaki Kirihata and
                  Daisuke Kato and
                  John K. DeBrosse and
                  Takahiko Rara and
                  Munehiro Yoshida and
                  Rideo Mukai and
                  Khandker N. Quader and
                  Takeshi Nagai and
                  Peter Poechmueller and
                  Peter Pfefferl and
                  Matthew R. Wordeman and
                  Shuso Fujii},
  title        = {A 286 mm\({}^{\mbox{2}}\) 256 Mb {DRAM} with {\texttimes}32 both-ends
                  {DQ}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {31},
  number       = {4},
  pages        = {567--574},
  year         = {1996},
  url          = {https://doi.org/10.1109/4.499734},
  doi          = {10.1109/4.499734},
  timestamp    = {Tue, 26 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/WatanabeWKKDRYM96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/WatanabeNW94,
  author       = {Yohji Watanabe and
                  Nobuo Nakamura and
                  Shigeyoshi Watanabe},
  title        = {Offset compensating bit-line sensing scheme for high density DRAM's},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {29},
  number       = {1},
  pages        = {9--13},
  year         = {1994},
  url          = {https://doi.org/10.1109/4.272089},
  doi          = {10.1109/4.272089},
  timestamp    = {Wed, 03 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/WatanabeNW94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.