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BibTeX records: V. Visvanathan
@article{DBLP:journals/jolpe/GalaDVK15, author = {Neel Gala and V. R. Devanathan and V. Visvanathan and V. Kamakoti}, title = {Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications}, journal = {J. Low Power Electron.}, volume = {11}, number = {2}, pages = {133--148}, year = {2015}, url = {https://doi.org/10.1166/jolpe.2015.1377}, doi = {10.1166/JOLPE.2015.1377}, timestamp = {Thu, 10 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jolpe/GalaDVK15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/GalaDSVK14, author = {Neel Gala and V. R. Devanathan and Karthik Srinivasan and V. Visvanathan and V. Kamakoti}, title = {ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs}, booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014, and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014}, pages = {342--347}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/VLSID.2014.65}, doi = {10.1109/VLSID.2014.65}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/GalaDSVK14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jolpe/GandhiDVPK13, author = {Virat Gandhi and V. R. Devanathan and V. Visvanathan and Milan Patnaik and V. Kamakoti}, title = {Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions}, journal = {J. Low Power Electron.}, volume = {9}, number = {2}, pages = {207--228}, year = {2013}, url = {https://doi.org/10.1166/jolpe.2013.1254}, doi = {10.1166/JOLPE.2013.1254}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jolpe/GandhiDVPK13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jolpe/PasumarthiDVPK12, author = {Rama Kumar Pasumarthi and V. R. Devanathan and V. Visvanathan and Seetal Potluri and V. Kamakoti}, title = {Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs}, journal = {J. Low Power Electron.}, volume = {8}, number = {5}, pages = {684--695}, year = {2012}, url = {https://doi.org/10.1166/jolpe.2012.1226}, doi = {10.1166/JOLPE.2012.1226}, timestamp = {Thu, 10 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jolpe/PasumarthiDVPK12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ViraraghavanAV10, author = {Janakiraman Viraraghavan and Bharadwaj Amrutur and V. Visvanathan}, title = {Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {29}, number = {7}, pages = {1056--1069}, year = {2010}, url = {https://doi.org/10.1109/TCAD.2010.2049059}, doi = {10.1109/TCAD.2010.2049059}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ViraraghavanAV10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jolpe/ViraraghavanAV08, author = {Janakiraman Viraraghavan and Bharadwaj Amrutur and V. Visvanathan}, title = {Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks}, journal = {J. Low Power Electron.}, volume = {4}, number = {3}, pages = {301--319}, year = {2008}, url = {https://doi.org/10.1166/jolpe.2008.187}, doi = {10.1166/JOLPE.2008.187}, timestamp = {Fri, 22 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jolpe/ViraraghavanAV08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cicc/DasAJAV08, author = {Bishnu Prasad Das and Bharadwaj Amrutur and H. S. Jamadagni and N. V. Arvind and V. Visvanathan}, title = {Within-die gate delay variability measurement using re-configurable ring oscillator}, booktitle = {Proceedings of the {IEEE} 2008 Custom Integrated Circuits Conference, {CICC} 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008}, pages = {133--136}, publisher = {{IEEE}}, year = {2008}, url = {https://doi.org/10.1109/CICC.2008.4672039}, doi = {10.1109/CICC.2008.4672039}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/cicc/DasAJAV08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/ChandrasekarVV05, author = {Sreeram Chandrasekar and Gaurav Kumar Varshney and V. Visvanathan}, title = {A Comprehensive Methodology for Noise Characterization of {ASIC} Cell Libraries}, booktitle = {6th International Symposium on Quality of Electronic Design {(ISQED} 2005), 21-23 March 2005, San Jose, CA, {USA}}, pages = {530--535}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ISQED.2005.4}, doi = {10.1109/ISQED.2005.4}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/ChandrasekarVV05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/ChandrasekarVV05, author = {Sreeram Chandrasekar and V. Visvanathan and Gaurav Kumar Varshney}, title = {Application of {DC} Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static {CMOS} Circuits}, booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India}, pages = {336--341}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ICVD.2005.55}, doi = {10.1109/ICVD.2005.55}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/ChandrasekarVV05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/SureshVKJ05, author = {B. Suresh and V. Visvanathan and R. S. Krishnan and H. S. Jamadagni}, title = {Application of Alpha Power Law Models to {PLL} Design Methodology}, booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India}, pages = {768--773}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ICVD.2005.54}, doi = {10.1109/ICVD.2005.54}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/SureshVKJ05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MandalV01, author = {Pradip Mandal and V. Visvanathan}, title = {{CMOS} op-amp sizing using a geometric programming formulation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {20}, number = {1}, pages = {22--38}, year = {2001}, url = {https://doi.org/10.1109/43.905672}, doi = {10.1109/43.905672}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MandalV01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/vlsisp/RamanathanNV00, author = {S. Ramanathan and S. K. Nandy and V. Visvanathan}, title = {Reconfigurable Filter Coprocessor Architecture for {DSP} Applications}, journal = {J. {VLSI} Signal Process.}, volume = {26}, number = {3}, pages = {333--359}, year = {2000}, url = {https://doi.org/10.1023/A:1026555400883}, doi = {10.1023/A:1026555400883}, timestamp = {Tue, 27 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/vlsisp/RamanathanNV00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/RamanathanV99, author = {S. Ramanathan and V. Visvanathan}, title = {Low-power pipelined {LMS} adaptive filter architectures with minimal adaptation delay1}, journal = {Integr.}, volume = {27}, number = {1}, pages = {1--32}, year = {1999}, url = {https://doi.org/10.1016/S0167-9260(98)00013-3}, doi = {10.1016/S0167-9260(98)00013-3}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/RamanathanV99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/RamanathanVN99, author = {S. Ramanathan and V. Visvanathan and S. K. Nandy}, title = {Synthesis of ASIPs for {DSP} algorithms}, journal = {Integr.}, volume = {28}, number = {1}, pages = {13--32}, year = {1999}, url = {https://doi.org/10.1016/S0167-9260(99)00009-7}, doi = {10.1016/S0167-9260(99)00009-7}, timestamp = {Tue, 27 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/integration/RamanathanVN99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/sigpro/RamanathanVN99, author = {S. Ramanathan and V. Visvanathan and S. K. Nandy}, title = {A computational engine for multirate {FIR} digital filtering}, journal = {Signal Process.}, volume = {79}, number = {2}, pages = {213--222}, year = {1999}, url = {https://doi.org/10.1016/S0165-1684(99)00095-X}, doi = {10.1016/S0165-1684(99)00095-X}, timestamp = {Tue, 27 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/sigpro/RamanathanVN99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/vlsisp/RamanathanVN99, author = {S. Ramanathan and V. Visvanathan and S. K. Nandy}, title = {Architectural Synthesis of Computational Engines for Subband Adaptive Filtering}, journal = {J. {VLSI} Signal Process.}, volume = {22}, number = {3}, pages = {173--195}, year = {1999}, url = {https://doi.org/10.1023/A:1008177205744}, doi = {10.1023/A:1008177205744}, timestamp = {Tue, 27 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/vlsisp/RamanathanVN99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/GautamVN99, author = {Avinash K. Gautam and V. Visvanathan and S. K. Nandy}, title = {Automatic Generation of Tree Multipliers Using Placement-Driven Netlists}, booktitle = {Proceedings of the {IEEE} International Conference On Computer Design, {VLSI} in Computers and Processors, {ICCD} '99, Austin, Texas, USA, October 10-13, 1999}, pages = {285--288}, publisher = {{IEEE} Computer Society}, year = {1999}, url = {https://doi.org/10.1109/ICCD.1999.808440}, doi = {10.1109/ICCD.1999.808440}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/GautamVN99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/MandalV99, author = {Pradip Mandal and V. Visvanathan}, title = {A New Approach for {CMOS} Op-Amp Synthesis}, booktitle = {12th International Conference on {VLSI} Design {(VLSI} Design 1999), 10-13 January 1999, Goa, India}, pages = {189--195}, publisher = {{IEEE} Computer Society}, year = {1999}, url = {https://doi.org/10.1109/ICVD.1999.745147}, doi = {10.1109/ICVD.1999.745147}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/MandalV99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/RamanathanVN99, author = {S. Ramanathan and V. Visvanathan and S. K. Nandy}, title = {Synthesis of Configurable Architectures for {DSP} Algorithms}, booktitle = {12th International Conference on {VLSI} Design {(VLSI} Design 1999), 10-13 January 1999, Goa, India}, pages = {350--357}, publisher = {{IEEE} Computer Society}, year = {1999}, url = {https://doi.org/10.1109/ICVD.1999.745181}, doi = {10.1109/ICVD.1999.745181}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/RamanathanVN99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/RamanathanV97, author = {S. Ramanathan and V. Visvanathan}, title = {Low-Power Configurable Processor Array for {DLMS} Adaptive Filtering}, booktitle = {10th International Conference on {VLSI} Design {(VLSI} Design 1997), 4-7 January 1997, Hyderabad, India}, pages = {198--207}, publisher = {{IEEE} Computer Society}, year = {1997}, url = {https://doi.org/10.1109/ICVD.1997.568076}, doi = {10.1109/ICVD.1997.568076}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/RamanathanV97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/MandalV97, author = {Pradip Mandal and V. Visvanathan}, title = {A Self-Biased High Performance Folded Cascode {CMOS} Op-Amp}, booktitle = {10th International Conference on {VLSI} Design {(VLSI} Design 1997), 4-7 January 1997, Hyderabad, India}, pages = {429--434}, publisher = {{IEEE} Computer Society}, year = {1997}, url = {https://doi.org/10.1109/ICVD.1997.568171}, doi = {10.1109/ICVD.1997.568171}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/MandalV97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/GuptaV96, author = {A. Ratan Gupta and V. Visvanathan}, title = {{VLSI} Implementation of {DSP} Architectures}, booktitle = {9th International Conference on {VLSI} Design {(VLSI} Design 1996), 3-6 January 1996, Bangalore, India}, pages = {3}, publisher = {{IEEE} Computer Society}, year = {1996}, url = {https://doi.ieeecomputersociety.org/10.1109/VLSID.1996.10006}, doi = {10.1109/VLSID.1996.10006}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/GuptaV96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/MandalV96, author = {Pradip Mandal and V. Visvanathan}, title = {Design of high performance two stage {CMOS} cascode op-amps with stable biasing}, booktitle = {9th International Conference on {VLSI} Design {(VLSI} Design 1996), 3-6 January 1996, Bangalore, India}, pages = {234--237}, publisher = {{IEEE} Computer Society}, year = {1996}, url = {https://doi.org/10.1109/ICVD.1996.489491}, doi = {10.1109/ICVD.1996.489491}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/MandalV96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/RamanathanV96, author = {S. Ramanathan and V. Visvanathan}, title = {A systolic architecture for {LMS} adaptive filtering with minimal adaptation delay}, booktitle = {9th International Conference on {VLSI} Design {(VLSI} Design 1996), 3-6 January 1996, Bangalore, India}, pages = {286--289}, publisher = {{IEEE} Computer Society}, year = {1996}, url = {https://doi.org/10.1109/ICVD.1996.489612}, doi = {10.1109/ICVD.1996.489612}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/RamanathanV96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/VisvanathanR95, author = {V. Visvanathan and S. Ramanathan}, title = {A modular systolic architecture for delayed least mean squares adaptive filtering}, booktitle = {8th International Conference on {VLSI} Design {(VLSI} Design 1995), 4-7 January 1995, New Delhi, India}, pages = {332--337}, publisher = {{IEEE} Computer Society}, year = {1995}, url = {https://doi.org/10.1109/ICVD.1995.512134}, doi = {10.1109/ICVD.1995.512134}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/VisvanathanR95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/GiriVNG94, author = {Abhijit Giri and V. Visvanathan and S. K. Nandy and S. K. Ghoshal}, title = {High Speed Digital Filtering on SRAM-Based FPGAs}, booktitle = {Proceedings of the Seventh International Conference on {VLSI} Design, {VLSI} Design 1994, Calcutta, India, January 5-8, 1994}, pages = {229--232}, publisher = {{IEEE} Computer Society}, year = {1994}, url = {https://doi.org/10.1109/ICVD.1994.282691}, doi = {10.1109/ICVD.1994.282691}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/GiriVNG94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/AnuradhaV94, author = {V. K. Anuradha and V. Visvanathan}, title = {A {CORDIC} Based Programmable {DXT} Processor Array}, booktitle = {Proceedings of the Seventh International Conference on {VLSI} Design, {VLSI} Design 1994, Calcutta, India, January 5-8, 1994}, pages = {343--348}, publisher = {{IEEE} Computer Society}, year = {1994}, url = {https://doi.org/10.1109/ICVD.1994.282716}, doi = {10.1109/ICVD.1994.282716}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/AnuradhaV94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/SomasekharV93, author = {Dinesh Somasekhar and V. Visvanathan}, title = {A 230-MHz half-bit level pipelined multiplier using true single-phase clocking}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {1}, number = {4}, pages = {415--422}, year = {1993}, url = {https://doi.org/10.1109/92.250188}, doi = {10.1109/92.250188}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/SomasekharV93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/MandalV93, author = {Pradip Mandal and V. Visvanathan}, editor = {Michael R. Lightner and Jochen A. G. Jess}, title = {Macromodeling of the {A.C.} characteristics of {CMOS} Op-amps}, booktitle = {Proceedings of the 1993 {IEEE/ACM} International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993}, pages = {334--340}, publisher = {{IEEE} Computer Society / {ACM}}, year = {1993}, url = {https://doi.org/10.1109/ICCAD.1993.580078}, doi = {10.1109/ICCAD.1993.580078}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/MandalV93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/icpp/EswarSHV93, author = {Kalluri Eswar and P. Sadayappan and Chua{-}Huang Huang and V. Visvanathan}, editor = {Salim Hariri and P. Bruce Berra}, title = {Supernodal Sparse Cholesky Facotrization on Distributed-Memory Multiprocessors}, booktitle = {Proceedings of the 1993 International Conference on Parallel Processing, Syracuse University, NY, USA, August 16-20, 1993. Volume {III:} Algorithms {\&} Applications}, pages = {18--22}, publisher = {{CRC} Press}, year = {1993}, url = {https://doi.org/10.1109/ICPP.1993.170}, doi = {10.1109/ICPP.1993.170}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/icpp/EswarSHV93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/icpp/NandyNVSC93, author = {S. K. Nandy and Ranjani Narayan and V. Visvanathan and P. Sadayappan and Prashant S. Chauhan}, editor = {Salim Hariri and P. Bruce Berra}, title = {A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded {VLSI} Processor Array}, booktitle = {Proceedings of the 1993 International Conference on Parallel Processing, Syracuse University, NY, USA, August 16-20, 1993. Volume {III:} Algorithms {\&} Applications}, pages = {94--97}, publisher = {{CRC} Press}, year = {1993}, url = {https://doi.org/10.1109/ICPP.1993.30}, doi = {10.1109/ICPP.1993.30}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/icpp/NandyNVSC93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/VisvanathanMR93, author = {V. Visvanathan and Nibedita Mohanty and S. Ramanathan}, title = {An Area-Efficient Systolic Architecture for Real-Time {VLSI} Finite Impulse Response Filters}, booktitle = {Proceedings of the Sixth International Conference on {VLSI} Design, {VLSI} Design 1993, Bombay, India, January 3-6, 1993}, pages = {166--171}, publisher = {{IEEE} Computer Society}, year = {1993}, url = {https://doi.org/10.1109/ICVD.1993.669671}, doi = {10.1109/ICVD.1993.669671}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/VisvanathanMR93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/RamanathanMV93, author = {S. Ramanathan and Nibedita Mohanty and V. Visvanathan}, title = {A Methodology for Generating Application Specific Tree Multipliers}, booktitle = {Proceedings of the Sixth International Conference on {VLSI} Design, {VLSI} Design 1993, Bombay, India, January 3-6, 1993}, pages = {176--179}, publisher = {{IEEE} Computer Society}, year = {1993}, url = {https://doi.org/10.1109/ICVD.1993.669673}, doi = {10.1109/ICVD.1993.669673}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/RamanathanMV93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/GhoshNPV93, author = {Debabrata Ghosh and S. K. Nandy and K. Parthasarathy and V. Visvanathan}, title = {{NPCPL:} Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs}, booktitle = {Proceedings of the Sixth International Conference on {VLSI} Design, {VLSI} Design 1993, Bombay, India, January 3-6, 1993}, pages = {341--346}, publisher = {{IEEE} Computer Society}, year = {1993}, url = {https://doi.org/10.1109/ICVD.1993.669707}, doi = {10.1109/ICVD.1993.669707}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/GhoshNPV93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/SomasekharV93, author = {Dinesh Somasekhar and V. Visvanathan}, title = {A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking}, booktitle = {Proceedings of the Sixth International Conference on {VLSI} Design, {VLSI} Design 1993, Bombay, India, January 3-6, 1993}, pages = {347--350}, publisher = {{IEEE} Computer Society}, year = {1993}, url = {https://doi.org/10.1109/ICVD.1993.669708}, doi = {10.1109/ICVD.1993.669708}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/SomasekharV93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/icpp/EswarSV91, author = {Kalluri Eswar and P. Sadayappan and V. Visvanathan}, title = {Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors}, booktitle = {Proceedings of the International Conference on Parallel Processing, {ICPP} '91, Austin, Texas, USA, August 1991. Volume {III:} Algorithms and Applications}, pages = {159--166}, publisher = {{CRC} Press}, year = {1991}, timestamp = {Mon, 28 Jul 2014 17:06:01 +0200}, biburl = {https://dblp.org/rec/conf/icpp/EswarSV91.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MilorV89, author = {Linda S. Milor and V. Visvanathan}, title = {Detection of catastrophic faults in analog integrated circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {8}, number = {2}, pages = {114--130}, year = {1989}, url = {https://doi.org/10.1109/43.21830}, doi = {10.1109/43.21830}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/MilorV89.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SadayappanV89, author = {P. Sadayappan and V. Visvanathan}, title = {Efficient sparse matrix factorization for circuit simulation on vector supercomputers}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {8}, number = {12}, pages = {1276--1285}, year = {1989}, url = {https://doi.org/10.1109/43.44508}, doi = {10.1109/43.44508}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SadayappanV89.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/SadayappanV89, author = {P. Sadayappan and V. Visvanathan}, editor = {Donald E. Thomas}, title = {Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers}, booktitle = {Proceedings of the 26th {ACM/IEEE} Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989}, pages = {13--18}, publisher = {{ACM} Press}, year = {1989}, url = {https://doi.org/10.1145/74382.74386}, doi = {10.1145/74382.74386}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/SadayappanV89.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/NgV89, author = {Antony P.{-}C. Ng and V. Visvanathan}, editor = {Donald E. Thomas}, title = {A Framework for Scheduling Multi-Rate Circuit Simulation}, booktitle = {Proceedings of the 26th {ACM/IEEE} Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989}, pages = {19--24}, publisher = {{ACM} Press}, year = {1989}, url = {https://doi.org/10.1145/74382.74387}, doi = {10.1145/74382.74387}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/NgV89.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/SadayappanV88, author = {P. Sadayappan and V. Visvanathan}, title = {Circuit Simulation on Shared-Memory Multiprocessors}, journal = {{IEEE} Trans. Computers}, volume = {37}, number = {12}, pages = {1634--1642}, year = {1988}, url = {https://doi.org/10.1109/12.9740}, doi = {10.1109/12.9740}, timestamp = {Tue, 16 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/SadayappanV88.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/SadayappanV88, author = {P. Sadayappan and V. Visvanathan}, title = {Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization}, booktitle = {Computer Design: {VLSI} in Computers and Processors, {ICCD} 1988., Proceedings of the 1988 {IEEE} International Conference on, Rye Brook, NY, USA, October 3-5, 1988}, pages = {32--35}, publisher = {{IEEE}}, year = {1988}, url = {https://doi.org/10.1109/ICCD.1988.25653}, doi = {10.1109/ICCD.1988.25653}, timestamp = {Mon, 09 Aug 2021 14:54:02 +0200}, biburl = {https://dblp.org/rec/conf/iccd/SadayappanV88.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ics/SadayappanV88, author = {P. Sadayappan and V. Visvanathan}, editor = {Jacques Lenfant}, title = {Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor}, booktitle = {Proceedings of the 2nd international conference on Supercomputing, {ICS} 1988, Saint Malo, France, July 4-8, 1988}, pages = {254--265}, publisher = {{ACM}}, year = {1988}, url = {https://doi.org/10.1145/55364.55389}, doi = {10.1145/55364.55389}, timestamp = {Tue, 06 Nov 2018 11:07:02 +0100}, biburl = {https://dblp.org/rec/conf/ics/SadayappanV88.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/compgeom/VisvanathanM86, author = {V. Visvanathan and Linda S. Milor}, editor = {Alok Aggarwal}, title = {An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation}, booktitle = {Proceedings of the Second Annual {ACM} {SIGACT/SIGGRAPH} Symposium on Computational Geometry, Yorktown Heights, NY, USA, June 2-4, 1986}, pages = {207--215}, publisher = {{ACM}}, year = {1986}, url = {https://doi.org/10.1145/10515.10538}, doi = {10.1145/10515.10538}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/compgeom/VisvanathanM86.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/VisvanathanS84, author = {V. Visvanathan and Alberto L. Sangiovanni{-}Vincentelli}, title = {A Computational Approach for the Diagnosability of Dynamical Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {3}, number = {3}, pages = {165--171}, year = {1984}, url = {https://doi.org/10.1109/TCAD.1984.1270071}, doi = {10.1109/TCAD.1984.1270071}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/VisvanathanS84.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/VisvanathanS81, author = {V. Visvanathan and Alberto L. Sangiovanni{-}Vincentelli}, title = {Diagnosability of Nonlinear Circuits and Systems - Part {I:} The dc Case}, journal = {{IEEE} Trans. Computers}, volume = {30}, number = {11}, pages = {889--898}, year = {1981}, url = {https://doi.org/10.1109/TC.1981.1675720}, doi = {10.1109/TC.1981.1675720}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/VisvanathanS81.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/SaeksSV81, author = {Richard Saeks and Alberto L. Sangiovanni{-}Vincentelli and V. Visvanathan}, title = {Diagnosability of Nonlinear Circuits and Systems - Part {II:} Dynamical Systems}, journal = {{IEEE} Trans. Computers}, volume = {30}, number = {11}, pages = {899--904}, year = {1981}, url = {https://doi.org/10.1109/TC.1981.1675721}, doi = {10.1109/TC.1981.1675721}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/SaeksSV81.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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