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ORCIDBibTeX records: Xavier Vera
@inproceedings{DBLP:conf/hotchips/Vera20,
author = {Xavier Vera},
title = {Inside Tiger Lake: Intel's Next Generation Mobile Client {CPU}},
booktitle = {{IEEE} Hot Chips 32 Symposium, {HCS} 2020, Palo Alto, CA, USA, August
16-18, 2020},
pages = {1--26},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/HCS49909.2020.9220443},
doi = {10.1109/HCS49909.2020.9220443},
timestamp = {Tue, 20 Oct 2020 15:27:17 +0200},
biburl = {https://dblp.org/rec/conf/hotchips/Vera20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/UpasaniVG16,
author = {Gaurang Upasani and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {A Case for Acoustic Wave Detectors for Soft-Errors},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {1},
pages = {5--18},
year = {2016},
url = {https://doi.org/10.1109/TC.2015.2419652},
doi = {10.1109/TC.2015.2419652},
timestamp = {Wed, 14 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/UpasaniVG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/UpasaniVG14,
author = {Gaurang Upasani and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {Framework for economical error recovery in embedded cores},
booktitle = {2014 {IEEE} 20th International On-Line Testing Symposium, {IOLTS}
2014, Platja d'Aro, Girona, Spain, July 7-9, 2014},
pages = {146--153},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/IOLTS.2014.6873687},
doi = {10.1109/IOLTS.2014.6873687},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/iolts/UpasaniVG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/UpasaniVG14,
author = {Gaurang Upasani and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {Avoiding core's {DUE} {\&} {SDC} via acoustic wave detectors and
tailored error containment and recovery},
booktitle = {{ACM/IEEE} 41st International Symposium on Computer Architecture,
{ISCA} 2014, Minneapolis, MN, USA, June 14-18, 2014},
pages = {37--48},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISCA.2014.6853200},
doi = {10.1109/ISCA.2014.6853200},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/UpasaniVG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/CarreteroHMRV13,
author = {Javier Carretero and
Enric Herrero and
Matteo Monchiero and
Tanaus{\'{u}} Ram{\'{\i}}rez and
Xavier Vera},
editor = {Enrico Macii},
title = {Capturing vulnerability variations for register files},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1468--1473},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.299},
doi = {10.7873/DATE.2013.299},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/CarreteroHMRV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/UpasaniVG13,
author = {Gaurang Upasani and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {Reducing {DUE-FIT} of caches by exploiting acoustic wave detectors
for error recovery},
booktitle = {2013 {IEEE} 19th International On-Line Testing Symposium (IOLTS),
Chania, Crete, Greece, July 8-10, 2013},
pages = {85--91},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/IOLTS.2013.6604056},
doi = {10.1109/IOLTS.2013.6604056},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/iolts/UpasaniVG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/FoutrisGVG13,
author = {Nikos Foutris and
Dimitris Gizopoulos and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
editor = {Avi Mendelson},
title = {Deconfigurable microprocessor architectures for silicon debug acceleration},
booktitle = {The 40th Annual International Symposium on Computer Architecture,
ISCA'13, Tel-Aviv, Israel, June 23-27, 2013},
pages = {631--642},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2485922.2485976},
doi = {10.1145/2485922.2485976},
timestamp = {Fri, 09 Jul 2021 15:51:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/FoutrisGVG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/UpasaniVG12,
author = {Gaurang Upasani and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {Setting an error detection infrastructure with low cost acoustic wave
detectors},
booktitle = {39th International Symposium on Computer Architecture {(ISCA} 2012),
June 9-13, 2012, Portland, OR, {USA}},
pages = {333--343},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISCA.2012.6237029},
doi = {10.1109/ISCA.2012.6237029},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/UpasaniVG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/CarreteroCVAG11,
author = {Javier Carretero and
Pedro Chaparro and
Xavier Vera and
Jaume Abella and
Antonio Gonz{\'{a}}lez},
title = {Implementing End-to-End Register Data-Flow Continuous Self-Test},
journal = {{IEEE} Trans. Computers},
volume = {60},
number = {8},
pages = {1194--1206},
year = {2011},
url = {https://doi.org/10.1109/TC.2010.179},
doi = {10.1109/TC.2010.179},
timestamp = {Tue, 18 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/CarreteroCVAG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GizopoulosPARHSMBV11,
author = {Dimitris Gizopoulos and
Mihalis Psarakis and
Sarita V. Adve and
Pradeep Ramachandran and
Siva Kumar Sastry Hari and
Daniel J. Sorin and
Albert Meixner and
Arijit Biswas and
Xavier Vera},
title = {Architectures for online error detection and recovery in multicore
processors},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {533--538},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763096},
doi = {10.1109/DATE.2011.5763096},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GizopoulosPARHSMBV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/CarreteroAVC11,
author = {Javier Carretero and
Jaume Abella and
Xavier Vera and
Pedro Chaparro},
title = {Control-Flow Recovery Validation Using Microarchitectural Invariants},
booktitle = {2011 {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2011, Vancouver, BC, Canada,
October 3-5, 2011},
pages = {209--216},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/DFT.2011.32},
doi = {10.1109/DFT.2011.32},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/CarreteroAVC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/CarreteroVARMG11,
author = {Javier Carretero and
Xavier Vera and
Jaume Abella and
Tanaus{\'{u}} Ram{\'{\i}}rez and
Matteo Monchiero and
Antonio Gonz{\'{a}}lez},
title = {Hardware/software-based diagnosis of load-store queues using expandable
activity logs},
booktitle = {17th International Conference on High-Performance Computer Architecture
{(HPCA-17} 2011), February 12-16 2011, San Antonio, Texas, {USA}},
pages = {321--331},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/HPCA.2011.5749740},
doi = {10.1109/HPCA.2011.5749740},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpca/CarreteroVARMG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/AymerichABCCFGHMMPRRVVWZ11,
author = {Nivard Aymerich and
A. Asenov and
Andrew R. Brown and
Ramon Canal and
Binjie Cheng and
Joan Figueras and
Antonio Gonz{\'{a}}lez and
Enric Herrero and
S. Markov and
Miguel Miranda and
Peyman Pouyan and
Tanaus{\'{u}} Ram{\'{\i}}rez and
Antonio Rubio and
Elena I. Vatajelu and
Xavier Vera and
Xingsheng Wang and
Paul Zuber},
title = {New reliability mechanisms in memory design for sub-22nm technologies},
booktitle = {17th {IEEE} International On-Line Testing Symposium {(IOLTS} 2011),
13-15 July, 2011, Athens, Greece},
pages = {111--114},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/IOLTS.2011.5993820},
doi = {10.1109/IOLTS.2011.5993820},
timestamp = {Tue, 11 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iolts/AymerichABCCFGHMMPRRVVWZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/FoutrisGPVG11,
author = {Nikos Foutris and
Dimitris Gizopoulos and
Mihalis Psarakis and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
editor = {Carlo Galuzzi and
Luigi Carro and
Andreas Moshovos and
Milos Prvulovic},
title = {Accelerating microprocessor silicon validation by exposing {ISA} diversity},
booktitle = {44rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
{MICRO} 2011, Porto Alegre, Brazil, December 3-7, 2011},
pages = {386--397},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2155620.2155666},
doi = {10.1145/2155620.2155666},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/FoutrisGPVG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/PonsMRAVG11,
author = {Marc Pons and
Francesc Moll and
Antonio Rubio and
Jaume Abella and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {Design of complex circuits using the Via-Configurable transistor array
regular layout fabric},
booktitle = {{IEEE} 24th International SoC Conference, {SOCC} 2011, Taipei, Taiwan,
September 26-28, 2011},
pages = {166--169},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/SOCC.2011.6085126},
doi = {10.1109/SOCC.2011.6085126},
timestamp = {Thu, 06 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/PonsMRAVG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:journals/procedia/CanalRABMZGV11,
author = {Ramon Canal and
Antonio Rubio and
A. Asenov and
A. Brown and
Miguel Miranda and
Paul Zuber and
Antonio Gonz{\'{a}}lez and
Xavier Vera},
editor = {Elisabeth Giacobino and
Rolf Pfeifer},
title = {{TRAMS} Project: Variability and Reliability of {SRAM} Memories in
sub-22 nm Bulk-CMOS Technologies},
booktitle = {Proceedings of the 2nd European Future Technologies Conference and
Exhibition, {FET} 2011, Budapest, Hungary, May 4-6, 2011},
series = {Procedia Computer Science},
volume = {7},
pages = {148--149},
publisher = {Elsevier},
year = {2011},
url = {https://doi.org/10.1016/j.procs.2011.09.010},
doi = {10.1016/J.PROCS.2011.09.010},
timestamp = {Thu, 06 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/procedia/CanalRABMZGV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/csur/AbellaV10,
author = {Jaume Abella and
Xavier Vera},
title = {Electromigration for microarchitects},
journal = {{ACM} Comput. Surv.},
volume = {42},
number = {2},
pages = {9:1--9:18},
year = {2010},
url = {https://doi.org/10.1145/1667062.1667066},
doi = {10.1145/1667062.1667066},
timestamp = {Tue, 18 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/csur/AbellaV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/CarreteroVCA10,
author = {Javier Carretero and
Xavier Vera and
Pedro Chaparro and
Jaume Abella},
title = {Microarchitectural Online Testing for Failure Detection in Memory
Order Buffers},
journal = {{IEEE} Trans. Computers},
volume = {59},
number = {5},
pages = {623--637},
year = {2010},
url = {https://doi.org/10.1109/TC.2009.139},
doi = {10.1109/TC.2009.139},
timestamp = {Tue, 18 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/CarreteroVCA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/AbellaCCV10,
author = {Jaume Abella and
Javier Carretero and
Pedro Chaparro and
Xavier Vera},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {The split register file},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {945--948},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5456914},
doi = {10.1109/DATE.2010.5456914},
timestamp = {Wed, 19 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/AbellaCCV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/AbellaCVCG10,
author = {Jaume Abella and
Pedro Chaparro and
Xavier Vera and
Javier Carretero and
Antonio Gonz{\'{a}}lez},
editor = {Matthew T. Jacob and
Chita R. Das and
Pradip Bose},
title = {High-Performance low-vcc in-order core},
booktitle = {16th International Conference on High-Performance Computer Architecture
{(HPCA-16} 2010), 9-14 January 2010, Bangalore, India},
pages = {1--11},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HPCA.2010.5416630},
doi = {10.1109/HPCA.2010.5416630},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpca/AbellaCVCG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/FoutrisPGAVG10,
author = {Nikos Foutris and
Mihalis Psarakis and
Dimitris Gizopoulos and
Andreas Apostolakis and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
editor = {Ron Press and
Erik H. Volkerink},
title = {{MT-SBST:} Self-test optimization in multithreaded multicore architectures},
booktitle = {2011 {IEEE} International Test Conference, {ITC} 2010, Austin, TX,
USA, November 2-4, 2010},
pages = {734--743},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/TEST.2010.5699277},
doi = {10.1109/TEST.2010.5699277},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/FoutrisPGAVG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PonsMRAVG10,
author = {Marc Pons and
Francesc Moll and
Antonio Rubio and
Jaume Abella and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {{VCTA:} {A} Via-Configurable Transistor Array regular fabric},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {335--340},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642683},
doi = {10.1109/VLSISOC.2010.5642683},
timestamp = {Tue, 11 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PonsMRAVG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tdsc/ErginUVG09,
author = {Oguz Ergin and
Osman S. Unsal and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {Reducing Soft Errors through Operand Width Aware Policies},
journal = {{IEEE} Trans. Dependable Secur. Comput.},
volume = {6},
number = {3},
pages = {217--230},
year = {2009},
url = {https://doi.org/10.1109/TDSC.2008.18},
doi = {10.1109/TDSC.2008.18},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tdsc/ErginUVG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tocs/VeraACG09,
author = {Xavier Vera and
Jaume Abella and
Javier Carretero and
Antonio Gonz{\'{a}}lez},
title = {Selective replication: {A} lightweight technique for soft errors},
journal = {{ACM} Trans. Comput. Syst.},
volume = {27},
number = {4},
pages = {8:1--8:30},
year = {2009},
url = {https://doi.org/10.1145/1658357.1658359},
doi = {10.1145/1658357.1658359},
timestamp = {Tue, 18 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tocs/VeraACG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/VeraACCG09,
author = {Xavier Vera and
Jaume Abella and
Javier Carretero and
Pedro Chaparro and
Antonio Gonz{\'{a}}lez},
title = {Online error detection and correction of erratic bits in register
files},
booktitle = {15th {IEEE} International On-Line Testing Symposium {(IOLTS} 2009),
24-26 June 2009, Sesimbra-Lisbon, Portugal},
pages = {81--86},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/IOLTS.2009.5195987},
doi = {10.1109/IOLTS.2009.5195987},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/VeraACCG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/Vera09,
author = {Xavier Vera},
title = {DFx for massively multiprocessors},
booktitle = {15th {IEEE} International On-Line Testing Symposium {(IOLTS} 2009),
24-26 June 2009, Sesimbra-Lisbon, Portugal},
pages = {153},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/IOLTS.2009.5195998},
doi = {10.1109/IOLTS.2009.5195998},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/Vera09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/CarreteroCVAG09,
author = {Javier Carretero and
Pedro Chaparro and
Xavier Vera and
Jaume Abella and
Antonio Gonz{\'{a}}lez},
editor = {Stephen W. Keckler and
Luiz Andr{\'{e}} Barroso},
title = {End-to-end register data-flow continuous self-test},
booktitle = {36th International Symposium on Computer Architecture {(ISCA} 2009),
June 20-24, 2009, Austin, TX, {USA}},
pages = {105--115},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1555754.1555770},
doi = {10.1145/1555754.1555770},
timestamp = {Fri, 09 Jul 2021 15:51:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/CarreteroCVAG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/AbellaCCVG09,
author = {Jaume Abella and
Javier Carretero and
Pedro Chaparro and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
editor = {David H. Albonesi and
Margaret Martonosi and
David I. August and
Jos{\'{e}} F. Mart{\'{\i}}nez},
title = {Low Vccmin fault-tolerant cache with highly predictable performance},
booktitle = {42st Annual {IEEE/ACM} International Symposium on Microarchitecture
{(MICRO-42} 2009), December 12-16, 2009, New York, New York, {USA}},
pages = {111--121},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1669112.1669128},
doi = {10.1145/1669112.1669128},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/AbellaCCVG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/AbellaVUEGT08,
author = {Jaume Abella and
Xavier Vera and
Osman S. Unsal and
Oguz Ergin and
Antonio Gonz{\'{a}}lez and
James W. Tschanz},
title = {Refueling: Preventing Wire Degradation due to Electromigration},
journal = {{IEEE} Micro},
volume = {28},
number = {6},
pages = {37--46},
year = {2008},
url = {https://doi.org/10.1109/MM.2008.92},
doi = {10.1109/MM.2008.92},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/AbellaVUEGT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ChaparroACV08,
author = {Pedro Chaparro and
Jaume Abella and
Javier Carretero and
Xavier Vera},
title = {Issue system protection mechanisms},
booktitle = {26th International Conference on Computer Design, {ICCD} 2008, 12-15
October 2008, Lake Tahoe, CA, USA, Proceedings},
pages = {599--604},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCD.2008.4751922},
doi = {10.1109/ICCD.2008.4751922},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ChaparroACV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/AbellaCVCG08,
author = {Jaume Abella and
Pedro Chaparro and
Xavier Vera and
Javier Carretero and
Antonio Gonz{\'{a}}lez},
title = {On-Line Failure Detection and Confinement in Caches},
booktitle = {14th {IEEE} International On-Line Testing Symposium {(IOLTS} 2008),
7-9 July 2008, Rhodes, Greece},
pages = {3--9},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/IOLTS.2008.15},
doi = {10.1109/IOLTS.2008.15},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/AbellaCVCG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/CarreteroVCA08,
author = {Javier Carretero and
Xavier Vera and
Pedro Chaparro and
Jaume Abella},
editor = {Douglas Young and
Nur A. Touba},
title = {On-line Failure Detection in Memory Order Buffers},
booktitle = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara,
California, USA, October 26-31, 2008},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/TEST.2008.4700582},
doi = {10.1109/TEST.2008.4700582},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/CarreteroVCA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/VeraLX07,
author = {Xavier Vera and
Bj{\"{o}}rn Lisper and
Jingling Xue},
title = {Data cache locking for tight timing calculations},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {7},
number = {1},
pages = {4:1--4:38},
year = {2007},
url = {https://doi.org/10.1145/1324969.1324973},
doi = {10.1145/1324969.1324973},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tecs/VeraLX07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/AbellaVUEG07,
author = {Jaume Abella and
Xavier Vera and
Osman S. Unsal and
Oguz Ergin and
Antonio Gonz{\'{a}}lez},
title = {Fuse: {A} Technique to Anticipate Failures due to Degradation in ALUs},
booktitle = {13th {IEEE} International On-Line Testing Symposium {(IOLTS} 2007),
8-11 July 2007, Heraklion, Crete, Greece},
pages = {15--22},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/IOLTS.2007.34},
doi = {10.1109/IOLTS.2007.34},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/AbellaVUEG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/VeraA07,
author = {Xavier Vera and
Jaume Abella},
title = {Surviving to Errors in Multi-Core Environments},
booktitle = {13th {IEEE} International On-Line Testing Symposium {(IOLTS} 2007),
8-11 July 2007, Heraklion, Crete, Greece},
pages = {260},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/IOLTS.2007.65},
doi = {10.1109/IOLTS.2007.65},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/VeraA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/AbellaVG07,
author = {Jaume Abella and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {Penelope: The NBTI-Aware Processor},
booktitle = {40th Annual {IEEE/ACM} International Symposium on Microarchitecture
{(MICRO-40} 2007), 1-5 December 2007, Chicago, Illinois, {USA}},
pages = {85--96},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/MICRO.2007.11},
doi = {10.1109/MICRO.2007.11},
timestamp = {Tue, 31 May 2022 14:39:58 +0200},
biburl = {https://dblp.org/rec/conf/micro/AbellaVG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/ErginUVG06,
author = {Oguz Ergin and
Osman S. Unsal and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {Exploiting Narrow Values for Soft Error Tolerance},
journal = {{IEEE} Comput. Archit. Lett.},
volume = {5},
number = {2},
year = {2006},
url = {https://doi.org/10.1109/L-CA.2006.12},
doi = {10.1109/L-CA.2006.12},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cal/ErginUVG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/UnsalTBDVGE06,
author = {Osman S. Unsal and
James W. Tschanz and
Keith A. Bowman and
Vivek De and
Xavier Vera and
Antonio Gonz{\'{a}}lez and
Oguz Ergin},
title = {Impact of Parameter Variations on Circuits and Microarchitecture},
journal = {{IEEE} Micro},
volume = {26},
number = {6},
pages = {30--39},
year = {2006},
url = {https://doi.org/10.1109/MM.2006.122},
doi = {10.1109/MM.2006.122},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/UnsalTBDVGE06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/UnsalEVG06,
author = {Osman S. Unsal and
Oguz Ergin and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {Empowering a helper cluster through data-width aware instruction selection
policies},
booktitle = {20th International Parallel and Distributed Processing Symposium {(IPDPS}
2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/IPDPS.2006.1639350},
doi = {10.1109/IPDPS.2006.1639350},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/UnsalEVG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/AbellaGVO05,
author = {Jaume Abella and
Antonio Gonz{\'{a}}lez and
Xavier Vera and
Michael F. P. O'Boyle},
title = {{IATAC:} a smart predictor to turn-off {L2} cache lines},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {2},
number = {1},
pages = {55--77},
year = {2005},
url = {https://doi.org/10.1145/1061267.1061271},
doi = {10.1145/1061267.1061271},
timestamp = {Tue, 18 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/AbellaGVO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/toplas/VeraALG05,
author = {Xavier Vera and
Jaume Abella and
Josep Llosa and
Antonio Gonz{\'{a}}lez},
title = {An accurate cost model for guiding data locality transformations},
journal = {{ACM} Trans. Program. Lang. Syst.},
volume = {27},
number = {5},
pages = {946--987},
year = {2005},
url = {https://doi.org/10.1145/1086642.1086646},
doi = {10.1145/1086642.1086646},
timestamp = {Tue, 18 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/toplas/VeraALG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/GibertASVG05,
author = {Enric Gibert and
Jaume Abella and
F. Jes{\'{u}}s S{\'{a}}nchez and
Xavier Vera and
Antonio Gonz{\'{a}}lez},
title = {Variable-Based Multi-module Data Caches for Clustered {VLIW} Processors},
booktitle = {14th International Conference on Parallel Architectures and Compilation
Techniques {(PACT} 2005), 17-21 September 2005, St. Louis, MO, {USA}},
pages = {207--217},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/PACT.2005.40},
doi = {10.1109/PACT.2005.40},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/IEEEpact/GibertASVG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/XueV04,
author = {Jingling Xue and
Xavier Vera},
title = {Efficient and Accurate Analytical Modeling of Whole-Program Data Cache
Behavior},
journal = {{IEEE} Trans. Computers},
volume = {53},
number = {5},
pages = {547--566},
year = {2004},
url = {https://doi.org/10.1109/TC.2004.1275296},
doi = {10.1109/TC.2004.1275296},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/XueV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/toplas/VeraBLG04,
author = {Xavier Vera and
Nerina Bermudo and
Josep Llosa and
Antonio Gonz{\'{a}}lez},
title = {A fast and accurate framework to analyze and optimize cache memory
behavior},
journal = {{ACM} Trans. Program. Lang. Syst.},
volume = {26},
number = {2},
pages = {263--300},
year = {2004},
url = {https://doi.org/10.1145/973097.973099},
doi = {10.1145/973097.973099},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/toplas/VeraBLG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/VeraAGL03,
author = {Xavier Vera and
Jaume Abella and
Antonio Gonz{\'{a}}lez and
Josep Llosa},
title = {Optimizing Program Locality Through CMEs and GAs},
booktitle = {12th International Conference on Parallel Architectures and Compilation
Techniques {(PACT} 2003), 27 September - 1 October 2003, New Orleans,
LA, {USA}},
pages = {68--78},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/PACT.2003.1238003},
doi = {10.1109/PACT.2003.1238003},
timestamp = {Tue, 31 May 2022 13:36:44 +0200},
biburl = {https://dblp.org/rec/conf/IEEEpact/VeraAGL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/HuangXV03,
author = {Qingguang Huang and
Jingling Xue and
Xavier Vera},
title = {Code Tiling for Improving the Cache Performance of {PDE} Solvers},
booktitle = {32nd International Conference on Parallel Processing {(ICPP} 2003),
6-9 October 2003, Kaohsiung, Taiwan},
pages = {615},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICPP.2003.1240630},
doi = {10.1109/ICPP.2003.1240630},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/HuangXV03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtss/VeraLX03,
author = {Xavier Vera and
Bj{\"{o}}rn Lisper and
Jingling Xue},
title = {Data Caches in Multitasking Hard Real-Time Systems},
booktitle = {Proceedings of the 24th {IEEE} Real-Time Systems Symposium {(RTSS}
2003), 3-5 December 2003, Cancun, Mexico},
pages = {154--165},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/REAL.2003.1253263},
doi = {10.1109/REAL.2003.1253263},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtss/VeraLX03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sigmetrics/VeraLX03,
author = {Xavier Vera and
Bj{\"{o}}rn Lisper and
Jingling Xue},
editor = {Bill Cheng and
Satish K. Tripathi and
Jennifer Rexford and
William H. Sanders},
title = {Data cache locking for higher program predictability},
booktitle = {Proceedings of the International Conference on Measurements and Modeling
of Computer Systems, {SIGMETRICS} 2003, June 9-14, 2003, San Diego,
CA, {USA}},
pages = {272--282},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/781027.781062},
doi = {10.1145/781027.781062},
timestamp = {Thu, 23 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sigmetrics/VeraLX03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/VeraX02,
author = {Xavier Vera and
Jingling Xue},
title = {Let's Study Whole-Program Cache Behaviour Analytically},
booktitle = {Proceedings of the Eighth International Symposium on High-Performance
Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February
2-6, 2002},
pages = {175--186},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/HPCA.2002.995708},
doi = {10.1109/HPCA.2002.995708},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpca/VeraX02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icppw/AbellaGLV02,
author = {Jaume Abella and
Antonio Gonz{\'{a}}lez and
Josep Llosa and
Xavier Vera},
title = {Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic
Algorithms},
booktitle = {31st International Conference on Parallel Processing Workshops {(ICPP}
2002 Workshops), 20-23 August 2002, Vancouver, BC, Canada},
pages = {568--580},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ICPPW.2002.1039779},
doi = {10.1109/ICPPW.2002.1039779},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icppw/AbellaGLV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lcpc/VeraLG02,
author = {Xavier Vera and
Josep Llosa and
Antonio Gonz{\'{a}}lez},
editor = {William W. Pugh and
Chau{-}Wen Tseng},
title = {Near-Optimal Padding for Removing Conflict Misses},
booktitle = {Languages and Compilers for Parallel Computing, 15th Workshop, {LCPC}
2002, College Park, MD, USA, July 25-27, 2002, Revised Papers},
series = {Lecture Notes in Computer Science},
volume = {2481},
pages = {329--343},
publisher = {Springer},
year = {2002},
url = {https://doi.org/10.1007/11596110\_22},
doi = {10.1007/11596110\_22},
timestamp = {Mon, 04 Apr 2022 21:23:55 +0200},
biburl = {https://dblp.org/rec/conf/lcpc/VeraLG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/BermudoVGL00,
author = {Nerina Bermudo and
Xavier Vera and
Antonio Gonz{\'{a}}lez and
Josep Llosa},
title = {Optimizing cache miss equations polyhedra},
journal = {{SIGARCH} Comput. Archit. News},
volume = {28},
number = {1},
pages = {43--52},
year = {2000},
url = {https://doi.org/10.1145/346023.346042},
doi = {10.1145/346023.346042},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/BermudoVGL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/europar/VeraLGB00,
author = {Xavier Vera and
Josep Llosa and
Antonio Gonz{\'{a}}lez and
Nerina Bermudo},
editor = {Arndt Bode and
Thomas Ludwig and
Wolfgang Karl and
Roland Wism{\"{u}}ller},
title = {A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research
Note)},
booktitle = {Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference,
Munich, Germany, August 29 - September 1, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1900},
pages = {194--198},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-44520-X\_26},
doi = {10.1007/3-540-44520-X\_26},
timestamp = {Tue, 14 May 2019 10:00:46 +0200},
biburl = {https://dblp.org/rec/conf/europar/VeraLGB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/BermudoVGL00,
author = {Nerina Bermudo and
Xavier Vera and
Antonio Gonz{\'{a}}lez and
Josep Llosa},
title = {An efficient solver for Cache Miss Equations},
booktitle = {2000 {IEEE} International Symposium on Performance Analysis of Systems
and Software, April 24-35, 2000, Austin, Texas, USA, Proceedings},
pages = {139--145},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISPASS.2000.842293},
doi = {10.1109/ISPASS.2000.842293},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispass/BermudoVGL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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