Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Sreehari Veeramachaneni
@inproceedings{DBLP:conf/vlsid/SakaliVM24,
author = {Raghavendra Kumar Sakali and
Sreehari Veeramachaneni and
Sk. Noor Mahammad},
title = {Fault-Tolerant Floating-Point Multiplier Design for Mission Critical
Systems},
booktitle = {37th International Conference on {VLSI} Design and 23rd International
Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
6-10, 2024},
pages = {678--683},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VLSID60093.2024.00120},
doi = {10.1109/VLSID60093.2024.00120},
timestamp = {Mon, 08 Apr 2024 20:48:39 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/SakaliVM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SakaliVM23,
author = {Raghavendra Kumar Sakali and
Sreehari Veeramachaneni and
Sk. Noor Mahammad},
title = {Preferential fault-tolerance multiplier design to mitigate soft errors
in FPGAs},
journal = {Integr.},
volume = {93},
pages = {102068},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2023.102068},
doi = {10.1016/J.VLSI.2023.102068},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SakaliVM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/SakaliBRVM23,
author = {Raghavendra Kumar Sakali and
P. Balasubramanian and
Ramesh Reddy and
Sreehari Veeramachaneni and
Sk. Noor Mahammad},
title = {Optimized Fault-Tolerant Adder Design Using Error Analysis},
journal = {J. Circuits Syst. Comput.},
volume = {32},
number = {6},
pages = {2350091:1--2350091:32},
year = {2023},
url = {https://doi.org/10.1142/S0218126623500913},
doi = {10.1142/S0218126623500913},
timestamp = {Sun, 06 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/SakaliBRVM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/JonnalagaddaUVA23,
author = {Aditya Anirudh Jonnalagadda and
Anil Kumar Uppugunduru and
Sreehari Veeramachaneni and
Syed Ershad Ahmed},
editor = {Himanshu Thapliyal and
Ronald F. DeMara and
Inna Partin{-}Vaisband and
Srinivas Katkoori},
title = {Design of Energy Efficient Posit Multiplier},
booktitle = {Proceedings of the Great Lakes Symposium on {VLSI} 2023, {GLSVLSI}
2023, Knoxville, TN, USA, June 5-7, 2023},
pages = {645--651},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3583781.3590227},
doi = {10.1145/3583781.3590227},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/JonnalagaddaUVA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/TharuniRMKAV23,
author = {Sangireddy Tharuni and
Basani Harshavardhan Reddy and
Bhukya Mamatha and
Uppugunduru Anil Kumar and
Syed Ershad Ahmed and
Sreehari Veeramachaneni},
title = {Power Efficient Approximate Ternary Subtractor for Image Processing
Applications},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2023,
Ahmedabad, India, December 18-20, 2023},
pages = {127--130},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/iSES58672.2023.00035},
doi = {10.1109/ISES58672.2023.00035},
timestamp = {Tue, 02 Apr 2024 12:53:25 +0200},
biburl = {https://dblp.org/rec/conf/ises/TharuniRMKAV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cssp/HarshaJBVS22,
author = {L. Guna Sekhar Sai Harsha and
Bhaskara Rao Jammu and
Nalini Bodasingi and
Sreehari Veeramachaneni and
Noor Mohammad S.},
title = {A Low Error, Hardware Efficient Logarithmic Multiplier},
journal = {Circuits Syst. Signal Process.},
volume = {41},
number = {1},
pages = {485--513},
year = {2022},
url = {https://doi.org/10.1007/s00034-021-01793-8},
doi = {10.1007/S00034-021-01793-8},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cssp/HarshaJBVS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/JyothiSJVM22,
author = {Chinthalgiri Jyothi and
Saranya Karunamurthi and
Bhaskara Rao Jammu and
Sreehari Veeramachaneni and
Sk. Noor Mahammad},
title = {A New Approximate 4-2 Compressor using Merged Sum and Carry},
journal = {J. Electron. Test.},
volume = {38},
number = {4},
pages = {381--394},
year = {2022},
url = {https://doi.org/10.1007/s10836-022-06019-6},
doi = {10.1007/S10836-022-06019-6},
timestamp = {Fri, 04 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/JyothiSJVM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcmse/JammuHBVS22,
author = {Bhaskara Rao Jammu and
L. Guna Sekhar Sai Harsha and
Nalini Bodasingi and
Sreehari Veeramachaneni and
Noor Mohammad S.},
title = {Hardware efficient circuit for low error logarithmic converter},
journal = {J. Comput. Methods Sci. Eng.},
volume = {22},
number = {2},
pages = {511--527},
year = {2022},
url = {https://doi.org/10.3233/JCM-215778},
doi = {10.3233/JCM-215778},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcmse/JammuHBVS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/KollaSVM22,
author = {Sandeep Kolla and
Ayesha Sk and
Sreehari Veeramachaneni and
Sk. Noor Mahammad},
title = {Logic Locking Designs at Transistor Level for Full Adders},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2022,
Warangal, India, December 18-22, 2022},
pages = {289--292},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/iSES54909.2022.00065},
doi = {10.1109/ISES54909.2022.00065},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ises/KollaSVM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cee/MounicaKVM21,
author = {Y. Mounica and
K. Naresh Kumar and
Sreehari Veeramachaneni and
S. K. Noor Mahammad},
title = {Energy efficient signed and unsigned radix 16 booth multiplier design},
journal = {Comput. Electr. Eng.},
volume = {90},
pages = {106892},
year = {2021},
url = {https://doi.org/10.1016/j.compeleceng.2020.106892},
doi = {10.1016/J.COMPELECENG.2020.106892},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cee/MounicaKVM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/KrishnaMJVM21,
author = {L. Hemanth Krishna and
Neeharika M. and
Vishvanath Janjirala and
Sreehari Veeramachaneni and
S. K. Noor Mahammad},
title = {Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed
multiplication},
journal = {{IET} Comput. Digit. Tech.},
volume = {15},
number = {1},
pages = {12--19},
year = {2021},
url = {https://doi.org/10.1049/cdt2.12002},
doi = {10.1049/CDT2.12002},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/KrishnaMJVM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijcta/HarshaJSVS21,
author = {L. Guna Sekhar Sai Harsha and
Bhaskara Rao Jammu and
Visweswara Rao Samoju and
Sreehari Veeramachaneni and
Noor Mohammad S.},
title = {A low-error, memory-based fast binary antilogarithmic converter},
journal = {Int. J. Circuit Theory Appl.},
volume = {49},
number = {7},
pages = {2214--2226},
year = {2021},
url = {https://doi.org/10.1002/cta.2981},
doi = {10.1002/CTA.2981},
timestamp = {Mon, 14 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijcta/HarshaJSVS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/KrishnaRSVM21,
author = {L. Hemanth Krishna and
J. Bhaskara Rao and
Ayesha Sk and
Sreehari Veeramachaneni and
S. K. Noor Mahammad},
title = {Energy Efficient Approximate 4: 2 Compressors for Error Tolerant Applications},
booktitle = {28th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2021, Dubai, United Arab Emirates, November 28 -
Dec. 1, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICECS53924.2021.9665614},
doi = {10.1109/ICECS53924.2021.9665614},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/KrishnaRSVM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icm2/KollaSVM21,
author = {Sandeep Kolla and
Ayesha Sk and
Sreehari Veeramachaneni and
Sk. Noor Mahammad},
title = {Design and Analysis of Obfuscated Full Adders},
booktitle = {International Conference on Microelectronics, {ICM} 2021, New Cairo
City, Egypt, December 19-22, 2021},
pages = {49--52},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICM52667.2021.9664955},
doi = {10.1109/ICM52667.2021.9664955},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icm2/KollaSVM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/KrishnaRSVM21,
author = {L. Hemanth Krishna and
J. Bhaskara Rao and
Ayesha Sk and
Sreehari Veeramachaneni and
Sk. Noor Mahammad},
title = {Energy Efficient Approximate Multiplier Design for Image/Video Processing
Applications},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2021,
Jaipur, India, December 18-22, 2021},
pages = {210--215},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/iSES52644.2021.00056},
doi = {10.1109/ISES52644.2021.00056},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ises/KrishnaRSVM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijcta/MounicaKVM20,
author = {Chandana Mounica and
Sagar Krishna and
Sreehari Veeramachaneni and
Sk. Noor Mahammad},
title = {Efficient implementation of mixed-precision multiply-accumulator unit
for {AI} algorithms},
journal = {Int. J. Circuit Theory Appl.},
volume = {48},
number = {8},
pages = {1386--1394},
year = {2020},
url = {https://doi.org/10.1002/cta.2776},
doi = {10.1002/CTA.2776},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijcta/MounicaKVM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/AdimulamKVS18,
author = {Mahesh Kumar Adimulam and
Amit Kapoor and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {An Ultra Low Power, 10-Bit Two-Step Flash {ADC} for Signal Processing
Applications},
booktitle = {31st International Conference on {VLSI} Design and 17th International
Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
6-10, 2018},
pages = {19--24},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/VLSID.2018.31},
doi = {10.1109/VLSID.2018.31},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/AdimulamKVS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/PalVPVM14,
author = {Subhankar Pal and
Chetan Vudadha and
P. Sai Phaneendra and
Sreehari Veeramachaneni and
Srinivas B. Mandalika},
title = {A New Design of an N-Bit Reversible Arithmetic Logic Unit},
booktitle = {2014 Fifth International Symposium on Electronic System Design, Surathkal,
Mangalore, India, December 15-17, 2014},
pages = {224--225},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISED.2014.56},
doi = {10.1109/ISED.2014.56},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/PalVPVM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ReddySVS14,
author = {B. Naveen Kumar Reddy and
M. Chandra Sekhar and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator
in Floating Point Units},
booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014,
and 2014 13th International Conference on Embedded Systems, Mumbai,
India, January 5-9, 2014},
pages = {128--132},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VLSID.2014.29},
doi = {10.1109/VLSID.2014.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ReddySVS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PVVS14,
author = {P. Sai Phaneendra and
Chetan Vudadha and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {An Optimized Design of Reversible Quantum Comparator},
booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014,
and 2014 13th International Conference on Embedded Systems, Mumbai,
India, January 5-9, 2014},
pages = {557--562},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VLSID.2014.103},
doi = {10.1109/VLSID.2014.103},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PVVS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscit/VudadhaPVS12,
author = {Chetan Vudadha and
Phaneendra P. Sai and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {{CNFET} based ternary magnitude comparator},
booktitle = {International Symposium on Communications and Information Technologies,
{ISCIT} 2012, Gold Coast, Australia, October 2-5, 2012},
pages = {942--946},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCIT.2012.6381040},
doi = {10.1109/ISCIT.2012.6381040},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscit/VudadhaPVS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/AhmedAVMS12,
author = {Syed Ershad Ahmed and
Sibi Abraham and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Modified Twin Precision Multiplier with 2D Bypassing Technique},
booktitle = {International Symposium on Electronic System Design, ISEDs 2012, Kolkata,
India, December 19-22, 2012},
pages = {102--106},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISED.2012.58},
doi = {10.1109/ISED.2012.58},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ised/AhmedAVMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VudadhaPVAMS12,
author = {Chetan Vudadha and
P. Sai Phaneendra and
Sreehari Veeramachaneni and
Syed Ershad Ahmed and
N. Moorthy Muthukrishnan and
Mandalika B. Srinivas},
title = {Design of Prefix-Based Optimal Reversible Comparator},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2012, Amherst,
MA, USA, August 19-21, 2012},
pages = {201--206},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISVLSI.2012.49},
doi = {10.1109/ISVLSI.2012.49},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VudadhaPVAMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VudadhaPAVMS12,
author = {Chetan Vudadha and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
Mandalika B. Srinivas},
title = {Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple
Hybrid Adders},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2012, Amherst,
MA, USA, August 19-21, 2012},
pages = {225--230},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISVLSI.2012.50},
doi = {10.1109/ISVLSI.2012.50},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VudadhaPAVMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VudadhaMNPAVMS12,
author = {Chetan Vudadha and
Goutham Makkena and
M. Venkata Swamy Nayudu and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
editor = {Vishwani D. Agrawal and
Srimat T. Chakradhar},
title = {Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive
Resolution Flash ADCs},
booktitle = {25th International Conference on {VLSI} Design, Hyderabad, India,
January 7-11, 2012},
pages = {280--285},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/VLSID.2012.84},
doi = {10.1109/VLSID.2012.84},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VudadhaMNPAVMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/VPAVMS11,
author = {Chetan Kumar V. and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Unified Architecture for {BCD} and Binary Adder/Subtractor},
booktitle = {14th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2011, August 31 - September 2, 2011, Oulu,
Finland},
pages = {426--429},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/DSD.2011.58},
doi = {10.1109/DSD.2011.58},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/VPAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscit/PVAVMS11,
author = {P. Sai Phaneendra and
Chetan Vudadha and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {Increment/decrement/2's complement/priority encoder circuit for varying
operand lengths},
booktitle = {11th International Symposium on Communications and Information Technologies,
{ISCIT} 2011, Hangzhou, China, October 12-14, 2011},
pages = {472--477},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCIT.2011.6092152},
doi = {10.1109/ISCIT.2011.6092152},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscit/PVAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/AdimulamMVMS11,
author = {Mahesh Kumar Adimulam and
Krishna Kumar Movva and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Multiple-Bandwidth 10-bit {SAR} Analog to Digital Converter},
booktitle = {International Symposium on Electronic System Design, {ISED} 2011,
Kochi, Kerala, India, December 19-21, 2011},
pages = {24--29},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISED.2011.63},
doi = {10.1109/ISED.2011.63},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/AdimulamMVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/VPAVMS11,
author = {Chetan Kumar V. and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with
Improved Decision Block},
booktitle = {International Symposium on Electronic System Design, {ISED} 2011,
Kochi, Kerala, India, December 19-21, 2011},
pages = {100--105},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISED.2011.52},
doi = {10.1109/ISED.2011.52},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/VPAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VPAVMS11,
author = {Chetan Kumar V. and
Sai Phaneendra P. and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Prefix Based Reconfigurable Adder},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
July 2011, Chennai, India},
pages = {349--350},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISVLSI.2011.69},
doi = {10.1109/ISVLSI.2011.69},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VPAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/SainiKVS10,
author = {Sandeep Saini and
A. Mahesh Kumar and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {An Alternate Approach to Buffer Insertion for Delay and Power Reduction
in {VLSI} Interconnects},
journal = {J. Low Power Electron.},
volume = {6},
number = {3},
pages = {429--435},
year = {2010},
url = {https://doi.org/10.1166/jolpe.2010.1090},
doi = {10.1166/JOLPE.2010.1090},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/SainiKVS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/AdimulamMVMS10,
author = {Mahesh Kumar Adimulam and
Krishna Kumar Movva and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
Mandalika B. Srinivas},
title = {Low power, variable resolution pipelined analog to Digital converter
with sub flash architecture},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
Kuala Lumpur, Malaysia, December 6-9, 2010},
pages = {204--207},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/APCCAS.2010.5774898},
doi = {10.1109/APCCAS.2010.5774898},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/AdimulamMVMS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AdimulamMVMS10,
author = {Mahesh Kumar Adimulam and
Krishna Kumar Movva and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
editor = {R. Iris Bahar and
Fabrizio Lombardi and
David Atienza and
Erik Brunvand},
title = {A low power, variable resolution two-step flash {ADC}},
booktitle = {Proceedings of the 20th {ACM} Great Lakes Symposium on {VLSI} 2009,
Providence, Rhode Island, USA, May 16-18 2010},
pages = {39--44},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1785481.1785492},
doi = {10.1145/1785481.1785492},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/AdimulamMVMS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AdimulamVMS10,
author = {Mahesh Kumar Adimulam and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Novel, Variable Resolution Flash {ADC} with Sub Flash Architecture},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2010, 5-7
July 2010, Lixouri Kefalonia, Greece},
pages = {434--435},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ISVLSI.2010.68},
doi = {10.1109/ISVLSI.2010.68},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AdimulamVMS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SainiAVS10,
author = {Sandeep Saini and
Mahesh Kumar Adimulam and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {An Alternative approach to Buffer Insertion for Delay and Power Reduction
in {VLSI} Interconnects},
booktitle = {{VLSI} Design 2010: 23rd International Conference on {VLSI} Design,
9th International Conference on Embedded Systems, Bangalore, India,
3-7 January 2010},
pages = {411--416},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VLSI.Design.2010.53},
doi = {10.1109/VLSI.DESIGN.2010.53},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SainiAVS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/AdimulamVS09,
author = {Mahesh Kumar Adimulam and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter},
journal = {J. Low Power Electron.},
volume = {5},
number = {3},
pages = {279--290},
year = {2009},
url = {https://doi.org/10.1166/jolpe.2009.1029},
doi = {10.1166/JOLPE.2009.1029},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/AdimulamVS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SinghGVS09,
author = {Anshul Singh and
Aman Gupta and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {A High Performance Unified {BCD} and Binary Adder/Subtractor},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2009, 13-15
May 2009, Tampa, Florida, {USA}},
pages = {211--216},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISVLSI.2009.40},
doi = {10.1109/ISVLSI.2009.40},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SinghGVS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/AdimulamVS09,
author = {Mahesh Kumar Adimulam and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {A novel low power, variable resolution pipelined {ADC}},
booktitle = {Annual {IEEE} International SoC Conference, SoCC 2009, September 9-11,
2009, Belfast, Northern Ireland, UK, Proceedings},
pages = {183--186},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/SOCCON.2009.5398061},
doi = {10.1109/SOCCON.2009.5398061},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/AdimulamVS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VeeramachaneniKTS09,
author = {Sreehari Veeramachaneni and
Mahesh Kumar Adimulam and
Venkat Tummala and
M. B. Srinivas},
title = {Design of a Low Power, Variable-Resolution Flash {ADC}},
booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
The 22nd International Conference on {VLSI} Design, New Delhi, India,
5-9 January 2009},
pages = {117--122},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VLSI.Design.2009.62},
doi = {10.1109/VLSI.DESIGN.2009.62},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VeeramachaneniKTS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VeeramachaneniKVSSS08,
author = {Sreehari Veeramachaneni and
Kirthi M. Krishna and
Prateek G. V. and
Subroto S. and
Bharat S. and
M. B. Srinivas},
title = {A Novel Carry-Look Ahead Approach to a Unified {BCD} and Binary Adder/Subtractor},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {547--552},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.80},
doi = {10.1109/VLSI.2008.80},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VeeramachaneniKVSSS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/VeeramachaneniAKS07,
author = {Sreehari Veeramachaneni and
Lingamneni Avinash and
Kirthi M. Krishna and
M. B. Srinivas},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Novel architectures for efficient (m, n) parallel counters},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {188--191},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228833},
doi = {10.1145/1228784.1228833},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/VeeramachaneniAKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/VeeramachaneniKASS07,
author = {Sreehari Veeramachaneni and
Kirthi M. Krishna and
Lingamneni Avinash and
Reddy Puppala Sreekanth and
M. B. Srinivas},
title = {Novel High-Speed Redundant Binary to Binary converter using Prefix
Networks},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {3271--3274},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378170},
doi = {10.1109/ISCAS.2007.378170},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/VeeramachaneniKASS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VeeramachaneniKASS07,
author = {Sreehari Veeramachaneni and
Kirthi M. Krishna and
Lingamneni Avinash and
Reddy Puppala Sreekanth and
M. B. Srinivas},
title = {Novel, High-Speed 16-Digit {BCD} Adders Conforming to {IEEE} 754r
Format},
booktitle = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2007), May 9-11, 2007, Porto Alegre, Brazil},
pages = {343--350},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISVLSI.2007.71},
doi = {10.1109/ISVLSI.2007.71},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VeeramachaneniKASS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VeeramachaneniKAPS07,
author = {Sreehari Veeramachaneni and
Kirthi M. Krishna and
Lingamneni Avinash and
Reddy Puppala Sreekanth and
M. B. Srinivas},
title = {Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2
Compressors},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {324--329},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.116},
doi = {10.1109/VLSID.2007.116},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VeeramachaneniKAPS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-21 17:26 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
