Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Kimiyoshi Usami
@article{DBLP:journals/tvlsi/UsamiYKASHB24,
author = {Kimiyoshi Usami and
Daiki Yokoyama and
Aika Kamei and
Hideharu Amano and
Kenta Suzuki and
Keizo Hiraga and
Kazuhiro Bessho},
title = {Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops
to Minimize Store Energy Under Process and Temperature Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {89--102},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3318468},
doi = {10.1109/TVLSI.2023.3318468},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/UsamiYKASHB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KameiAKYUHSB23,
author = {Aika Kamei and
Hideharu Amano and
Takuya Kojima and
Daiki Yokoyama and
Kimiyoshi Usami and
Keizo Hiraga and
Kenta Suzuki and
Kazuhiro Bessho},
title = {A Variation-Aware {MTJ} Store Energy Estimation Model for Edge Devices
With Verify-and-Retryable Nonvolatile Flip-Flops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {532--542},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3237794},
doi = {10.1109/TVLSI.2023.3237794},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KameiAKYUHSB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iotais/UsamiWNLM23,
author = {Kimiyoshi Usami and
Songxiang Wang and
Kaito Nagai and
Giovanna Latronico and
Paolo Mele},
title = {A 200mV Operable On-Chip Temperature Sensor for IoT Devices Powered
by Energy Harvesters with Ultra-Low Output Voltage},
booktitle = {{IEEE} International Conference on Internet of Things and Intelligence
Systems, IoTaIS 2023, Bali, Indonesia, November 28-30, 2023},
pages = {65--71},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/IoTaIS60147.2023.10346043},
doi = {10.1109/IOTAIS60147.2023.10346043},
timestamp = {Fri, 09 Feb 2024 20:38:53 +0100},
biburl = {https://dblp.org/rec/conf/iotais/UsamiWNLM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/SuzukiHBUU23,
author = {Kenta Suzuki and
Keizo Hiraga and
Kazuhiro Bessho and
Kimiyoshi Usami and
Taku Umebayashi},
title = {A 40 nm 2 kb MTJ-Based Non-Volatile {SRAM} Macro with Novel Data-Aware
Store Architecture for Normally Off Computing},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185432},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185432},
timestamp = {Fri, 28 Jul 2023 10:40:41 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/SuzukiHBUU23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norcas/UsamiYKA22,
author = {Kimiyoshi Usami and
Daiki Yokoyama and
Aika Kamei and
Hideharu Amano},
editor = {Jari Nurmi and
Dag T. Wisland and
Snorre Aunet and
Kristian Kjelgaard},
title = {Optimal switching time to minimize store energy in MTJ-based flip-flops
under process and temperature variations},
booktitle = {{IEEE} Nordic Circuits and Systems Conference, NorCAS 2022, Oslo,
Norway, October 25-26, 2022},
pages = {1--7},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/NorCAS57515.2022.9934567},
doi = {10.1109/NORCAS57515.2022.9934567},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/norcas/UsamiYKA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetc/OnoU21,
author = {Yoshinori Ono and
Kimiyoshi Usami},
title = {Energy Efficient Approximate Storing of Image Data for {MTJ} Based
Non-Volatile Flip-Flops and {MRAM}},
journal = {{IEICE} Trans. Electron.},
volume = {104-C},
number = {7},
pages = {338--349},
year = {2021},
url = {https://doi.org/10.1587/transele.2020cdp0009},
doi = {10.1587/TRANSELE.2020CDP0009},
timestamp = {Thu, 12 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetc/OnoU21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/KameiKAYMUHSB21,
author = {Aika Kamei and
Takuya Kojima and
Hideharu Amano and
Daiki Yokoyama and
Hisato Miyauchi and
Kimiyoshi Usami and
Keizo Hiraga and
Kenta Suzuki and
Kazuhiro Bessho},
title = {Energy saving in a multi-context coarse grained reconfigurable array
with non-volatile flip-flops},
booktitle = {14th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23,
2021},
pages = {273--280},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MCSoC51149.2021.00047},
doi = {10.1109/MCSOC51149.2021.00047},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mcsoc/KameiKAYMUHSB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/UsamiAAIHSK20,
author = {Kimiyoshi Usami and
Sosuke Akiba and
Hideharu Amano and
Takeharu Ikezoe and
Keizo Hiraga and
Kenta Suzuki and
Yasuo Kanda},
title = {Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step
Store Control for Energy Minimization},
booktitle = {2020 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
2020, Kokubunji, Japan, April 15-17, 2020},
pages = {1--3},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/COOLCHIPS49199.2020.9097630},
doi = {10.1109/COOLCHIPS49199.2020.9097630},
timestamp = {Sat, 06 Jun 2020 15:00:53 +0200},
biburl = {https://dblp.org/rec/conf/coolchips/UsamiAAIHSK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nvmsa/OnoU20,
author = {Yoshinori Ono and
Kimiyoshi Usami},
title = {Energy Efficient Approximate Storing of Image Data for {MTJ} Based
Non-volatile Memory},
booktitle = {9th Non-Volatile Memory Systems and Applications Symposium, {NVMSA}
2020, Seoul, South Korea, August 19-21, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/NVMSA51238.2020.9188231},
doi = {10.1109/NVMSA51238.2020.9188231},
timestamp = {Tue, 22 Sep 2020 12:06:25 +0200},
biburl = {https://dblp.org/rec/conf/nvmsa/OnoU20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nvmsa/UsamiAAKAIHSY18,
author = {Kimiyoshi Usami and
Junya Akaike and
Sosuke Akiba and
Masaru Kudo and
Hideharu Amano and
Takeharu Ikezoe and
Keizo Hiraga and
Yusuke Shuto and
Kojiro Yagami},
title = {Energy Efficient Write Verify and Retry Scheme for {MTJ} Based Flip-Flop
and Application},
booktitle = {{IEEE} 7th Non-Volatile Memory Systems and Applications Symposium,
{NVMSA} 2018, Hakodate, Sapporo, Japan, August 28-31, 2018},
pages = {91--98},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NVMSA.2018.00023},
doi = {10.1109/NVMSA.2018.00023},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/nvmsa/UsamiAAKAIHSY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/IkezoeAAUKHSY18,
author = {Takeharu Ikezoe and
Hideharu Amano and
Junya Akaike and
Kimiyoshi Usami and
Masaru Kudo and
Keizo Hiraga and
Yusuke Shuto and
Kojiro Yagami},
editor = {David Andrews and
Ren{\'{e}} Cumplido and
Claudia Feregrino and
Dirk Stroobandt},
title = {A Coarse Grained-Reconfigurable Accelerator with energy efficient
MTJ-based Non-volatile Flip-flops},
booktitle = {2018 International Conference on ReConFigurable Computing and FPGAs,
ReConFig 2018, Cancun, Mexico, December 3-5, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/RECONFIG.2018.8641712},
doi = {10.1109/RECONFIG.2018.8641712},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/IkezoeAAUKHSY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YoshidaU17,
author = {Yusuke Yoshida and
Kimiyoshi Usami},
title = {Energy-Efficient Standard Cell Memory with Optimized Body-Bias Separation
in Silicon-on-Thin-BOX {(SOTB)}},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {100-A},
number = {12},
pages = {2785--2796},
year = {2017},
url = {https://doi.org/10.1587/transfun.E100.A.2785},
doi = {10.1587/TRANSFUN.E100.A.2785},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YoshidaU17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OkuharaFUA17,
author = {Hayate Okuhara and
Yu Fujita and
Kimiyoshi Usami and
Hideharu Amano},
title = {Power Optimization Methodology for Ultralow Power Microcontroller
With Silicon on Thin {BOX} {MOSFET}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1578--1582},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2635675},
doi = {10.1109/TVLSI.2016.2635675},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OkuharaFUA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/YoshidaUA17,
author = {Yusuke Yoshida and
Kimiyoshi Usami and
Hideharu Amano},
title = {Digital embedded memory scheme using voltage scaling and body bias
separation for low-power system},
booktitle = {International SoC Design Conference, {ISOCC} 2017, Seoul, South Korea,
November 5-8, 2017},
pages = {148--149},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISOCC.2017.8368840},
doi = {10.1109/ISOCC.2017.8368840},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/YoshidaUA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/AmanoKNUKMN17,
author = {Hideharu Amano and
Tadahiro Kuroda and
Hiroshi Nakamura and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroki Matsutani and
Mitaro Namiki},
title = {Building block multi-chip systems using inductive coupling through
chip interface},
booktitle = {International SoC Design Conference, {ISOCC} 2017, Seoul, South Korea,
November 5-8, 2017},
pages = {152--154},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISOCC.2017.8368842},
doi = {10.1109/ISOCC.2017.8368842},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/AmanoKNUKMN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nvmsa/KudoU17,
author = {Masaru Kudo and
Kimiyoshi Usami},
title = {Nonvolatile power gating with {MTJ} based nonvolatile flip-flops for
a microprocessor},
booktitle = {{IEEE} 6th Non-Volatile Memory Systems and Applications Symposium,
{NVMSA} 2017, Hsinchu, Taiwan, August 16-18, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/NVMSA.2017.8064472},
doi = {10.1109/NVMSA.2017.8064472},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/nvmsa/KudoU17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/UsamiKYMA17,
author = {Kimiyoshi Usami and
Shunsuke Kogure and
Yusuke Yoshida and
Ryo Magasaki and
Hideharu Amano},
title = {Level-shifter-less approach for multi-VDD design to use body bias
control in {FD-SOI}},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203473},
doi = {10.1109/VLSI-SOC.2017.8203473},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/UsamiKYMA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/UsamiKYMA17a,
author = {Kimiyoshi Usami and
Shunsuke Kogure and
Yusuke Yoshida and
Ryo Magasaki and
Hideharu Amano},
editor = {Michail Maniatakos and
Ibrahim Abe M. Elfadel and
Matteo Sonza Reorda and
H. Fatih Ugurdag and
Jos{\'{e}} Monteiro and
Ricardo Reis},
title = {Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body
Bias Control in {FD-SOI}},
booktitle = {VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
- 25th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates,
October 23-25, 2017, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {500},
pages = {1--21},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-15663-3\_1},
doi = {10.1007/978-3-030-15663-3\_1},
timestamp = {Tue, 12 Sep 2023 07:57:22 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/UsamiKYMA17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AhmedMKUA16,
author = {Akram Ben Ahmed and
Hiroki Matsutani and
Michihiro Koibuchi and
Kimiyoshi Usami and
Hideharu Amano},
title = {Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency
for Low-Power Network-on-Chips Systems},
journal = {{IEICE} Trans. Electron.},
volume = {99-C},
number = {8},
pages = {909--917},
year = {2016},
url = {https://doi.org/10.1587/transele.E99.C.909},
doi = {10.1587/TRANSELE.E99.C.909},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/AhmedMKUA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KoshibaSUASKNN16,
author = {Atsushi Koshiba and
Mikiko Sato and
Kimiyoshi Usami and
Hideharu Amano and
Ryuichi Sakamoto and
Masaaki Kondo and
Hiroshi Nakamura and
Mitaro Namiki},
title = {An Operating System Guided Fine-Grained Power Gating Control Based
on Runtime Characteristics of Applications},
journal = {{IEICE} Trans. Electron.},
volume = {99-C},
number = {8},
pages = {926--935},
year = {2016},
url = {https://doi.org/10.1587/transele.E99.C.926},
doi = {10.1587/TRANSELE.E99.C.926},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/KoshibaSUASKNN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/IshibashiSKUAKP15,
author = {Koichiro Ishibashi and
Nobuyuki Sugii and
Shiro Kamohara and
Kimiyoshi Usami and
Hideharu Amano and
Kazutoshi Kobayashi and
Cong{-}Kha Pham},
title = {A Perpetuum Mobile 32bit {CPU} on 65nm {SOTB} {CMOS} Technology with
Reverse-Body-Bias Assisted Sleep Mode},
journal = {{IEICE} Trans. Electron.},
volume = {98-C},
number = {7},
pages = {536--543},
year = {2015},
url = {https://doi.org/10.1587/transele.E98.C.536},
doi = {10.1587/TRANSELE.E98.C.536},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/IshibashiSKUAKP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KoshibaWSSKUAKN15,
author = {Atsushi Koshiba and
Motoki Wada and
Ryuichi Sakamoto and
Mikiko Sato and
Tsubasa Kosaka and
Kimiyoshi Usami and
Hideharu Amano and
Masaaki Kondo and
Hiroshi Nakamura and
Mitaro Namiki},
title = {A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption
of Processor Functional Units},
journal = {{IEICE} Trans. Electron.},
volume = {98-C},
number = {7},
pages = {559--568},
year = {2015},
url = {https://doi.org/10.1587/transele.E98.C.559},
doi = {10.1587/TRANSELE.E98.C.559},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/KoshibaWSSKUAKN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AbeSUYT15,
author = {Shin{-}ya Abe and
Youhua Shi and
Kimiyoshi Usami and
Masao Yanagisawa and
Nozomu Togawa},
title = {An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm
for Multiple Clock Domains Design},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {98-A},
number = {7},
pages = {1376--1391},
year = {2015},
url = {https://doi.org/10.1587/transfun.E98.A.1376},
doi = {10.1587/TRANSFUN.E98.A.1376},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/AbeSUYT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/OkuharaUA15,
author = {Hayate Okuhara and
Kimiyoshi Usami and
Hideharu Amano},
title = {A leakage current monitor circuit using silicon on thin {BOX} {MOSFET}
for dynamic back gate bias control},
booktitle = {2015 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
XVIII, Yokohama, Japan, April 13-15, 2015},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/CoolChips.2015.7158656},
doi = {10.1109/COOLCHIPS.2015.7158656},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/OkuharaUA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/OkuharaKFUA15,
author = {Hayate Okuhara and
Kuniaki Kitamori and
Yu Fujita and
Kimiyoshi Usami and
Hideharu Amano},
title = {An optimal power supply and body bias voltage for a ultra low power
micro-controller with silicon on thin box {MOSFET}},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2015, Rome, Italy, July 22-24, 2015},
pages = {207--212},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISLPED.2015.7273515},
doi = {10.1109/ISLPED.2015.7273515},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/OkuharaKFUA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/UsamiKMKTWAKSNKN14,
author = {Kimiyoshi Usami and
Masaru Kudo and
Kensaku Matsunaga and
Tsubasa Kosaka and
Yoshihiro Tsurui and
Weihan Wang and
Hideharu Amano and
Hiroaki Kobayashi and
Ryuichi Sakamoto and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura},
title = {Design and control methodology for fine grain power gating based on
energy characterization and code profiling of microprocessors},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {843--848},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742995},
doi = {10.1109/ASPDAC.2014.6742995},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/UsamiKMKTWAKSNKN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/IshibashiSUAKPM14,
author = {Koichiro Ishibashi and
Nobuyuki Sugii and
Kimiyoshi Usami and
Hideharu Amano and
Kazutoshi Kobayashi and
Cong{-}Kha Pham and
Hideki Makiyama and
Yoshiki Yamamoto and
Hirofumi Shinohara and
Toshiaki Iwamatsu and
Yasuo Yamaguchi and
Hidekazu Oda and
Takumi Hasegawa and
Shinobu Okanishi and
Hiroshi Yanagita and
Shiro Kamohara and
Masaru Kadoshima and
Keiichi Maekawa and
Tomohiro Yamashita and
Duc{-}Hung Le and
Takumu Yomogita and
Masaru Kudo and
Kuniaki Kitamori and
Shuya Kondo and
Yuuki Manzawa},
title = {A Perpetuum Mobile 32bit {CPU} with 13.4pJ/cycle, 0.14{\(\mathrm{\mu}\)}A
sleep current using Reverse Body Bias Assisted 65nm {SOTB} {CMOS}
technology},
booktitle = {2014 {IEEE} Symposium on Low-Power and High-Speed Chips, {COOL} Chips
XVII, Yokohama, Japan, April 14-16, 2014},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/CoolChips.2014.6842954},
doi = {10.1109/COOLCHIPS.2014.6842954},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/coolchips/IshibashiSUAKPM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KondoKSWTNWAMKUKN14,
author = {Masaaki Kondo and
Hiroaki Kobayashi and
Ryuichi Sakamoto and
Motoki Wada and
Jun Tsukamoto and
Mitaro Namiki and
Weihan Wang and
Hideharu Amano and
Kensaku Matsunaga and
Masaru Kudo and
Kimiyoshi Usami and
Toshiya Komoda and
Hiroshi Nakamura},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Design and evaluation of fine-grained power-gating for embedded microprocessors},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--6},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.158},
doi = {10.7873/DATE.2014.158},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/KondoKSWTNWAMKUKN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/KamoharaSIUAKP14,
author = {Shiro Kamohara and
Nobuyuki Sugii and
Koichiro Ishibashi and
Kimiyoshi Usami and
Hideharu Amano and
Kazutoshi Kobayashi and
Cong{-}Kha Pham},
title = {A perpetuum mobile 32bit {CPU} on 65nm {SOTB} {CMOS} technology with
reverse-body-bias assisted sleep mode},
booktitle = {2014 {IEEE} Hot Chips 26 Symposium (HCS), Cupertino, CA, USA, August
10-12, 2014},
pages = {1},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/HOTCHIPS.2014.7478838},
doi = {10.1109/HOTCHIPS.2014.7478838},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hotchips/KamoharaSIUAKP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/issoc/UsamiMKTANKN14,
author = {Kimiyoshi Usami and
Makoto Miyauchi and
Masaru Kudo and
Kazumitsu Takagi and
Hideharu Amano and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura},
editor = {Jari Nurmi and
Peeter Ellervee and
Dragomir Milojevic and
Ondrej Daniel and
Tommi Paakki},
title = {Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain
power gating},
booktitle = {2014 International Symposium on System-on-Chip, SoC 2014, Tampere,
Finland, October 28-29, 2014},
pages = {1--7},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSOC.2014.6972438},
doi = {10.1109/ISSOC.2014.6972438},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/issoc/UsamiMKTANKN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/FujitaUA14,
author = {Yu Fujita and
Kimiyoshi Usami and
Hideharu Amano},
title = {A Thermal Management System for Building Block Computing Systems},
booktitle = {{IEEE} 8th International Symposium on Embedded Multicore/Manycore
SoCs, MCSoC 2014, Aizu-Wakamatsu, Japan, September 23-25, 2014},
pages = {165--171},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/MCSoC.2014.32},
doi = {10.1109/MCSOC.2014.32},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/FujitaUA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/NakamuraWOUAKN13,
author = {Hiroshi Nakamura and
Weihan Wang and
Yuya Ohta and
Kimiyoshi Usami and
Hideharu Amano and
Masaaki Kondo and
Mitaro Namiki},
title = {Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit,
Architecture, and System Software Design},
journal = {{IEICE} Trans. Electron.},
volume = {96-C},
number = {4},
pages = {404--412},
year = {2013},
url = {https://doi.org/10.1587/transele.E96.C.404},
doi = {10.1587/TRANSELE.E96.C.404},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/NakamuraWOUAKN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/Usami13,
author = {Kimiyoshi Usami},
title = {Foreword},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {96-A},
number = {12},
pages = {2457},
year = {2013},
url = {https://doi.org/10.1587/transfun.E96.A.2457},
doi = {10.1587/TRANSFUN.E96.A.2457},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/Usami13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AbeSUYT13,
author = {Shin{-}ya Abe and
Youhua Shi and
Kimiyoshi Usami and
Masao Yanagisawa and
Nozomu Togawa},
title = {Floorplan Driven Architecture and High-Level Synthesis Algorithm for
Dynamic Multiple Supply Voltages},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {96-A},
number = {12},
pages = {2597--2611},
year = {2013},
url = {https://doi.org/10.1587/transfun.E96.A.2597},
doi = {10.1587/TRANSFUN.E96.A.2597},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/AbeSUYT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/MiuraKTMKASNUKN13,
author = {Noriyuki Miura and
Yusuke Koizumi and
Yasuhiro Take and
Hiroki Matsutani and
Tadahiro Kuroda and
Hideharu Amano and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
title = {A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface},
journal = {{IEEE} Micro},
volume = {33},
number = {6},
pages = {6--15},
year = {2013},
url = {https://doi.org/10.1109/MM.2013.112},
doi = {10.1109/MM.2013.112},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/micro/MiuraKTMKASNUKN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/MiuraKSTMKASNUK13,
author = {Noriyuki Miura and
Yusuke Koizumi and
Eiichi Sasaki and
Yasuhiro Take and
Hiroki Matsutani and
Tadahiro Kuroda and
Hideharu Amano and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
title = {A scalable 3D heterogeneous multi-core processor with inductive-coupling
thruchip interface},
booktitle = {2013 {IEEE} Symposium on Low-Power and High-Speed Chips, {COOL} Chips
XVI, Yokohama, Japan, April 17-19, 2013},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/CoolChips.2013.6547916},
doi = {10.1109/COOLCHIPS.2013.6547916},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/MiuraKSTMKASNUK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KoizumiMTMKASNUKN13,
author = {Yusuke Koizumi and
Noriyuki Miura and
Yasuhiro Take and
Hiroki Matsutani and
Tadahiro Kuroda and
Hideharu Amano and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
title = {Demonstration of a heterogeneous multi-core processor with 3-D inductive
coupling links},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645628},
doi = {10.1109/FPL.2013.6645628},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KoizumiMTMKASNUKN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/MiuraKSTMKASNUK13,
author = {Noriyuki Miura and
Yusuke Koizumi and
Eiichi Sasaki and
Yasuhiro Take and
Hiroki Matsutani and
Tadahiro Kuroda and
Hideharu Amano and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
title = {A scalable 3D heterogeneous multi-core processor with inductive-coupling
thruchip interface},
booktitle = {2013 {IEEE} Hot Chips 25 Symposium (HCS), Stanford University, CA,
USA, August 25-27, 2013},
pages = {1},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2013.7478328},
doi = {10.1109/HOTCHIPS.2013.7478328},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hotchips/MiuraKSTMKASNUK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/AbeSUYT13,
author = {Shin{-}ya Abe and
Youhua Shi and
Kimiyoshi Usami and
Masao Yanagisawa and
Nozomu Togawa},
title = {An energy-efficient high-level synthesis algorithm incorporating interconnection
delays and dynamic multiple supply voltages},
booktitle = {2013 International Symposium on {VLSI} Design, Automation, and Test,
{VLSI-DAT} 2013, Hsinchu, Taiwan, April 22-24, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLDI-DAT.2013.6533808},
doi = {10.1109/VLDI-DAT.2013.6533808},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/AbeSUYT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MatsutaniHKUNA12,
author = {Hiroki Matsutani and
Yuto Hirata and
Michihiro Koibuchi and
Kimiyoshi Usami and
Hiroshi Nakamura and
Hideharu Amano},
title = {A multi-Vdd dynamic variable-pipeline on-chip router for CMPs},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {407--412},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6164982},
doi = {10.1109/ASPDAC.2012.6164982},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/MatsutaniHKUNA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/WangOIUA12,
author = {Weihan Wang and
Yuya Ohta and
Yoshifumi Ishii and
Kimiyoshi Usami and
Hideharu Amano},
editor = {Hiroaki Kobayashi and
Makoto Ikeda and
Fumio Arakawa},
title = {Trade-off analysis of fine-grained power gating methods for functional
units in a {CPU}},
booktitle = {2012 {IEEE} Symposium on Low-Power and High-Speed Chips, {COOL} Chips
XV, Yokohama, Japan, April 18-20, 2012},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/COOLChips.2012.6216587},
doi = {10.1109/COOLCHIPS.2012.6216587},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/WangOIUA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KoizumiSAMTKSNUKN12,
author = {Yusuke Koizumi and
Eiichi Sasaki and
Hideharu Amano and
Hiroki Matsutani and
Yasuhiro Take and
Tadahiro Kuroda and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {CMA-Cube: {A} scalable reconfigurable accelerator with 3-D wireless
inductive coupling interconnect},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {543--546},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339375},
doi = {10.1109/FPL.2012.6339375},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KoizumiSAMTKSNUKN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/KoizumiAMMKSNUKN12,
author = {Yusuke Koizumi and
Hideharu Amano and
Hiroki Matsutani and
Noriyuki Miura and
Tadahiro Kuroda and
Ryuichi Sakamoto and
Mitaro Namiki and
Kimiyoshi Usami and
Masaaki Kondo and
Hiroshi Nakamura},
title = {Dynamic power control with a heterogeneous multi-core system using
a 3-D wireless inductive coupling interconnect},
booktitle = {2012 International Conference on Field-Programmable Technology, {FPT}
2012, Seoul, Korea (South), December 10-12, 2012},
pages = {293--296},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPT.2012.6412150},
doi = {10.1109/FPT.2012.6412150},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/KoizumiAMMKSNUKN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/TakedaMUN12,
author = {Seidai Takeda and
Shinobu Miwa and
Kimiyoshi Usami and
Hiroshi Nakamura},
editor = {Erik Brunvard and
Ken Stevens and
Joseph R. Cavallaro and
Tong Zhang},
title = {Stepwise sleep depth control for run-time leakage power saving},
booktitle = {Great Lakes Symposium on {VLSI} 2012, GLSVLSI'12, Salt Lake City,
UT, USA, May 3-4, 2012},
pages = {233--238},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2206781.2206838},
doi = {10.1145/2206781.2206838},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/TakedaMUN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/TakedaMUN12,
author = {Seidai Takeda and
Shinobu Miwa and
Kimiyoshi Usami and
Hiroshi Nakamura},
editor = {Keith A. Bowman and
Kamesh V. Gadepally and
Pallab Chatterjee and
Mark M. Budnik and
Lalitha Immaneni},
title = {Efficient leakage power saving by sleep depth controlling for Multi-mode
Power Gating},
booktitle = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
2012, Santa Clara, CA, USA, March 19-21, 2012},
pages = {625--632},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISQED.2012.6187558},
doi = {10.1109/ISQED.2012.6187558},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/TakedaMUN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/NakamuraMKUA12,
author = {Takeo Nakamura and
Hiroki Matsutani and
Michihiro Koibuchi and
Kimiyoshi Usami and
Hideharu Amano},
title = {Fine-Grained Power Control Using {A} Multi-Voltage Variable Pipeline
Router},
booktitle = {{IEEE} 6th International Symposium on Embedded Multicore/Manycore
SoCs, MCSoC 2012, Fukushima, Japan, September 20-22, 2012},
pages = {59--66},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/MCSoC.2012.38},
doi = {10.1109/MCSOC.2012.38},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/NakamuraMKUA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/crc/SasakiAUKNN12,
author = {Hiroshi Sasaki and
Hideharu Amano and
Kimiyoshi Usami and
Masaaki Kondo and
Mitaro Namiki and
Hiroshi Nakamura},
editor = {Ishfaq Ahmad and
Sanjay Ranka},
title = {Geyser},
booktitle = {Handbook of Energy-Aware and Green Computing - Two Volume Set},
pages = {49--65},
publisher = {Chapman and Hall/CRC},
year = {2012},
url = {http://www.crcnetbase.com/doi/abs/10.1201/b16631-5},
doi = {10.1201/B16631-5},
timestamp = {Fri, 17 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/crc/SasakiAUKNN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TakedaKNU11,
author = {Seidai Takeda and
Kyundong Kim and
Hiroshi Nakamura and
Kimiyoshi Usami},
title = {Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering
Input Vector Pattern and Non-linear Current Model},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {94-A},
number = {12},
pages = {2499--2509},
year = {2011},
url = {https://doi.org/10.1587/transfun.E94.A.2499},
doi = {10.1587/TRANSFUN.E94.A.2499},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/TakedaKNU11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/LeiIUNKNA11,
author = {Zhao Lei and
Daisuke Ikebuchi and
Kimiyoshi Usami and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura and
Hideharu Amano},
title = {Design and Implementation Fine-grained Power Gating on Microprocessor
Functional Units},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {182--192},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.182},
doi = {10.2197/IPSJTSLDM.4.182},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/LeiIUNKNA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/OzakiYISIANUNK11,
author = {Nobuaki Ozaki and
Yoshihiro Yasuda and
Mai Izawa and
Yoshiki Saito and
Daisuke Ikebuchi and
Hideharu Amano and
Hiroshi Nakamura and
Kimiyoshi Usami and
Mitaro Namiki and
Masaaki Kondo},
title = {Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips},
journal = {{IEEE} Micro},
volume = {31},
number = {6},
pages = {6--18},
year = {2011},
url = {https://doi.org/10.1109/MM.2011.94},
doi = {10.1109/MM.2011.94},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/micro/OzakiYISIANUNK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MatsutaniKIUNA11,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Daisuke Ikebuchi and
Kimiyoshi Usami and
Hiroshi Nakamura and
Hideharu Amano},
title = {Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time
Power-Gating Routers for CMPs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {4},
pages = {520--533},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2110470},
doi = {10.1109/TCAD.2011.2110470},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MatsutaniKIUNA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/YamamotoHHKAU11,
author = {Tatsuya Yamamoto and
Kazuei Hironaka and
Yuki Hayakawa and
Masayuki Kimura and
Hideharu Amano and
Kimiyoshi Usami},
editor = {Andreas Koch and
Ram Krishnamurthy and
John McAllister and
Roger F. Woods and
Tarek A. El{-}Ghazawi},
title = {Dynamic V\({}_{\mbox{DD}}\) Switching Technique and Mapping Optimization
in Dynamically Reconfigurable Processor for Efficient Energy Reduction},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications -
7th International Symposium, {ARC} 2011, Belfast, UK, March 23-25,
2011. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {6578},
pages = {230--241},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-19475-7\_24},
doi = {10.1007/978-3-642-19475-7\_24},
timestamp = {Fri, 25 Feb 2022 16:33:50 +0100},
biburl = {https://dblp.org/rec/conf/arc/YamamotoHHKAU11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhaoISKSKAKHUMUKNTNK11,
author = {Lei Zhao and
Daisuke Ikebuchi and
Yoshiki Saito and
M. Kamata and
Naomi Seki and
Yu Kojima and
Hideharu Amano and
Satoshi Koyama and
Tatsunori Hashida and
Y. Umahashi and
D. Masuda and
Kimiyoshi Usami and
Keiji Kimura and
Mitaro Namiki and
Seidai Takeda and
Hiroshi Nakamura and
Masaaki Kondo},
title = {Geyser-2: The second prototype {CPU} with fine-grained run-time power
gating},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {87--88},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722310},
doi = {10.1109/ASPDAC.2011.5722310},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ZhaoISKSKAKHUMUKNTNK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/OzakiUANNK11,
author = {Nobuaki Ozaki and
Kimiyoshi Usami and
Hideharu Amano and
Mitaro Namiki and
Hiroshi Nakamura and
Masaaki Kondo},
title = {SLD-1(Silent Large Datapath): {A} ultra low power reconfigurable accelerator},
booktitle = {2011 {IEEE} Symposium on Low-Power and High-Speed Chips, Cool Chips
XIV, Yokohama, Japan, 20-22 April, 2011},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/COOLCHIPS.2011.5890918},
doi = {10.1109/COOLCHIPS.2011.5890918},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/OzakiUANNK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/OzakiYSIKANUNK11,
author = {Nobuaki Ozaki and
Yoshihiro Yasuda and
Yoshiki Saito and
Daisuke Ikebuchi and
Masayuki Kimura and
Hideharu Amano and
Hiroshi Nakamura and
Kimiyoshi Usami and
Mitaro Namiki and
Masaaki Kondo},
editor = {Russell Tessier},
title = {Cool Mega-Array: {A} highly energy efficient reconfigurable accelerator},
booktitle = {2011 International Conference on Field-Programmable Technology, {FPT}
2011, New Delhi, India, December 12-14, 2011},
pages = {1--8},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/FPT.2011.6132668},
doi = {10.1109/FPT.2011.6132668},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/OzakiYSIKANUNK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/UsamiGMKIAN11,
author = {Kimiyoshi Usami and
Yuya Goto and
Kensaku Matsunaga and
Satoshi Koyama and
Daisuke Ikebuchi and
Hideharu Amano and
Hiroshi Nakamura},
editor = {Naehyuck Chang and
Hiroshi Nakamura and
Koji Inoue and
Kenichi Osada and
Massimo Poncino},
title = {On-chip detection methodology for break-even time of power gated function
units},
booktitle = {Proceedings of the 2011 International Symposium on Low Power Electronics
and Design, 2011, Fukuoka, Japan, August 1-3, 2011},
pages = {241--246},
publisher = {{IEEE/ACM}},
year = {2011},
url = {http://portal.acm.org/citation.cfm?id=2016858\&\#38;CFID=34981777\&\#38;CFTOKEN=25607807},
timestamp = {Mon, 13 Aug 2012 09:40:34 +0200},
biburl = {https://dblp.org/rec/conf/islped/UsamiGMKIAN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/IkebuchiSKKZASKHUMUTNNK10,
author = {Daisuke Ikebuchi and
Naomi Seki and
Yu Kojima and
M. Kamata and
Lei Zhao and
Hideharu Amano and
Toshiaki Shirai and
Satoshi Koyama and
Tatsunori Hashida and
Y. Umahashi and
Hiroki Masuda and
Kimiyoshi Usami and
Seidai Takeda and
Hiroshi Nakamura and
Mitaro Namiki and
Masaaki Kondo},
title = {Geyser-1: a {MIPS} {R3000} {CPU} core with fine-grained run-time power
gating},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {369--370},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419857},
doi = {10.1109/ASPDAC.2010.5419857},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/IkebuchiSKKZASKHUMUTNNK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/UsamiHKYIANKN10,
author = {Kimiyoshi Usami and
Tatsunori Hashida and
Satoshi Koyama and
Tatsuya Yamamoto and
Daisuke Ikebuchi and
Hideharu Amano and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura},
title = {Adaptive power gating for function units in a microprocessor},
booktitle = {11th International Symposium on Quality of Electronic Design {(ISQED}
2010), 22-24 March 2010, San Jose, CA, {USA}},
pages = {29--37},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISQED.2010.5450407},
doi = {10.1109/ISQED.2010.5450407},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/UsamiHKYIANKN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/MatsutaniKIUNA10,
author = {Hiroki Matsutani and
Michihiro Koibuchi and
Daisuke Ikebuchi and
Kimiyoshi Usami and
Hiroshi Nakamura and
Hideharu Amano},
title = {Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs},
booktitle = {{NOCS} 2010, Fourth {ACM/IEEE} International Symposium on Networks-on-Chip,
Grenoble, France, May 3-6, 2010},
pages = {61--68},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/NOCS.2010.16},
doi = {10.1109/NOCS.2010.16},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nocs/MatsutaniKIUNA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arcs/LeiXSYHUA09,
author = {Lei Zhao and
Hui Xu and
Naomi Seki and
Yoshiki Saito and
Yohei Hasegawa and
Kimiyoshi Usami and
Hideharu Amano},
editor = {Mladen Berekovic and
Christian M{\"{u}}ller{-}Schloer and
Christian Hochberger and
Stephan Wong},
title = {Cache Controller Design on Ultra Low Leakage Embedded Processors},
booktitle = {Architecture of Computing Systems - {ARCS} 2009, 22nd International
Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5455},
pages = {171--182},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-642-00454-4\_18},
doi = {10.1007/978-3-642-00454-4\_18},
timestamp = {Tue, 14 May 2019 10:00:52 +0200},
biburl = {https://dblp.org/rec/conf/arcs/LeiXSYHUA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/UsamiSHMTNSANIKN09,
author = {Kimiyoshi Usami and
Toshiaki Shirai and
Tatsunori Hashida and
Hiroki Masuda and
Seidai Takeda and
Mitsutaka Nakata and
Naomi Seki and
Hideharu Amano and
Mitaro Namiki and
Masashi Imai and
Masaaki Kondo and
Hiroshi Nakamura},
title = {Design and Implementation of Fine-Grain Power Gating with Ground Bounce
Suppression},
booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
The 22nd International Conference on {VLSI} Design, New Delhi, India,
5-9 January 2009},
pages = {381--386},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VLSI.Design.2009.63},
doi = {10.1109/VLSI.DESIGN.2009.63},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/UsamiSHMTNSANIKN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/FrenkilCU08,
author = {Jerry Frenkil and
Ken Choi and
Kimiyoshi Usami},
editor = {Donatella Sciuto},
title = {Power Gating for Ultra-low Leakage: Physics, Design, and Analysis},
booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany,
March 10-14, 2008},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1109/DATE.2008.4484640},
doi = {10.1109/DATE.2008.4484640},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/FrenkilCU08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SaitoSNNHTKNTUA08,
author = {Yoshiki Saito and
Tomoaki Shirai and
Takuro Nakamura and
Takashi Nishimura and
Yohei Hasegawa and
Satoshi Tsutsumi and
Toshihiro Kashima and
Mitsutaka Nakata and
Seidai Takeda and
Kimiyoshi Usami and
Hideharu Amano},
editor = {Tarek A. El{-}Ghazawi and
Yao{-}Wen Chang and
Juinn{-}Dar Huang and
Proshanta Saha},
title = {Leakage power reduction for coarse grained dynamically reconfigurable
processor arrays with fine grained Power Gating technique},
booktitle = {2008 International Conference on Field-Programmable Technology, {FPT}
2008, Taipei, Taiwan, December 7-10, 2008},
pages = {329--332},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPT.2008.4762410},
doi = {10.1109/FPT.2008.4762410},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/SaitoSNNHTKNTUA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/SekiZKIKHAKTSNUSKNKN08,
author = {Naomi Seki and
Lei Zhao and
Jo Kei and
Daisuke Ikebuchi and
Yu Kojima and
Yohei Hasegawa and
Hideharu Amano and
Toshihiro Kashima and
Seidai Takeda and
Toshiaki Shirai and
Mitsutaka Nakata and
Kimiyoshi Usami and
Tetsuya Sunata and
Jun Kanai and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura},
title = {A fine-grain dynamic sleep control scheme in {MIPS} {R3000}},
booktitle = {26th International Conference on Computer Design, {ICCD} 2008, 12-15
October 2008, Lake Tahoe, CA, USA, Proceedings},
pages = {612--617},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCD.2008.4751924},
doi = {10.1109/ICCD.2008.4751924},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/SekiZKIKHAKTSNUSKNKN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Usami07,
author = {Kimiyoshi Usami},
title = {Overview on Low Power SoC Design Technology},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {634--636},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358057},
doi = {10.1109/ASPDAC.2007.358057},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/Usami07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/OhkuboU06,
author = {Naoaki Ohkubo and
Kimiyoshi Usami},
title = {Delay Modeling and Critical-Path Delay Calculation for {MTCMOS} Circuits},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {89-A},
number = {12},
pages = {3482--3490},
year = {2006},
url = {https://doi.org/10.1093/ietfec/e89-a.12.3482},
doi = {10.1093/IETFEC/E89-A.12.3482},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/OhkuboU06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/OhkuboU06,
author = {Naoaki Ohkubo and
Kimiyoshi Usami},
editor = {Fumiyasu Hirose},
title = {Delay modeling and static timing analysis for {MTCMOS} circuits},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {570--575},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594746},
doi = {10.1109/ASPDAC.2006.1594746},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/OhkuboU06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/UsamiO06,
author = {Kimiyoshi Usami and
Naoaki Ohkubo},
title = {A Design Approach for Fine-grained Run-Time Power Gating using Locally
Extracted Sleep Signals},
booktitle = {24th International Conference on Computer Design {(ICCD} 2006), 1-4
October 2006, San Jose, CA, {USA}},
pages = {155--161},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ICCD.2006.4380809},
doi = {10.1109/ICCD.2006.4380809},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/UsamiO06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/UsamiKKSF02,
author = {Kimiyoshi Usami and
Naoyuki Kawabe and
Masayuki Koizumi and
Katsuhiro Seta and
Toshiyuki Furusawa},
title = {Selective Multi-Threshold Technique for High-Performance and Low-Standby
Applications},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {85-A},
number = {12},
pages = {2667--2673},
year = {2002},
url = {http://search.ieice.org/bin/summary.php?id=e85-a\_12\_2667},
timestamp = {Wed, 09 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/UsamiKKSF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/QuKUP02,
author = {Gang Qu and
Naoyuki Kawabe and
Kimiyoshi Usami and
Miodrag Potkonjak},
title = {Code Coverage-Based Power Estimation Techniques for Microprocessors},
journal = {J. Circuits Syst. Comput.},
volume = {11},
number = {5},
pages = {557},
year = {2002},
url = {https://doi.org/10.1142/S0218126602000616},
doi = {10.1142/S0218126602000616},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcsc/QuKUP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/UsamiKKSF02,
author = {Kimiyoshi Usami and
Naoyuki Kawabe and
Masayuki Koizumi and
Katsuhiro Seta and
Toshiyuki Furusawa},
editor = {Vivek De and
Mary Jane Irwin and
Ingrid Verbauwhede and
Christian Piguet},
title = {Automated selective multi-threshold design for ultra-low standby applications},
booktitle = {Proceedings of the 2002 International Symposium on Low Power Electronics
and Design, 2002, Monterey, California, USA, August 12-14, 2002},
pages = {202--206},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/566408.566458},
doi = {10.1145/566408.566458},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/UsamiKKSF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/UsamiI00,
author = {Kimiyoshi Usami and
Mutsunori Igarashi},
title = {Low-power design methodology and applications utilizing dual supply
voltages},
booktitle = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
Conference 2000, Yokohama, Japan},
pages = {123--128},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/368434.368590},
doi = {10.1145/368434.368590},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/UsamiI00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KawabeU00,
author = {Naoyuki Kawabe and
Kimiyoshi Usami},
title = {Low-power technique for on-chip memory using biased partitioning and
access concentration},
booktitle = {Proceedings of the {IEEE} 2000 Custom Integrated Circuits Conference,
{CICC} 2000, Orlando, FL, USA, May 21-24, 2000},
pages = {275--278},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/CICC.2000.852665},
doi = {10.1109/CICC.2000.852665},
timestamp = {Mon, 10 Oct 2022 09:13:21 +0200},
biburl = {https://dblp.org/rec/conf/cicc/KawabeU00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/QuKUP00,
author = {Gang Qu and
Naoyuki Kawabe and
Kimiyoshi Usami and
Miodrag Potkonjak},
editor = {Giovanni De Micheli},
title = {Function-level power estimation methodology for microprocessors},
booktitle = {Proceedings of the 37th Conference on Design Automation, Los Angeles,
CA, USA, June 5-9, 2000},
pages = {810--813},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/337292.337786},
doi = {10.1145/337292.337786},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/QuKUP00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/UsamiIMIKIN98,
author = {Kimiyoshi Usami and
Mutsunori Igarashi and
Fumihiro Minami and
Takashi Ishikawa and
Masahiro Kanazawa and
Makoto Ichida and
Kazutaka Nogami},
title = {Automated low-power technique exploiting multiple supply voltages
applied to a media processor},
journal = {{IEEE} J. Solid State Circuits},
volume = {33},
number = {3},
pages = {463--472},
year = {1998},
url = {https://doi.org/10.1109/4.661212},
doi = {10.1109/4.661212},
timestamp = {Tue, 05 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/UsamiIMIKIN98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TakahashiHNAFHM98,
author = {Masafumi Takahashi and
Mototsugu Hamada and
Tsuyoshi Nishikawa and
Hideho Arakida and
Tetsuya Fujita and
Fumitoshi Hatori and
Shinji Mita and
Kojiro Suzuki and
Akihiko Chiba and
Toshihiro Terazawa and
Fumihiko Sano and
Yoshinori Watanabe and
Kimiyoshi Usami and
Mutsunori Igarashi and
Takashi Ishikawa and
Masahiro Kanazawa and
Tadahiro Kuroda and
Tohru Furuyama},
title = {A 60-mW {MPEG4} video codec using clustered voltage scaling with variable
supply-voltage scheme},
journal = {{IEEE} J. Solid State Circuits},
volume = {33},
number = {11},
pages = {1772--1780},
year = {1998},
url = {https://doi.org/10.1109/4.726575},
doi = {10.1109/4.726575},
timestamp = {Tue, 05 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/TakahashiHNAFHM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KitaharaMUUNMM98,
author = {Takeshi Kitahara and
Fumihiro Minami and
Toshiaki Ueda and
Kimiyoshi Usami and
Seiichi Nishio and
Masami Murakata and
Takashi Mitsuhashi},
title = {A Clock-Gating Method for Low-Power {LSI} Design},
booktitle = {Proceedings of the {ASP-DAC} '98, Asia and South Pacific Design Automation
Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13,
1998},
pages = {307--312},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/ASPDAC.1998.669476},
doi = {10.1109/ASPDAC.1998.669476},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KitaharaMUUNMM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/HamadaTACTIKIUK98,
author = {Mototsugu Hamada and
Masafumi Takahashi and
Hideho Arakida and
Akihiko Chiba and
Toshihiro Terazawa and
Takashi Ishikawa and
Masahiro Kanazawa and
Mutsunori Igarashi and
Kimiyoshi Usami and
Tadahiro Kuroda},
title = {A top-down low power design technique using clustered voltage scaling
with variable supply-voltage scheme},
booktitle = {Proceedings of the {IEEE} 1998 Custom Integrated Circuits Conference,
{CICC} 1998, Santa Clara, CA, USA, May 11-14, 1998},
pages = {495--498},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/CICC.1998.695026},
doi = {10.1109/CICC.1998.695026},
timestamp = {Fri, 07 Jul 2023 11:00:51 +0200},
biburl = {https://dblp.org/rec/conf/cicc/HamadaTACTIKIUK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/UsamiIIKTHATK98,
author = {Kimiyoshi Usami and
Mutsunori Igarashi and
Takashi Ishikawa and
Masahiro Kanazawa and
Masafumi Takahashi and
Mototsugu Hamada and
Hideho Arakida and
Toshihiro Terazawa and
Tadahiro Kuroda},
editor = {Basant R. Chawla and
Randal E. Bryant and
Jan M. Rabaey},
title = {Design Methodology of Ultra Low-Power {MPEG4} Codec Core Exploiting
Voltage Scaling Techniques},
booktitle = {Proceedings of the 35th Conference on Design Automation, Moscone center,
San Francico, California, USA, June 15-19, 1998},
pages = {483--488},
publisher = {{ACM} Press},
year = {1998},
url = {https://doi.org/10.1145/277044.277178},
doi = {10.1145/277044.277178},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/UsamiIIKTHATK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/IgarashiUNMKATMIKSIH97,
author = {Mutsunori Igarashi and
Kimiyoshi Usami and
Kazutaka Nogami and
Fumihiro Minami and
Yukio Kawasaki and
Takahiro Aoki and
Midori Takano and
Chiharo Mizuno and
Takashi Ishikawa and
Masahiro Kanazawa and
Shinji Sonoda and
Makoto Ichida and
Naoyuki Hatanaka},
editor = {Brock Barton and
Massoud Pedram and
Anantha P. Chandrakasan and
Sayfe Kiaei},
title = {A low-power design method using multiple supply voltages},
booktitle = {Proceedings of the 1997 International Symposium on Low Power Electronics
and Design, 1997, Monterey, California, USA, August 18-20, 1997},
pages = {36--41},
publisher = {{ACM}},
year = {1997},
url = {https://doi.org/10.1145/263272.263279},
doi = {10.1145/263272.263279},
timestamp = {Mon, 27 Sep 2021 11:47:11 +0200},
biburl = {https://dblp.org/rec/conf/islped/IgarashiUNMKATMIKSIH97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/UsamiH95,
author = {Kimiyoshi Usami and
Mark Horowitz},
editor = {Massoud Pedram and
Robert W. Brodersen and
Kurt Keutzer},
title = {Clustered voltage scaling technique for low-power design},
booktitle = {Proceedings of the 1995 International Symposium on Low Power Design
1995, Dana Point, California, USA, April 23-26, 1995},
pages = {3--8},
publisher = {{ACM}},
year = {1995},
url = {https://doi.org/10.1145/224081.224083},
doi = {10.1145/224081.224083},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/UsamiH95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MatsumotoWUSHM90,
author = {Nobu Matsumoto and
Yoko Watanabe and
Kimiyoshi Usami and
Yukio Sugeno and
Hiroshi Hatada and
Shojiro Mori},
editor = {Richard C. Smith},
title = {Datapath Generator Based on Gate-Level Symbolic Layout},
booktitle = {Proceedings of the 27th {ACM/IEEE} Design Automation Conference. Orlando,
Florida, USA, June 24-28, 1990},
pages = {388--393},
publisher = {{IEEE} Computer Society Press},
year = {1990},
url = {https://doi.org/10.1145/123186.123314},
doi = {10.1145/123186.123314},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MatsumotoWUSHM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-03-24 02:54 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
