BibTeX records: Yasumasa Tsukamoto

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@article{DBLP:journals/ieiceta/IgarashiUTYTSK21,
  author       = {Mitsuhiko Igarashi and
                  Yuuki Uchida and
                  Yoshio Takazawa and
                  Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Koji Shibutani and
                  Kazutoshi Kobayashi},
  title        = {An Analysis of Local {BTI} Variation with Ring-Oscillator in Advanced
                  Processes and Its Impact on Logic Circuit and {SRAM}},
  journal      = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
  volume       = {104-A},
  number       = {11},
  pages        = {1536--1545},
  year         = {2021},
  url          = {https://doi.org/10.1587/transfun.2020kep0017},
  doi          = {10.1587/TRANSFUN.2020KEP0017},
  timestamp    = {Thu, 12 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ieiceta/IgarashiUTYTSK21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/YabuuchiMTT20,
  author       = {Makoto Yabuuchi and
                  Masao Morimoto and
                  Yasumasa Tsukamoto and
                  Shinji Tanaka},
  title        = {A 7nm Fin-FET 4.04-Mb/mm2 {TCAM} with Improved Electromigration Reliability
                  Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line
                  Amplifier},
  booktitle    = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
                  HI, USA, June 16-19, 2020},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/VLSICircuits18222.2020.9162775},
  doi          = {10.1109/VLSICIRCUITS18222.2020.9162775},
  timestamp    = {Mon, 24 Aug 2020 16:22:01 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/YabuuchiMTT20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/irps/IgarashiUTYTS19,
  author       = {Mitsuhiko Igarashi and
                  Yuuki Uchida and
                  Yoshio Takazawa and
                  Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Koji Shibutani},
  title        = {Study of Local {BTI} Variation and its Impact on Logic Circuit and
                  {SRAM} in 7 nm Fin-FET Process},
  booktitle    = {{IEEE} International Reliability Physics Symposium, {IRPS} 2019, Monterey,
                  CA, USA, March 31 - April 4, 2019},
  pages        = {1--6},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/IRPS.2019.8720508},
  doi          = {10.1109/IRPS.2019.8720508},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/irps/IgarashiUTYTS19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/YabuuchiTFTSN18,
  author       = {Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Hidehiro Fujiwara and
                  Miki Tanaka and
                  Shinji Tanaka and
                  Koji Nii},
  title        = {A 28-nm 1R1W Two-Port 8T {SRAM} Macro With Screening Circuitry Against
                  Read Disturbance and Wordline Coupling Noise Failures},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {26},
  number       = {11},
  pages        = {2335--2344},
  year         = {2018},
  url          = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2864267},
  doi          = {10.1109/TVLSI.2018.2864267},
  timestamp    = {Mon, 24 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/YabuuchiTFTSN18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asscc/IgarashiUTTSN18,
  author       = {Mitsuhiko Igarashi and
                  Yuuki Uchida and
                  Yoshio Takazawa and
                  Yasumasa Tsukamoto and
                  Koji Shibutani and
                  Koji Nii},
  title        = {A Fully Standard-Cell Based On-Chip {BTI} and {HCI} Monitor with 6.2x
                  {BTI} sensitivity and 3.6x {HCI} sensitivity at 7 nm Fin-FET Process},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
                  Taiwan, November 5-7, 2018},
  pages        = {195--196},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASSCC.2018.8579303},
  doi          = {10.1109/ASSCC.2018.8579303},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asscc/IgarashiUTTSN18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/irps/IgarashiUTTSN18,
  author       = {Mitsuhiko Igarashi and
                  Yuuki Uchida and
                  Yoshio Takazawa and
                  Yasumasa Tsukamoto and
                  Koji Shibutani and
                  Koji Nii},
  title        = {Study of impact of BTI's local layout effect including recovery effect
                  on various standard-cells in 10nm FinFET},
  booktitle    = {{IEEE} International Reliability Physics Symposium, {IRPS} 2018, Burlingame,
                  CA, USA, March 11-15, 2018},
  pages        = {1},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/IRPS.2018.8353654},
  doi          = {10.1109/IRPS.2018.8353654},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/irps/IgarashiUTTSN18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asscc/IgarashiTTTS17,
  author       = {Mitsuhiko Igarashi and
                  Yoshio Takazawa and
                  Yasumasa Tsukamoto and
                  Kan Takeuchi and
                  Koji Shibutani},
  title        = {{NBTI/PBTI} separated {BTI} monitor with 4.2x sensitivity by standard
                  cell based unbalanced ring oscillator},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
                  Korea (South), November 6-8, 2017},
  pages        = {201--204},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ASSCC.2017.8240251},
  doi          = {10.1109/ASSCC.2017.8240251},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/asscc/IgarashiTTTS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asscc/IshiiYSMTYSSTN16,
  author       = {Yuichiro Ishii and
                  Makoto Yabuuchi and
                  Yohei Sawada and
                  Masao Morimoto and
                  Yasumasa Tsukamoto and
                  Yuta Yoshida and
                  Ken Shibata and
                  Toshiaki Sano and
                  Shinji Tanaka and
                  Koji Nii},
  title        = {A 5.92-Mb/mm\({}^{\mbox{2}}\) 28-nm pseudo 2-read/write dual-port
                  {SRAM} using double pumping circuitry},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
                  Japan, November 7-9, 2016},
  pages        = {17--20},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ASSCC.2016.7844124},
  doi          = {10.1109/ASSCC.2016.7844124},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/asscc/IshiiYSMTYSSTN16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/TsukamotoMYTN15,
  author       = {Yasumasa Tsukamoto and
                  Masao Morimoto and
                  Makoto Yabuuchi and
                  Miki Tanaka and
                  Koji Nii},
  title        = {1.8 Mbit/mm\({}^{\mbox{2}}\) ternary-CAM macro with 484 ps search
                  access time in 16 nm Fin-FET bulk {CMOS} technology},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
                  2015},
  pages        = {274},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSIC.2015.7231286},
  doi          = {10.1109/VLSIC.2015.7231286},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/TsukamotoMYTN15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/UmemotoNIYOTTTMMY14,
  author       = {Yukiko Umemoto and
                  Koji Nii and
                  Jiro Ishikawa and
                  Makoto Yabuuchi and
                  Kazuyoshi Okamoto and
                  Yasumasa Tsukamoto and
                  Shinji Tanaka and
                  Koji Tanaka and
                  Tetsuya Matsumura and
                  Kazutaka Mori and
                  Kazumasa Yanagisawa},
  title        = {28 nm 50{\%} Power-Reducing Contacted Mask Read Only Memory Macro
                  With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column
                  Source Bias Control Technique},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {22},
  number       = {3},
  pages        = {575--584},
  year         = {2014},
  url          = {https://doi.org/10.1109/TVLSI.2013.2246201},
  doi          = {10.1109/TVLSI.2013.2246201},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/UmemotoNIYOTTTMMY14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/YabuuchiTMTN14,
  author       = {Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Masao Morimoto and
                  Miki Tanaka and
                  Koji Nii},
  title        = {13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment
                  system for read/write assists},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {234--235},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757414},
  doi          = {10.1109/ISSCC.2014.6757414},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/YabuuchiTMTN14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/TanakaIYSTTNS14,
  author       = {Shinji Tanaka and
                  Yuichiro Ishii and
                  Makoto Yabuuchi and
                  Toshiaki Sano and
                  Koji Tanaka and
                  Yasumasa Tsukamoto and
                  Koji Nii and
                  Hirotoshi Sato},
  title        = {A 512-kb 1-GHz 28-nm partially write-assisted dual-port {SRAM} with
                  self-adjustable negative bias bitline},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
                  Honolulu, HI, USA, June 10-13, 2014},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/VLSIC.2014.6858411},
  doi          = {10.1109/VLSIC.2014.6858411},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/TanakaIYSTTNS14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/MaedaKMTTNS13,
  author       = {Noriaki Maeda and
                  Shigenobu Komatsu and
                  Masao Morimoto and
                  Koji Tanaka and
                  Yasumasa Tsukamoto and
                  Koji Nii and
                  Yasuhisa Shimazaki},
  title        = {A 0.41 {\(\mathrm{\mu}\)}A Standby Leakage 32 kb Embedded {SRAM} with
                  Low-Voltage Resume-Standby Utilizing All Digital Current Comparator
                  in 28 nm {HKMG} {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {48},
  number       = {4},
  pages        = {917--923},
  year         = {2013},
  url          = {https://doi.org/10.1109/JSSC.2012.2237571},
  doi          = {10.1109/JSSC.2012.2237571},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/MaedaKMTTNS13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cicc/YabuuchiFTTTN13,
  author       = {Makoto Yabuuchi and
                  Hidehiro Fujiwara and
                  Yasumasa Tsukamoto and
                  Miki Tanaka and
                  Shinji Tanaka and
                  Koji Nii},
  title        = {A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against
                  read disturb failure},
  booktitle    = {Proceedings of the {IEEE} 2013 Custom Integrated Circuits Conference,
                  {CICC} 2013, San Jose, CA, USA, September 22-25, 2013},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/CICC.2013.6658451},
  doi          = {10.1109/CICC.2013.6658451},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/YabuuchiFTTTN13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isqed/NiiYFTIMM13,
  author       = {Koji Nii and
                  Makoto Yabuuchi and
                  Hidehiro Fujiwara and
                  Yasumasa Tsukamoto and
                  Yuichiro Ishii and
                  Tetsuya Matsumura and
                  Yoshio Matsuda},
  title        = {A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53{\%} standby
                  leakage with multi-Vt asymmetric halo {MOS} and write assist circuitry},
  booktitle    = {International Symposium on Quality Electronic Design, {ISQED} 2013,
                  Santa Clara, CA, USA, March 4-6, 2013},
  pages        = {438--441},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISQED.2013.6523648},
  doi          = {10.1109/ISQED.2013.6523648},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isqed/NiiYFTIMM13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/ats/NiiTIYFO12,
  author       = {Koji Nii and
                  Yasumasa Tsukamoto and
                  Yuichiro Ishii and
                  Makoto Yabuuchi and
                  Hidehiro Fujiwara and
                  Kazuyoshi Okamoto},
  title        = {A Test Screening Method for 28 nm {HK/MG} Single-Port and Dual-Port
                  SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues},
  booktitle    = {21st {IEEE} Asian Test Symposium, {ATS} 2012, Niigata, Japan, November
                  19-22, 2012},
  pages        = {246--251},
  publisher    = {{IEEE} Computer Society},
  year         = {2012},
  url          = {https://doi.org/10.1109/ATS.2012.59},
  doi          = {10.1109/ATS.2012.59},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ats/NiiTIYFO12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isqed/TsukamotoYFNSL12,
  author       = {Yasumasa Tsukamoto and
                  Makoto Yabuuchi and
                  Hidehiro Fujiwara and
                  Koji Nii and
                  Changhwan Shin and
                  Tsu{-}Jae King Liu},
  editor       = {Keith A. Bowman and
                  Kamesh V. Gadepally and
                  Pallab Chatterjee and
                  Mark M. Budnik and
                  Lalitha Immaneni},
  title        = {Quasi-Planar Tri-gate {(QPT)} bulk {CMOS} technology for single-port
                  {SRAM} application},
  booktitle    = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
                  2012, Santa Clara, CA, USA, March 19-21, 2012},
  pages        = {270--274},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISQED.2012.6187505},
  doi          = {10.1109/ISQED.2012.6187505},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isqed/TsukamotoYFNSL12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isqed/KidaTK12,
  author       = {Takeshi Kida and
                  Yasumasa Tsukamoto and
                  Yuji Kihara},
  editor       = {Keith A. Bowman and
                  Kamesh V. Gadepally and
                  Pallab Chatterjee and
                  Mark M. Budnik and
                  Lalitha Immaneni},
  title        = {Optimization of importance sampling Monte Carlo using consecutive
                  mean-shift method and its application to {SRAM} dynamic stability
                  analysis},
  booktitle    = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
                  2012, Santa Clara, CA, USA, March 19-21, 2012},
  pages        = {572--579},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISQED.2012.6187551},
  doi          = {10.1109/ISQED.2012.6187551},
  timestamp    = {Thu, 25 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isqed/KidaTK12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/IshiiTNFYTTS12,
  author       = {Yuichiro Ishii and
                  Yasumasa Tsukamoto and
                  Koji Nii and
                  Hidehiro Fujiwara and
                  Makoto Yabuuchi and
                  Koji Tanaka and
                  Shinji Tanaka and
                  Yasuhisa Shimazaki},
  title        = {A 28nm 360ps-access-time two-port {SRAM} with a time-sharing scheme
                  to circumvent read disturbs},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {236--238},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6176991},
  doi          = {10.1109/ISSCC.2012.6176991},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/IshiiTNFYTTS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/FujiwaraYTNOKN12,
  author       = {Hidehiro Fujiwara and
                  Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Hirofumi Nakano and
                  Toru Owada and
                  Hiroyuki Kawai and
                  Koji Nii},
  editor       = {Ramalingam Sridhar and
                  Norbert Schuhmann and
                  Kaijian Shi},
  title        = {A stable chip-ID generating physical uncloneable function using random
                  address errors in {SRAM}},
  booktitle    = {{IEEE} 25th International {SOC} Conference, {SOCC} 2012, Niagara Falls,
                  NY, USA, September 12-14, 2012},
  pages        = {143--147},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/SOCC.2012.6398399},
  doi          = {10.1109/SOCC.2012.6398399},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/FujiwaraYTNOKN12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/IshiiFTTNKY11,
  author       = {Yuichiro Ishii and
                  Hidehiro Fujiwara and
                  Shinji Tanaka and
                  Yasumasa Tsukamoto and
                  Koji Nii and
                  Yuji Kihara and
                  Kazumasa Yanagisawa},
  title        = {A 28 nm Dual-Port {SRAM} Macro With Screening Circuitry Against Write-Read
                  Disturb Failure Issues},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {46},
  number       = {11},
  pages        = {2535--2544},
  year         = {2011},
  url          = {https://doi.org/10.1109/JSSC.2011.2164021},
  doi          = {10.1109/JSSC.2011.2164021},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/IshiiFTTNKY11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cicc/TsukamotoKYINTTK11,
  author       = {Yasumasa Tsukamoto and
                  Takeshi Kida and
                  T. Yamaki and
                  Yuichiro Ishii and
                  Koji Nii and
                  Koji Tanaka and
                  Shinji Tanaka and
                  Yuji Kihara},
  editor       = {Rakesh Patel and
                  Tom Andre and
                  Aurangzeb Khan},
  title        = {Dynamic stability in minimum operating voltage Vmin for single-port
                  and dual-port SRAMs},
  booktitle    = {2011 {IEEE} Custom Integrated Circuits Conference, {CICC} 2011, San
                  Jose, CA, USA, Sept. 19-21, 2011},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/CICC.2011.6055314},
  doi          = {10.1109/CICC.2011.6055314},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/TsukamotoKYINTTK11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/islped/YabuuchiTFTMIN11,
  author       = {Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Hidehiro Fujiwara and
                  Shigeki Tawa and
                  Koji Maekawa and
                  Motoshige Igarashi and
                  Koji Nii},
  editor       = {Naehyuck Chang and
                  Hiroshi Nakamura and
                  Koji Inoue and
                  Kenichi Osada and
                  Massimo Poncino},
  title        = {A dynamic body-biased {SRAM} with asymmetric halo implant MOSFETs},
  booktitle    = {Proceedings of the 2011 International Symposium on Low Power Electronics
                  and Design, 2011, Fukuoka, Japan, August 1-3, 2011},
  pages        = {285--290},
  publisher    = {{IEEE/ACM}},
  year         = {2011},
  url          = {http://portal.acm.org/citation.cfm?id=2016868\&\#38;CFID=34981777\&\#38;CFTOKEN=25607807},
  timestamp    = {Mon, 13 Aug 2012 09:40:34 +0200},
  biburl       = {https://dblp.org/rec/conf/islped/YabuuchiTFTMIN11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/NiiYTHIK10,
  author       = {Koji Nii and
                  Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Yuuichi Hirano and
                  Toshiaki Iwamatsu and
                  Yuji Kihara},
  title        = {A 0.5V 100MHz {PD-SOI} {SRAM} with enhanced read stability and write
                  margin by asymmetric {MOSFET} and forward body bias},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
                  Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
                  2010},
  pages        = {356--357},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSCC.2010.5433817},
  doi          = {10.1109/ISSCC.2010.5433817},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/NiiYTHIK10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/NiiTYMIUOMS09,
  author       = {Koji Nii and
                  Yasumasa Tsukamoto and
                  Makoto Yabuuchi and
                  Yasuhiro Masuda and
                  Susumu Imaoka and
                  Keiichi Usui and
                  Shigeki Ohbayashi and
                  Hiroshi Makino and
                  Hirofumi Shinohara},
  title        = {Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention
                  of Simultaneous Common-Row-Access},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {44},
  number       = {3},
  pages        = {977--986},
  year         = {2009},
  url          = {https://doi.org/10.1109/JSSC.2009.2013766},
  doi          = {10.1109/JSSC.2009.2013766},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/NiiTYMIUOMS09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/OhbayashiYKOIUY08,
  author       = {Shigeki Ohbayashi and
                  Makoto Yabuuchi and
                  Kazushi Kono and
                  Yuji Oda and
                  Susumu Imaoka and
                  Keiichi Usui and
                  Toshiaki Yonezu and
                  Takeshi Iwamoto and
                  Koji Nii and
                  Yasumasa Tsukamoto and
                  Masashi Arakawa and
                  Takahiro Uchida and
                  Masakazu Okada and
                  Atsushi Ishii and
                  Tsutomu Yoshihara and
                  Hiroshi Makino and
                  Koichiro Ishibashi and
                  Hirofumi Shinohara},
  title        = {A 65 nm Embedded {SRAM} With Wafer Level Burn-In Mode, Leak-Bit Redundancy
                  and Cu E-Trim Fuse for Known Good Die},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {43},
  number       = {1},
  pages        = {96--108},
  year         = {2008},
  url          = {https://doi.org/10.1109/JSSC.2007.908004},
  doi          = {10.1109/JSSC.2007.908004},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/OhbayashiYKOIUY08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/NiiYTOIMYITOHSO08,
  author       = {Koji Nii and
                  Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Shigeki Ohbayashi and
                  Susumu Imaoka and
                  Hiroshi Makino and
                  Yoshinobu Yamagami and
                  Satoshi Ishikura and
                  Toshio Terano and
                  Toshiyuki Oashi and
                  Keiji Hashimoto and
                  Akio Sebe and
                  Gen Okazaki and
                  Katsuji Satomi and
                  Hironori Akamatsu and
                  Hirofumi Shinohara},
  title        = {A 45-nm Bulk {CMOS} Embedded {SRAM} With Improved Immunity Against
                  Process and Temperature Variations},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {43},
  number       = {1},
  pages        = {180--191},
  year         = {2008},
  url          = {https://doi.org/10.1109/JSSC.2007.907998},
  doi          = {10.1109/JSSC.2007.907998},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/NiiYTOIMYITOHSO08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/IshikuraKTYKSNY08,
  author       = {Satoshi Ishikura and
                  Marefusa Kurumada and
                  Toshio Terano and
                  Yoshinobu Yamagami and
                  Naoki Kotani and
                  Katsuji Satomi and
                  Koji Nii and
                  Makoto Yabuuchi and
                  Yasumasa Tsukamoto and
                  Shigeki Ohbayashi and
                  Toshiyuki Oashi and
                  Hiroshi Makino and
                  Hirofumi Shinohara and
                  Hironori Akamatsu},
  title        = {A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique
                  With Immunity From Simultaneous {R/W} Access Issues},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {43},
  number       = {4},
  pages        = {938--945},
  year         = {2008},
  url          = {https://doi.org/10.1109/JSSC.2008.917568},
  doi          = {10.1109/JSSC.2008.917568},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/IshikuraKTYKSNY08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/OhbayashiYNTIOY07,
  author       = {Shigeki Ohbayashi and
                  Makoto Yabuuchi and
                  Koji Nii and
                  Yasumasa Tsukamoto and
                  Susumu Imaoka and
                  Yuji Oda and
                  Tsutomu Yoshihara and
                  Motoshige Igarashi and
                  Masahiko Takeuchi and
                  Hiroshi Kawashima and
                  Yasuo Yamaguchi and
                  Kazuhiro Tsukamoto and
                  Masahide Inuishi and
                  Hiroshi Makino and
                  Koichiro Ishibashi and
                  Hirofumi Shinohara},
  title        = {A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read
                  and Write Operation Stabilizing Circuits},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {42},
  number       = {4},
  pages        = {820--829},
  year         = {2007},
  url          = {https://doi.org/10.1109/JSSC.2007.891648},
  doi          = {10.1109/JSSC.2007.891648},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/OhbayashiYNTIOY07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/YabuuchiNTOIMYITOHSOSAS07,
  author       = {Makoto Yabuuchi and
                  Koji Nii and
                  Yasumasa Tsukamoto and
                  Shigeki Ohbayashi and
                  Susumu Imaoka and
                  Hiroshi Makino and
                  Yoshinobu Yamagami and
                  Satoshi Ishikura and
                  Toshio Terano and
                  Toshiyuki Oashi and
                  Keiji Hashimoto and
                  Akio Sebe and
                  Gen Okazaki and
                  Katsuji Satomi and
                  Hironori Akamatsu and
                  Hirofumi Shinohara},
  title        = {A 45nm Low-Standby-Power Embedded {SRAM} with Improved Immunity Against
                  Process and Temperature Variations},
  booktitle    = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2007, Digest of Technical Papers, San Francisco, CA, USA, February
                  11-15, 2007},
  pages        = {326--606},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/ISSCC.2007.373426},
  doi          = {10.1109/ISSCC.2007.373426},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/YabuuchiNTOIMYITOHSOSAS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/OhbayashiYKOIUYINTAUOIMIS07,
  author       = {Shigeki Ohbayashi and
                  Makoto Yabuuchi and
                  Kazushi Kono and
                  Yuji Oda and
                  Susumu Imaoka and
                  Keiichi Usui and
                  Toshiaki Yonezu and
                  Takeshi Iwamoto and
                  Koji Nii and
                  Yasumasa Tsukamoto and
                  Masashi Arakawa and
                  Takahiro Uchida and
                  Masakazu Okada and
                  Atsushi Ishii and
                  Hiroshi Makino and
                  Koichiro Ishibashi and
                  Hirofumi Shinohara},
  title        = {A 65nm Embedded {SRAM} with Wafer-Level Burn-In Mode, Leak-Bit Redundancy
                  and E-Trim Fuse for Known Good Die},
  booktitle    = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2007, Digest of Technical Papers, San Francisco, CA, USA, February
                  11-15, 2007},
  pages        = {488--617},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/ISSCC.2007.373507},
  doi          = {10.1109/ISSCC.2007.373507},
  timestamp    = {Wed, 17 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/OhbayashiYKOIUYINTAUOIMIS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iccad/TsukamotoNIOOYMIS05,
  author       = {Yasumasa Tsukamoto and
                  Koji Nii and
                  Susumu Imaoka and
                  Yuji Oda and
                  Shigeki Ohbayashi and
                  Tomoaki Yoshizawa and
                  Hiroshi Makino and
                  Koichiro Ishibashi and
                  Hirofumi Shinohara},
  title        = {Worst-case analysis to obtain stable read/write {DC} margin of high
                  density 6T-SRAM-array with local Vth variability},
  booktitle    = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
                  San Jose, CA, USA, November 6-10, 2005},
  pages        = {398--405},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ICCAD.2005.1560101},
  doi          = {10.1109/ICCAD.2005.1560101},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iccad/TsukamotoNIOOYMIS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/ItohTSNTM05,
  author       = {Niichi Itoh and
                  Yasumasa Tsukamoto and
                  Takeshi Shibagaki and
                  Koji Nii and
                  Hidehiro Takata and
                  Hiroshi Makino},
  title        = {A 32{\texttimes}24-bit multiplier-accumulator with advanced rectangular
                  styled Wallace-tree structure},
  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
                  May 2005, Kobe, Japan},
  pages        = {73--76},
  publisher    = {{IEEE}},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCAS.2005.1464527},
  doi          = {10.1109/ISCAS.2005.1464527},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/ItohTSNTM05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/NiiTYIYSSMI04,
  author       = {Koji Nii and
                  Yasumasa Tsukamoto and
                  Tomoaki Yoshizawa and
                  Susumu Imaoka and
                  Yoshinobu Yamagami and
                  Toshikazu Suzuki and
                  Akinori Shibayama and
                  Hiroshi Makino and
                  Shuhei Iwade},
  title        = {A 90-nm low-power 32-kB embedded {SRAM} with gate leakage suppression
                  circuit for mobile applications},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {39},
  number       = {4},
  pages        = {684--693},
  year         = {2004},
  url          = {https://doi.org/10.1109/JSSC.2004.825235},
  doi          = {10.1109/JSSC.2004.825235},
  timestamp    = {Fri, 26 Aug 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/NiiTYIYSSMI04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcad/FujinagaTKUKT95,
  author       = {Masato Fujinaga and
                  I. Tottori and
                  Tatsuya Kunikiyo and
                  Tetsuya Uchida and
                  Norihiko Kotani and
                  Yasumasa Tsukamoto},
  title        = {3-D numerical modeling of thermal flow for insulating thin film using
                  surface diffusion},
  journal      = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
  volume       = {14},
  number       = {5},
  pages        = {631--638},
  year         = {1995},
  url          = {https://doi.org/10.1109/43.384427},
  doi          = {10.1109/43.384427},
  timestamp    = {Thu, 24 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcad/FujinagaTKUKT95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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