BibTeX records: Shihheng Tsai

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@inproceedings{DBLP:conf/aspdac/TsaiLH12,
  author       = {Shihheng Tsai and
                  Man{-}Yu Li and
                  Chung{-}Yang Huang},
  title        = {A semi-formal min-cost buffer insertion technique considering multi-mode
                  multi-corner timing constraints},
  booktitle    = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
                  {ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
  pages        = {505--510},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ASPDAC.2012.6165005},
  doi          = {10.1109/ASPDAC.2012.6165005},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/TsaiLH12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dac/TsaiH09,
  author       = {Shihheng Tsai and
                  Chung{-}Yang Huang},
  title        = {A false-path aware formal static timing analyzer considering simultaneous
                  input transitions},
  booktitle    = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
                  San Francisco, CA, USA, July 26-31, 2009},
  pages        = {25--30},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1629911.1629921},
  doi          = {10.1145/1629911.1629921},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/TsaiH09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}