BibTeX records: Dar Sun

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@inproceedings{DBLP:conf/isscc/FujiwaraMZCNCHS22,
  author       = {Hidehiro Fujiwara and
                  Haruki Mori and
                  Wei{-}Chang Zhao and
                  Mei{-}Chen Chuang and
                  Rawan Naous and
                  Chao{-}Kai Chuang and
                  Takeshi Hashizume and
                  Dar Sun and
                  Chia{-}Fu Lee and
                  Kerem Akarvardar and
                  Saman Adham and
                  Tan{-}Li Chou and
                  Mahmut Ersin Sinangil and
                  Yih Wang and
                  Yu{-}Der Chih and
                  Yen{-}Huei Chen and
                  Hung{-}Jen Liao and
                  Tsung{-}Yung Jonathan Chang},
  title        = {A 5-nm 254-TOPS/W 221-TOPS/mm\({}^{\mbox{2}}\) Fully-Digital Computing-in-Memory
                  Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and
                  Simultaneous {MAC} and Write Operations},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
                  San Francisco, CA, USA, February 20-26, 2022},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/ISSCC42614.2022.9731754},
  doi          = {10.1109/ISSCC42614.2022.9731754},
  timestamp    = {Mon, 21 Mar 2022 13:32:47 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/FujiwaraMZCNCHS22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/SinangilENASKLW21,
  author       = {Mahmut E. Sinangil and
                  Burak Erbagci and
                  Rawan Naous and
                  Kerem Akarvardar and
                  Dar Sun and
                  Win{-}San Khwa and
                  Hung{-}Jen Liao and
                  Yih Wang and
                  Jonathan Chang},
  title        = {A 7-nm Compute-in-Memory {SRAM} Macro Supporting Multi-Bit Input,
                  Weight and Output and Achieving 351 {TOPS/W} and 372.4 {GOPS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {56},
  number       = {1},
  pages        = {188--198},
  year         = {2021},
  url          = {https://doi.org/10.1109/JSSC.2020.3031290},
  doi          = {10.1109/JSSC.2020.3031290},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/SinangilENASKLW21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ChihLFSLNCLLMZS21,
  author       = {Yu{-}Der Chih and
                  Po{-}Hao Lee and
                  Hidehiro Fujiwara and
                  Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Rawan Naous and
                  Yu{-}Lin Chen and
                  Chieh{-}Pu Lo and
                  Cheng{-}Han Lu and
                  Haruki Mori and
                  Wei{-}Cheng Zhao and
                  Dar Sun and
                  Mahmut E. Sinangil and
                  Yen{-}Huei Chen and
                  Tan{-}Li Chou and
                  Kerem Akarvardar and
                  Hung{-}Jen Liao and
                  Yih Wang and
                  Meng{-}Fan Chang and
                  Tsung{-}Yung Jonathan Chang},
  title        = {An 89TOPS/W and 16.3TOPS/mm\({}^{\mbox{2}}\) All-Digital SRAM-Based
                  Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning
                  Edge Applications},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
                  San Francisco, CA, USA, February 13-22, 2021},
  pages        = {252--254},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/ISSCC42613.2021.9365766},
  doi          = {10.1109/ISSCC42613.2021.9365766},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ChihLFSLNCLLMZS21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/0001SESKLWC20,
  author       = {Qing Dong and
                  Mahmut E. Sinangil and
                  Burak Erbagci and
                  Dar Sun and
                  Win{-}San Khwa and
                  Hung{-}Jen Liao and
                  Yih Wang and
                  Jonathan Chang},
  title        = {15.3 {A} 351TOPS/W and 372.4GOPS Compute-in-Memory {SRAM} Macro in
                  7nm FinFET {CMOS} for Machine-Learning Applications},
  booktitle    = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
                  2020, San Francisco, CA, USA, February 16-20, 2020},
  pages        = {242--244},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/ISSCC19947.2020.9062985},
  doi          = {10.1109/ISSCC19947.2020.9062985},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/0001SESKLWC20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asscc/FujiwaraCLWSWLC16,
  author       = {Hidehiro Fujiwara and
                  Yen{-}Huei Chen and
                  Chih{-}Yu Lin and
                  Wei{-}Cheng Wu and
                  Dar Sun and
                  Shin{-}Rung Wu and
                  Hung{-}Jen Liao and
                  Jonathan Chang},
  title        = {A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted {WL}
                  scheme for IoT applications},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
                  Japan, November 7-9, 2016},
  pages        = {185--188},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ASSCC.2016.7844166},
  doi          = {10.1109/ASSCC.2016.7844166},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/asscc/FujiwaraCLWSWLC16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/FujiwaraWCLSWLL15,
  author       = {Hidehiro Fujiwara and
                  Li{-}Wen Wang and
                  Yen{-}Huei Chen and
                  Kao{-}Cheng Lin and
                  Dar Sun and
                  Shin{-}Rung Wu and
                  Jhon{-}Jhy Liaw and
                  Chih{-}Yung Lin and
                  Mu{-}Chi Chiang and
                  Hung{-}Jen Liao and
                  Shien{-}Yang Wu and
                  Jonathan Chang},
  title        = {17.2 {A} 64kb 16nm asynchronous disturb current free 2-port {SRAM}
                  with {PMOS} pass-gates for FinFET technologies},
  booktitle    = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2015, Digest of Technical Papers, San Francisco, CA, USA, February
                  22-26, 2015},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/ISSCC.2015.7063051},
  doi          = {10.1109/ISSCC.2015.7063051},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/FujiwaraWCLSWLL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ChenCLCSLWCY12,
  author       = {Yen{-}Huei Chen and
                  Shao{-}Yu Chou and
                  Quincy Li and
                  Wei{-}Min Chan and
                  Dar Sun and
                  Hung{-}Jen Liao and
                  Ping Wang and
                  Meng{-}Fan Chang and
                  Hiroyuki Yamauchi},
  title        = {Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset
                  Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance
                  Margin in a 40 nm Fully Functional Embedded {SRAM}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {47},
  number       = {4},
  pages        = {969--980},
  year         = {2012},
  url          = {https://doi.org/10.1109/JSSC.2012.2185180},
  doi          = {10.1109/JSSC.2012.2185180},
  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/ChenCLCSLWCY12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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