BibTeX records: Kevin Stawiasz

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@article{DBLP:journals/jssc/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15,
  author       = {Eric J. Fluhr and
                  Steve Baumgartner and
                  David W. Boerstler and
                  John F. Bulzacchelli and
                  Timothy Diemoz and
                  Daniel Dreps and
                  George English and
                  Joshua Friedrich and
                  Anne Gattiker and
                  Tilman Gloekler and
                  Christopher J. Gonzalez and
                  Jason Hibbeler and
                  Keith A. Jenkins and
                  Yong Kim and
                  Paul Muench and
                  Ryan Nett and
                  Jose Paredes and
                  Juergen Pille and
                  Donald W. Plass and
                  Phillip J. Restle and
                  Raphael Robertazzi and
                  David Shan and
                  David W. Siljenberg and
                  Michael A. Sperling and
                  Kevin Stawiasz and
                  Gregory S. Still and
                  Zeynep Toprak Deniz and
                  James D. Warnock and
                  Glen A. Wiedemeier and
                  Victor V. Zyuban},
  title        = {The 12-Core POWER8{\texttrademark} Processor With 7.6 Tb/s {IO} Bandwidth,
                  Integrated Voltage Regulation, and Resonant Clocking},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {50},
  number       = {1},
  pages        = {10--23},
  year         = {2015},
  url          = {https://doi.org/10.1109/JSSC.2014.2358553},
  doi          = {10.1109/JSSC.2014.2358553},
  timestamp    = {Fri, 25 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/irps/OldigesRGMSMTKM15,
  author       = {Phil Oldiges and
                  Kenneth P. Rodbell and
                  Michael S. Gordon and
                  John G. Massey and
                  Kevin Stawiasz and
                  Conal E. Murray and
                  Henry H. K. Tang and
                  K. Kim and
                  K. Paul Muller},
  title        = {{SOI} FinFET soft error upset susceptibility and analysis},
  booktitle    = {{IEEE} International Reliability Physics Symposium, {IRPS} 2015, Monterey,
                  CA, USA, April 19-23, 2015},
  pages        = {4},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/IRPS.2015.7112729},
  doi          = {10.1109/IRPS.2015.7112729},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/irps/OldigesRGMSMTKM15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/irps/RayLRSWYSS15,
  author       = {Emily Ray and
                  Barry P. Linder and
                  Raphael Robertazzi and
                  Kevin Stawiasz and
                  Alan J. Weger and
                  Emmanuel Yashchin and
                  James H. Stathis and
                  Peilin Song},
  title        = {Analyzing path delays for accelerated testing of logic chips},
  booktitle    = {{IEEE} International Reliability Physics Symposium, {IRPS} 2015, Monterey,
                  CA, USA, April 19-23, 2015},
  pages        = {6},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/IRPS.2015.7112764},
  doi          = {10.1109/IRPS.2015.7112764},
  timestamp    = {Fri, 23 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/irps/RayLRSWYSS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/FluhrFDZSGHHMNP14,
  author       = {Eric J. Fluhr and
                  Joshua Friedrich and
                  Daniel M. Dreps and
                  Victor V. Zyuban and
                  Gregory S. Still and
                  Christopher J. Gonzalez and
                  Allen Hall and
                  David Hogenmiller and
                  Frank Malgioglio and
                  Ryan Nett and
                  Jose Paredes and
                  Juergen Pille and
                  Donald W. Plass and
                  Ruchir Puri and
                  Phillip J. Restle and
                  David Shan and
                  Kevin Stawiasz and
                  Zeynep Toprak Deniz and
                  Dieter F. Wendel and
                  Matthew M. Ziegler},
  title        = {5.1 POWER8\({}^{\mbox{TM}}\): {A} 12-core server-class processor in
                  22nm {SOI} with 7.6Tb/s off-chip bandwidth},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {96--97},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757353},
  doi          = {10.1109/ISSCC.2014.6757353},
  timestamp    = {Fri, 25 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/FluhrFDZSGHHMNP14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/DenizSBSKKBGRSD14,
  author       = {Zeynep Toprak Deniz and
                  Michael A. Sperling and
                  John F. Bulzacchelli and
                  Gregory S. Still and
                  Ryan Kruse and
                  Seongwon Kim and
                  David Boerstler and
                  Tilman Gloekler and
                  Raphael Robertazzi and
                  Kevin Stawiasz and
                  Tim Diemoz and
                  George English and
                  David Hui and
                  Paul Muench and
                  Joshua Friedrich},
  title        = {5.2 Distributed system of digitally controlled microregulators enabling
                  per-core {DVFS} for the POWER8\({}^{\mbox{TM}}\) microprocessor},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {98--99},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757354},
  doi          = {10.1109/ISSCC.2014.6757354},
  timestamp    = {Mon, 10 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/DenizSBSKKBGRSD14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/esscirc/KuangJSS13,
  author       = {Jente B. Kuang and
                  Keith A. Jenkins and
                  Kevin Stawiasz and
                  Jeremy D. Schaub},
  title        = {Performance impact of through-silicon vias (TSVs) in three-dimensional
                  technology measured by {SRAM} ring oscillators},
  booktitle    = {{ESSCIRC} 2013 - Proceedings of the 39th European Solid-State Circuits
                  Conference, Bucharest, Romania, September 16-20, 2013},
  pages        = {419--422},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ESSCIRC.2013.6649162},
  doi          = {10.1109/ESSCIRC.2013.6649162},
  timestamp    = {Fri, 23 Jul 2021 15:40:30 +0200},
  biburl       = {https://dblp.org/rec/conf/esscirc/KuangJSS13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/QaziSCC11,
  author       = {Masood Qazi and
                  Kevin Stawiasz and
                  Leland Chang and
                  Anantha P. Chandrakasan},
  title        = {A 512kb 8T {SRAM} Macro Operating Down to 0.57 {V} With an AC-Coupled
                  Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm
                  {SOI} {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {46},
  number       = {1},
  pages        = {85--96},
  year         = {2011},
  url          = {https://doi.org/10.1109/JSSC.2010.2085970},
  doi          = {10.1109/JSSC.2010.2085970},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/QaziSCC11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/QaziSCC10,
  author       = {Masood Qazi and
                  Kevin Stawiasz and
                  Leland Chang and
                  Anantha P. Chandrakasan},
  title        = {A 512kb 8T {SRAM} macro operating down to 0.57V with an AC-coupled
                  sense amplifier and embedded data-retention-voltage sensor in 45nm
                  {SOI} {CMOS}},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
                  Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
                  2010},
  pages        = {350--351},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSCC.2010.5433818},
  doi          = {10.1109/ISSCC.2010.5433818},
  timestamp    = {Mon, 27 Sep 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/QaziSCC10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/BhavnagarwalaKR08,
  author       = {Azeez J. Bhavnagarwala and
                  Stephen Kosonocky and
                  Carl Radens and
                  Yuen H. Chan and
                  Kevin Stawiasz and
                  Uma Srinivasan and
                  Steven P. Kowalczyk and
                  Matthew M. Ziegler},
  title        = {A Sub-600-mV, Fluctuation Tolerant 65-nm {CMOS} {SRAM} Array With
                  Dynamic Cell Biasing},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {43},
  number       = {4},
  pages        = {946--955},
  year         = {2008},
  url          = {https://doi.org/10.1109/JSSC.2008.917506},
  doi          = {10.1109/JSSC.2008.917506},
  timestamp    = {Tue, 19 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/BhavnagarwalaKR08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/KimKKSP07,
  author       = {Suhwan Kim and
                  Stephen V. Kosonocky and
                  Daniel R. Knebel and
                  Kevin Stawiasz and
                  Marios C. Papaefthymiou},
  title        = {A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron
                  {CMOS} ICs},
  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume       = {54-II},
  number       = {7},
  pages        = {586--590},
  year         = {2007},
  url          = {https://doi.org/10.1109/TCSII.2007.894428},
  doi          = {10.1109/TCSII.2007.894428},
  timestamp    = {Fri, 23 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/KimKKSP07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/islped/KimKKS04,
  author       = {Suhwan Kim and
                  Stephen V. Kosonocky and
                  Daniel R. Knebel and
                  Kevin Stawiasz},
  editor       = {Rajiv V. Joshi and
                  Kiyoung Choi and
                  Vivek Tiwari and
                  Kaushik Roy},
  title        = {Experimental measurement of a novel power gating structure with intermediate
                  power saving mode},
  booktitle    = {Proceedings of the 2004 International Symposium on Low Power Electronics
                  and Design, 2004, Newport Beach, California, USA, August 9-11, 2004},
  pages        = {20--25},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1013235.1013246},
  doi          = {10.1145/1013235.1013246},
  timestamp    = {Fri, 23 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/islped/KimKKS04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/esscirc/KimKKSHI03,
  author       = {Suhwan Kim and
                  Stephen V. Kosonocky and
                  Daniel R. Knebel and
                  Kevin Stawiasz and
                  David F. Heidel and
                  Michael Immediato},
  editor       = {Jos{\'{e}} E. Franca and
                  Rudolf Koch},
  title        = {Minimizing inductive noise in system-on-a-chip with multiple power
                  gating structures},
  booktitle    = {{ESSCIRC} 2003 - 29th European Solid-State Circuits Conference, Estoril,
                  Portugal, September 16-18, 2003},
  pages        = {635--638},
  publisher    = {{IEEE}},
  year         = {2003},
  url          = {https://doi.org/10.1109/ESSCIRC.2003.1257215},
  doi          = {10.1109/ESSCIRC.2003.1257215},
  timestamp    = {Tue, 04 Jul 2023 08:46:31 +0200},
  biburl       = {https://dblp.org/rec/conf/esscirc/KimKKSHI03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/YangCKSPA98,
  author       = {Jungwook Yang and
                  Joongho Choi and
                  Daniel M. Kuchta and
                  Kevin G. Stawiasz and
                  Petar K. Pepeljugoski and
                  Herschel A. Ainspan},
  title        = {A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-{\(\mu\)}m GaAs
                  technology},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {33},
  number       = {12},
  pages        = {2197--2204},
  year         = {1998},
  url          = {https://doi.org/10.1109/4.735704},
  doi          = {10.1109/4.735704},
  timestamp    = {Wed, 06 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/YangCKSPA98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vts/KosonockyBWHKABHHIJJPRS98,
  author       = {Stephen V. Kosonocky and
                  Arthur A. Bright and
                  Kevin W. Warren and
                  Ruud A. Haring and
                  Steve Klepner and
                  Sameh W. Asaad and
                  S. Basavaiah and
                  Bob Havreluk and
                  David F. Heidel and
                  Michael Immediato and
                  Keith A. Jenkins and
                  Rajiv V. Joshi and
                  Benjamin D. Parker and
                  T. V. Rajeevakumar and
                  Kevin Stawiasz},
  title        = {Designing a Testable System on a Chip},
  booktitle    = {16th {IEEE} {VLSI} Test Symposium {(VTS} '98), 28 April - 1 May 1998,
                  Princeton, NJ, {USA}},
  pages        = {2--7},
  publisher    = {{IEEE} Computer Society},
  year         = {1998},
  url          = {https://doi.org/10.1109/VTEST.1998.670841},
  doi          = {10.1109/VTEST.1998.670841},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vts/KosonockyBWHKABHHIJJPRS98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vts/HeidelDHINSS98,
  author       = {David F. Heidel and
                  Sang H. Dhong and
                  H. Peter Hofstee and
                  Michael Immediato and
                  Kevin J. Nowka and
                  Joel Silberman and
                  Kevin Stawiasz},
  title        = {High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating
                  a 1 GHz Microprocessor},
  booktitle    = {16th {IEEE} {VLSI} Test Symposium {(VTS} '98), 28 April - 1 May 1998,
                  Princeton, NJ, {USA}},
  pages        = {234--238},
  publisher    = {{IEEE} Computer Society},
  year         = {1998},
  url          = {https://doi.org/10.1109/VTEST.1998.670873},
  doi          = {10.1109/VTEST.1998.670873},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vts/HeidelDHINSS98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ibmrd/KirtleyKTSGYGSW95,
  author       = {John R. Kirtley and
                  Mark B. Ketchen and
                  Chang C. Tsuei and
                  Jonathan Z. Sun and
                  William J. Gallagher and
                  Lock See Yu{-}Jahnes and
                  Arunava Gupta and
                  Kevin G. Stawiasz and
                  Shalom J. Wind},
  title        = {Design and applications of a scanning {SQUID} microscope},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {39},
  number       = {6},
  pages        = {655--668},
  year         = {1995},
  url          = {https://doi.org/10.1147/rd.396.0655},
  doi          = {10.1147/RD.396.0655},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/KirtleyKTSGYGSW95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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