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ORCIDBibTeX records: Jinuk Luke Shin
@inproceedings{DBLP:conf/cicc/ChenHWYSHLPDSFYZDLYSSJ23,
author = {Zhengyu Chen and
Dawei Huang and
Mingran Wang and
Bowen Yang and
Jinuk Luke Shin and
Changran Hu and
Bo Li and
Raghu Prabhakar and
Gao Deng and
Yongning Sheng and
Sihua Fu and
Lu Yuan and
Tian Zhao and
Yun Du and
Chen Liu and
Jun Yang and
Viren Shah and
Venkat Srinivasan and
Sumti Jairath},
title = {{AI} SoC Design Challenges in the Foundation Model Era},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2023, San Antonio,
TX, USA, April 23-26, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/CICC57935.2023.10121242},
doi = {10.1109/CICC57935.2023.10121242},
timestamp = {Sun, 21 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ChenHWYSHLPDSFYZDLYSSJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/PrabhakarJS22,
author = {Raghu Prabhakar and
Sumti Jairath and
Jinuk Luke Shin},
title = {SambaNova {SN10} {RDU:} {A} 7nm Dataflow Architecture to Accelerate
Software 2.0},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {350--352},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731612},
doi = {10.1109/ISSCC42614.2022.9731612},
timestamp = {Mon, 21 Mar 2022 13:32:47 +0100},
biburl = {https://dblp.org/rec/conf/isscc/PrabhakarJS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BeigneSOKG16,
author = {Edith Beign{\'{e}} and
Jinuk Luke Shin and
Yusuke Oike and
Chulwoo Kim and
Jan Genoe},
title = {Introduction to the January Special Issue on the 2015 {IEEE} International
Solid-State Circuits Conference},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {1},
pages = {3--7},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2015.2502519},
doi = {10.1109/JSSC.2015.2502519},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BeigneSOKG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KrishnaswamyBKM15,
author = {Venkatram Krishnaswamy and
Jeffrey Brooks and
Georgios K. Konstadinidis and
Curtis McAllister and
Ha Pham and
Sebastian Turullols and
Jinuk Luke Shin and
Yifan YangGong and
Haowei Zhang},
title = {4.3 Fine-grained adaptive power management of the {SPARC} {M7} processor},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062932},
doi = {10.1109/ISSCC.2015.7062932},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KrishnaswamyBKM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiSKSKCDMZLLPSH15,
author = {Penny Li and
Jinuk Luke Shin and
Georgios K. Konstadinidis and
Francis Schumacher and
Venkatram Krishnaswamy and
Hoyeol Cho and
Sudesna Dash and
Robert P. Masleid and
Chaoyang Zheng and
Yuanjung David Lin and
Paul Loewenstein and
Heechoul Park and
Vijay Srinivasan and
Dawei Huang and
Changku Hwang and
Wenjay Hsu and
Curtis McAllister},
title = {4.2 {A} 20nm 32-Core 64MB {L3} cache {SPARC} {M7} processor},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062931},
doi = {10.1109/ISSCC.2015.7062931},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LiSKSKCDMZLLPSH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/InoueS15,
author = {Atsuki Inoue and
Jinuk Luke Shin},
title = {Session 4 overview: Processors: High-performance digital subcommittee},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {68--69},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062929},
doi = {10.1109/ISSCC.2015.7062929},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/InoueS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HartCGGHHJJKKKMMNRSSSTQY14,
author = {Jason Hart and
Hoyeol Cho and
Yuefei Ge and
Gregory Gruber and
Dawei Huang and
Changku Hwang and
Daisy Jian and
Timothy Johnson and
Georgios K. Konstadinidis and
Venkatram Krishnaswamy and
Lance Kwong and
Robert P. Masleid and
Rakesh Mehta and
Umesh Nawathe and
Aparna Ramachandran and
Harikaran Sathianathan and
Yongning Sheng and
Jinuk Luke Shin and
Sebastian Turullols and
Zuxu Qin and
King C. Yen},
title = {A 3.6 GHz 16-Core {SPARC} SoC Processor in 28 nm},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {1},
pages = {19--31},
year = {2014},
url = {https://doi.org/10.1109/JSSC.2013.2284648},
doi = {10.1109/JSSC.2013.2284648},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HartCGGHHJJKKKMMNRSSSTQY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/YangGongTWHYKHS14,
author = {Yifan YangGong and
Sebastian Turullols and
Daniel Woo and
Changku Huang and
King C. Yen and
Venkatram Krishnaswamy and
Kalon Holdbrook and
Jinuk Luke Shin},
title = {Asymmetric Frequency Locked Loop {(AFLL)} for adaptive clock generation
in a 28nm {SPARC} {M6} processor},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2014, KaoHsiung,
Taiwan, November 10-12, 2014},
pages = {373--376},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASSCC.2014.7008938},
doi = {10.1109/ASSCC.2014.7008938},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/asscc/YangGongTWHYKHS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ShinGLDCSSJPETKMKDGM13,
author = {Jinuk Luke Shin and
Robert T. Golla and
Hongping Penny Li and
Sudesna Dash and
Youngmoon Choi and
Alan P. Smith and
Harikaran Sathianathan and
Mayur Joshi and
Heechoul Park and
Mohamed Elgebaly and
Sebastian Turullols and
Song Kim and
Robert P. Masleid and
Georgios K. Konstadinidis and
Mary Jo Doherty and
Greg Grohoski and
Curtis McAllister},
title = {The Next Generation 64b {SPARC} Core in a {T4} SoC Processor},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {1},
pages = {82--90},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2012.2223036},
doi = {10.1109/JSSC.2012.2223036},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ShinGLDCSSJPETKMKDGM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HartBCGGHHJJKKMNRSSTQY13,
author = {Jason Hart and
Steve Butler and
Hoyeol Cho and
Yuefei Ge and
Gregory Gruber and
Dawei Huang and
Changku Hwang and
Daisy Jian and
Timothy Johnson and
Georgios K. Konstadinidis and
Lance Kwong and
Robert P. Masleid and
Umesh Nawathe and
Aparna Ramachandran and
Yongning Sheng and
Jinuk Luke Shin and
Sebastian Turullols and
Zuxu Qin and
King C. Yen},
title = {3.6GHz 16-core {SPARC} SoC processor in 28nm},
booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
17-21, 2013},
pages = {48--49},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISSCC.2013.6487631},
doi = {10.1109/ISSCC.2013.6487631},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/HartBCGGHHJJKKMNRSSTQY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KrishnaswamyHTS13,
author = {Venkatram Krishnaswamy and
Dawei Huang and
Sebastian Turullols and
Jinuk Luke Shin},
title = {Bandwidth and power management of glueless 8-socket {SPARC} {T5} system},
booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
17-21, 2013},
pages = {58--59},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISSCC.2013.6487636},
doi = {10.1109/ISSCC.2013.6487636},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KrishnaswamyHTS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FriedrichS12,
author = {Joshua Friedrich and
Jinuk Luke Shin},
title = {Session 3 overview: Processors: High performance digital subcommittee},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {54--55},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6177122},
doi = {10.1109/ISSCC.2012.6177122},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FriedrichS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ShinPLSCSDTKMKGDGM12,
author = {Jinuk Luke Shin and
Heechoul Park and
Hongping Penny Li and
Alan P. Smith and
Youngmoon Choi and
Harikaran Sathianathan and
Sudesna Dash and
Sebastian Turullols and
Song Kim and
Robert P. Masleid and
Georgios K. Konstadinidis and
Robert T. Golla and
Mary Jo Doherty and
Greg Grohoski and
Curtis McAllister},
title = {The next-generation 64b {SPARC} core in a {T4} SoC processor},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {60--62},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6176878},
doi = {10.1109/ISSCC.2012.6176878},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ShinPLSCSDTKMKGDGM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ShinHPHTSPLJSLS11,
author = {Jinuk Luke Shin and
Dawei Huang and
Bruce Petrick and
Changku Hwang and
Kenway W. Tam and
Alan P. Smith and
Ha Pham and
Hongping Penny Li and
Timothy Johnson and
Francis Schumacher and
Ana Sonia Leon and
Allan Strong},
title = {A 40 nm 16-Core 128-Thread {SPARC} SoC Processor},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {1},
pages = {131--144},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2010.2080491},
doi = {10.1109/JSSC.2010.2080491},
timestamp = {Fri, 15 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ShinHPHTSPLJSLS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ShinTHPPHLSJSGLS10,
author = {Jinuk Luke Shin and
Kenway W. Tam and
Dawei Huang and
Bruce Petrick and
Ha Pham and
Changku Hwang and
Hongping Penny Li and
Alan P. Smith and
Timothy Johnson and
Francis Schumacher and
David Greenhill and
Ana Sonia Leon and
Allan Strong},
title = {A 40nm 16-core 128-thread {CMT} {SPARC} SoC processor},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {98--99},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5434030},
doi = {10.1109/ISSCC.2010.5434030},
timestamp = {Fri, 15 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ShinTHPPHLSJSGLS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LeonTSWS07,
author = {Ana Sonia Leon and
Kenway W. Tam and
Jinuk Luke Shin and
David Weisner and
Francis Schumacher},
title = {A Power-Efficient High-Throughput 32-Thread {SPARC} Processor},
journal = {{IEEE} J. Solid State Circuits},
volume = {42},
number = {1},
pages = {7--16},
year = {2007},
url = {https://doi.org/10.1109/JSSC.2006.885049},
doi = {10.1109/JSSC.2006.885049},
timestamp = {Fri, 15 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/LeonTSWS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/LeonLS06,
author = {Ana Sonia Leon and
Brian Langley and
Jinuk Luke Shin},
title = {The UltraSPARC {T1} Processor: {CMT} Reliability},
booktitle = {Proceedings of the {IEEE} 2006 Custom Integrated Circuits Conference,
{CICC} 2006, DoubleTree Hotel, San Jose, California, USA, September
10-13, 2006},
pages = {555--562},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/CICC.2006.320989},
doi = {10.1109/CICC.2006.320989},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/LeonLS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LeonSTBSKWS06,
author = {Ana Sonia Leon and
Jinuk Luke Shin and
Kenway W. Tam and
William Bryg and
Francis Schumacher and
Poonacha Kongetira and
David Weisner and
Allan Strong},
title = {A Power-Efficient High-Throughput 32-Thread {SPARC} Processor},
booktitle = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
2006, Digest of Technical Papers, an Francisco, CA, USA, February
6-9, 2006},
pages = {295--304},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISSCC.2006.1696060},
doi = {10.1109/ISSCC.2006.1696060},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LeonSTBSKWS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TakayanagiSPSLP05,
author = {Toshinari Takayanagi and
Jinuk Luke Shin and
Bruce Petrick and
Jeffrey Y. Su and
Howard Levy and
Ha Pham and
Jinseung Son and
Nathan Moon and
Dina Bistry and
Umesh Nair and
Mandeep Singh and
Vikas Mathur and
Ana Sonia Leon},
title = {A dual-core 64-bit ultraSPARC microprocessor for dense server applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {40},
number = {1},
pages = {7--18},
year = {2005},
url = {https://doi.org/10.1109/JSSC.2004.838023},
doi = {10.1109/JSSC.2004.838023},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/TakayanagiSPSLP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ShinPSL05,
author = {Jinuk Luke Shin and
Bruce Petrick and
Mandeep Singh and
Ana Sonia Leon},
title = {Design and implementation of an embedded 512-KB level-2 cache subsystem},
journal = {{IEEE} J. Solid State Circuits},
volume = {40},
number = {9},
pages = {1815--1820},
year = {2005},
url = {https://doi.org/10.1109/JSSC.2005.852165},
doi = {10.1109/JSSC.2005.852165},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ShinPSL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ShinPLSSMYCGZL04,
author = {Jinuk Luke Shin and
Bruce Petrick and
Howard Levy and
Jinseung Son and
Mandeep Singh and
Vikas Mathur and
Jung{-}Cheng Yeh and
Heesung Choi and
Vishal Gupta and
Tom Ziaja and
Ana Sonia Leon},
title = {Design and implementation of an embedded 512KB level 2 cache subsystem},
booktitle = {Proceedings of the {IEEE} 2004 Custom Integrated Circuits Conference,
{CICC} 2004, Orlando, FL, USA, October 2004},
pages = {349--352},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/CICC.2004.1358818},
doi = {10.1109/CICC.2004.1358818},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ShinPLSSMYCGZL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/TakayanagiSPSL04,
author = {Toshinari Takayanagi and
Jinuk Luke Shin and
Bruce Petrick and
Jeffrey Y. Su and
Ana Sonia Leon},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {A dual-core 64b ultraSPARC microprocessor for dense server applications},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {673--677},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996750},
doi = {10.1145/996566.996750},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/TakayanagiSPSL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/OsadaSKLWSKII01,
author = {Kenichi Osada and
Jinuk Luke Shin and
Masood Khan and
Yude Liou and
Karl Wang and
Kenichi Shoji and
Kenichi Kuroda and
Shuji Ikeda and
Koichiro Ishibashi},
title = {Universal-V\({}_{\mbox{dd}}\) 0.65-2.0-V 32-kB cache using a voltage-adapted
timing-generation scheme and a lithographically symmetrical cell},
journal = {{IEEE} J. Solid State Circuits},
volume = {36},
number = {11},
pages = {1738--1744},
year = {2001},
url = {https://doi.org/10.1109/4.962296},
doi = {10.1109/4.962296},
timestamp = {Wed, 06 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/OsadaSKLWSKII01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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