Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Insup Shin
@article{DBLP:journals/tvlsi/ShinKLS16,
author = {Insup Shin and
Jae{-}Joon Kim and
Yu{-}Shiang Lin and
Youngsoo Shin},
title = {One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked
Elements},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {2},
pages = {600--612},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2409118},
doi = {10.1109/TVLSI.2015.2409118},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShinKLS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ShinKS15,
author = {Insup Shin and
Jae{-}Joon Kim and
Youngsoo Shin},
title = {Aggressive Voltage Scaling Through Fast Correction of Multiple Errors
With Seamless Pipeline Operation},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {62-I},
number = {2},
pages = {468--477},
year = {2015},
url = {https://doi.org/10.1109/TCSI.2014.2364691},
doi = {10.1109/TCSI.2014.2364691},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ShinKS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ShinSBKP14,
author = {Youngsoo Shin and
Insup Shin and
Donkyu Baek and
Duckhwan Kim and
Seungwhun Paik},
title = {{HAPL:} Heterogeneous Array of Programmable Logic Using Selective
Mask Patterning},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {61-I},
number = {1},
pages = {146--159},
year = {2014},
url = {https://doi.org/10.1109/TCSI.2013.2264690},
doi = {10.1109/TCSI.2013.2264690},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ShinSBKP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ShinKS14,
author = {Insup Shin and
Jae{-}Joon Kim and
Youngsoo Shin},
title = {Power minimization of pipeline architecture through 1-cycle error
correction and voltage scaling},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {179--184},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742886},
doi = {10.1109/ASPDAC.2014.6742886},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ShinKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/BaekSS13,
author = {Donkyu Baek and
Insup Shin and
Youngsoo Shin},
title = {Accurate gate delay Extraction for Timing Analysis of Body-Biased
Circuits},
journal = {J. Circuits Syst. Comput.},
volume = {22},
number = {8},
year = {2013},
url = {https://doi.org/10.1142/S0218126613500722},
doi = {10.1142/S0218126613500722},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/BaekSS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ShinKLS13,
author = {Insup Shin and
Jae{-}Joon Kim and
Yu{-}Shiang Lin and
Youngsoo Shin},
editor = {Pai H. Chou and
Ru Huang and
Yuan Xie and
Tanay Karnik},
title = {A pipeline architecture with 1-cycle timing error correction for low
voltage operations},
booktitle = {International Symposium on Low Power Electronics and Design (ISLPED),
Beijing, China, September 4-6, 2013},
pages = {199--204},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISLPED.2013.6629294},
doi = {10.1109/ISLPED.2013.6629294},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/ShinKLS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeomunSS12,
author = {Jun Seomun and
Insup Shin and
Youngsoo Shin},
title = {Synthesis of Active-Mode Power-Gating Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {391--403},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2171963},
doi = {10.1109/TCAD.2011.2171963},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeomunSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShinPSS12,
author = {Insup Shin and
Seungwhun Paik and
Dongwan Shin and
Youngsoo Shin},
title = {HLS-dv: {A} High-Level Synthesis Framework for Dual-Vdd Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {593--604},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2122310},
doi = {10.1109/TVLSI.2011.2122310},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShinPSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ShinBS12,
author = {Insup Shin and
Donkyu Baek and
Youngsoo Shin},
title = {Introducing irregularity to routing architecture of structured {ASIC}
for better routability},
booktitle = {2012 International Conference on Field-Programmable Technology, {FPT}
2012, Seoul, Korea (South), December 10-12, 2012},
pages = {224--228},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPT.2012.6412138},
doi = {10.1109/FPT.2012.6412138},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/ShinBS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icicdt/BaekSS12,
author = {Donkyu Baek and
Insup Shin and
Youngsoo Shin},
title = {Gate delay modeling for static timing analysis of body-biased circuits},
booktitle = {{IEEE} International Conference on {IC} Design {\&} Technology,
{ICICDT} 2012, Austin, TX, USA, May 30 - June 1, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ICICDT.2012.6232836},
doi = {10.1109/ICICDT.2012.6232836},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/icicdt/BaekSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/BaekSPS11,
author = {Donkyu Baek and
Insup Shin and
Seungwhun Paik and
Youngsoo Shin},
title = {Selectively patterned masks: Structured {ASIC} with asymptotically
{ASIC} performance},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {376--381},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722217},
doi = {10.1109/ASPDAC.2011.5722217},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/BaekSPS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PaikSKS10,
author = {Seungwhun Paik and
Insup Shin and
Taewhan Kim and
Youngsoo Shin},
title = {HLS-l: {A} High-Level Synthesis Framework for Latch-Based Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {657--670},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043588},
doi = {10.1109/TCAD.2010.2043588},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PaikSKS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SeomunSS10,
author = {Jun Seomun and
Insup Shin and
Youngsoo Shin},
editor = {Sachin S. Sapatnekar},
title = {Synthesis and implementation of active mode power gating circuits},
booktitle = {Proceedings of the 47th Design Automation Conference, {DAC} 2010,
Anaheim, California, USA, July 13-18, 2010},
pages = {487--492},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1837274.1837395},
doi = {10.1145/1837274.1837395},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SeomunSS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ShinPS09,
author = {Insup Shin and
Seungwhun Paik and
Youngsoo Shin},
title = {Register allocation for high-level synthesis using dual supply voltages},
booktitle = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
San Francisco, CA, USA, July 26-31, 2009},
pages = {937--942},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629911.1630152},
doi = {10.1145/1629911.1630152},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ShinPS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PaikSS09,
author = {Seungwhun Paik and
Insup Shin and
Youngsoo Shin},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {HLS-l: High-level synthesis of high performance latch-based circuits},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {1112--1117},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090830},
doi = {10.1109/DATE.2009.5090830},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/PaikSS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-25 02:02 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
