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BibTeX records: N. Pete Sedcole
@article{DBLP:journals/iet-cdt/StottSC10, author = {Edward A. Stott and N. Pete Sedcole and Peter Y. K. Cheung}, title = {Fault tolerance and reliability in field-programmable gate arrays}, journal = {{IET} Comput. Digit. Tech.}, volume = {4}, number = {3}, pages = {196--210}, year = {2010}, url = {https://doi.org/10.1049/iet-cdt.2009.0011}, doi = {10.1049/IET-CDT.2009.0011}, timestamp = {Tue, 14 Jul 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/iet-cdt/StottSC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/MakSCL10, author = {Terrence S. T. Mak and N. Pete Sedcole and Peter Y. K. Cheung and Wayne Luk}, title = {Wave-pipelined intra-chip signaling for on-FPGA communications}, journal = {Integr.}, volume = {43}, number = {2}, pages = {188--201}, year = {2010}, url = {https://doi.org/10.1016/j.vlsi.2010.01.002}, doi = {10.1016/J.VLSI.2010.01.002}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/MakSCL10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/StottWSC10, author = {Edward A. Stott and Justin S. J. Wong and N. Pete Sedcole and Peter Y. K. Cheung}, editor = {Peter Y. K. Cheung and John Wawrzynek}, title = {Degradation in FPGAs: measurement and modelling}, booktitle = {Proceedings of the {ACM/SIGDA} 18th International Symposium on Field Programmable Gate Arrays, {FPGA} 2010, Monterey, California, USA, February 21-23, 2010}, pages = {229--238}, publisher = {{ACM}}, year = {2010}, url = {https://doi.org/10.1145/1723112.1723152}, doi = {10.1145/1723112.1723152}, timestamp = {Wed, 03 Apr 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpga/StottWSC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/WongSC09, author = {Justin S. J. Wong and N. Pete Sedcole and Peter Y. K. Cheung}, title = {Self-Measurement of Combinatorial Circuit Delays in FPGAs}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {2}, number = {2}, pages = {10:1--10:22}, year = {2009}, url = {https://doi.org/10.1145/1534916.1534920}, doi = {10.1145/1534916.1534920}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/WongSC09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/SedcoleSC09, author = {N. Pete Sedcole and Edward A. Stott and Peter Y. K. Cheung}, editor = {Martin Danek and Jiri Kadlec and Brent E. Nelson}, title = {Compensating for variability in FPGAs by re-mapping and re-placement}, booktitle = {19th International Conference on Field Programmable Logic and Applications, {FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic}, pages = {613--616}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.org/10.1109/FPL.2009.5272380}, doi = {10.1109/FPL.2009.5272380}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/SedcoleSC09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/WangMSC09, author = {Li Wang and Terrence S. T. Mak and N. Pete Sedcole and Peter Y. K. Cheung}, title = {Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2009), 24-17 May 2009, Taipei, Taiwan}, pages = {1293--1296}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.org/10.1109/ISCAS.2009.5118000}, doi = {10.1109/ISCAS.2009.5118000}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/WangMSC09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/SedcoleC08, author = {N. Pete Sedcole and Peter Y. K. Cheung}, title = {Parametric Yield Modeling and Simulations of {FPGA} Circuits Considering Within-Die Delay Variations}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {1}, number = {2}, pages = {10:1--10:28}, year = {2008}, url = {https://doi.org/10.1145/1371579.1371582}, doi = {10.1145/1371579.1371582}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/SedcoleC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/MakSCL08, author = {Terrence S. T. Mak and N. Pete Sedcole and Peter Y. K. Cheung and Wayne Luk}, editor = {Mike Hutton and Paul Chow}, title = {High-throughput interconnect wave-pipelining for global communication in FPGAs}, booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA, February 24-26, 2008}, pages = {258}, publisher = {{ACM}}, year = {2008}, url = {https://doi.org/10.1145/1344671.1344714}, doi = {10.1145/1344671.1344714}, timestamp = {Tue, 06 Nov 2018 16:58:23 +0100}, biburl = {https://dblp.org/rec/conf/fpga/MakSCL08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/SedcoleWC08, author = {N. Pete Sedcole and Justin S. J. Wong and Peter Y. K. Cheung}, editor = {Mike Hutton and Paul Chow}, title = {Measuring and modeling {FPGA} clock variability}, booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA, February 24-26, 2008}, pages = {258}, publisher = {{ACM}}, year = {2008}, url = {https://doi.org/10.1145/1344671.1344713}, doi = {10.1145/1344671.1344713}, timestamp = {Wed, 03 Apr 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpga/SedcoleWC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/StottSC08, author = {Edward A. Stott and N. Pete Sedcole and Peter Y. K. Cheung}, title = {Fault tolerant methods for reliability in FPGAs}, booktitle = {{FPL} 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008}, pages = {415--420}, publisher = {{IEEE}}, year = {2008}, url = {https://doi.org/10.1109/FPL.2008.4629973}, doi = {10.1109/FPL.2008.4629973}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/StottSC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/WongCS08, author = {Justin S. J. Wong and Peter Y. K. Cheung and N. Pete Sedcole}, title = {Combating process variation on {FPGAS} with a precise at-speed delay measurement method}, booktitle = {{FPL} 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008}, pages = {703--704}, publisher = {{IEEE}}, year = {2008}, url = {https://doi.org/10.1109/FPL.2008.4630046}, doi = {10.1109/FPL.2008.4630046}, timestamp = {Wed, 03 Apr 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/WongCS08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/MakSCL08, author = {Terrence S. T. Mak and N. Pete Sedcole and Peter Y. K. Cheung and Wayne Luk}, editor = {Tarek A. El{-}Ghazawi and Yao{-}Wen Chang and Juinn{-}Dar Huang and Proshanta Saha}, title = {Wave-pipelined signaling for on-FPGA communication}, booktitle = {2008 International Conference on Field-Programmable Technology, {FPT} 2008, Taipei, Taiwan, December 7-10, 2008}, pages = {9--16}, publisher = {{IEEE}}, year = {2008}, url = {https://doi.org/10.1109/FPT.2008.4762360}, doi = {10.1109/FPT.2008.4762360}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/fpt/MakSCL08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/WongSC08, author = {Justin S. J. Wong and N. Pete Sedcole and Peter Y. K. Cheung}, editor = {Tarek A. El{-}Ghazawi and Yao{-}Wen Chang and Juinn{-}Dar Huang and Proshanta Saha}, title = {A transition probability based delay measurement method for arbitrary circuits on FPGAs}, booktitle = {2008 International Conference on Field-Programmable Technology, {FPT} 2008, Taipei, Taiwan, December 7-10, 2008}, pages = {105--112}, publisher = {{IEEE}}, year = {2008}, url = {https://doi.org/10.1109/FPT.2008.4762372}, doi = {10.1109/FPT.2008.4762372}, timestamp = {Wed, 03 Apr 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpt/WongSC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/SedcoleWC08, author = {N. Pete Sedcole and Justin S. J. Wong and Peter Y. K. Cheung}, editor = {Tarek A. El{-}Ghazawi and Yao{-}Wen Chang and Juinn{-}Dar Huang and Proshanta Saha}, title = {Modelling and compensating for clock skew variability in FPGAs}, booktitle = {2008 International Conference on Field-Programmable Technology, {FPT} 2008, Taipei, Taiwan, December 7-10, 2008}, pages = {217--224}, publisher = {{IEEE}}, year = {2008}, url = {https://doi.org/10.1109/FPT.2008.4762386}, doi = {10.1109/FPT.2008.4762386}, timestamp = {Wed, 03 Apr 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpt/SedcoleWC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isvlsi/SedcoleWC08, author = {N. Pete Sedcole and Justin S. J. Wong and Peter Y. K. Cheung}, title = {Characterisation of {FPGA} Clock Variability}, booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9 April 2008, Montpellier, France}, pages = {322--328}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ISVLSI.2008.48}, doi = {10.1109/ISVLSI.2008.48}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isvlsi/SedcoleWC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/nocs/MakDSCYL08, author = {Terrence S. T. Mak and Crescenzo D'Alessandro and N. Pete Sedcole and Peter Y. K. Cheung and Alexandre Yakovlev and Wayne Luk}, title = {Implementation of Wave-Pipelined Interconnects in FPGAs}, booktitle = {Second International Symposium on Networks-on-Chips, {NOCS} 2008, 5-6 April 2008, Newcastle University, {UK.} Proceedings}, pages = {213--214}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.ieeecomputersociety.org/10.1109/NOCS.2008.32}, doi = {10.1109/NOCS.2008.32}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/nocs/MakDSCYL08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/MakSCL08, author = {Terrence S. T. Mak and N. Pete Sedcole and Peter Y. K. Cheung and Wayne Luk}, editor = {Ion I. Mandoiu and Andrew A. Kennings}, title = {Interconnection lengths and delays estimation for communication links in FPGAs}, booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction {(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings}, pages = {1--10}, publisher = {{ACM}}, year = {2008}, url = {https://doi.org/10.1145/1353610.1353612}, doi = {10.1145/1353610.1353612}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/slip/MakSCL08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/MakDSCYL08, author = {Terrence S. T. Mak and Crescenzo D'Alessandro and N. Pete Sedcole and Peter Y. K. Cheung and Alexandre Yakovlev and Wayne Luk}, editor = {Ion I. Mandoiu and Andrew A. Kennings}, title = {Global interconnections in FPGAs: modeling and performance analysis}, booktitle = {The Tenth International Workshop on System-Level Interconnect Prediction {(SLIP} 2008), Newcastle, UK, April 5-8, 2008, Proceedings}, pages = {51--58}, publisher = {{ACM}}, year = {2008}, url = {https://doi.org/10.1145/1353610.1353621}, doi = {10.1145/1353610.1353621}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/slip/MakDSCYL08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/SedcoleCCL07, author = {N. Pete Sedcole and Peter Y. K. Cheung and George A. Constantinides and Wayne Luk}, title = {Run-Time Integration of Reconfigurable Video Processing Systems}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {15}, number = {9}, pages = {1003--1016}, year = {2007}, url = {https://doi.org/10.1109/TVLSI.2007.902203}, doi = {10.1109/TVLSI.2007.902203}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/SedcoleCCL07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/SedcoleC07, author = {N. Pete Sedcole and Peter Y. K. Cheung}, editor = {Andr{\'{e}} DeHon and Mike Hutton}, title = {Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis}, booktitle = {Proceedings of the {ACM/SIGDA} 15th International Symposium on Field Programmable Gate Arrays, {FPGA} 2007, Monterey, California, USA, February 18-20, 2007}, pages = {178--187}, publisher = {{ACM}}, year = {2007}, url = {https://doi.org/10.1145/1216919.1216949}, doi = {10.1145/1216919.1216949}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/SedcoleC07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/WongSC07, author = {Justin S. J. Wong and N. Pete Sedcole and Peter Y. K. Cheung}, editor = {Hideharu Amano and Andy Ye and Takeshi Ikenaga}, title = {Self-characterization of Combinatorial Circuit Delays in FPGAs}, booktitle = {2007 International Conference on Field-Programmable Technology, {ICFPT} 2007, Kitakyushu, Japan, December 12-14, 2007}, pages = {17--23}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1109/FPT.2007.4439227}, doi = {10.1109/FPT.2007.4439227}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/fpt/WongSC07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/nocs/MakSCLL07, author = {Terrence S. T. Mak and N. Pete Sedcole and Peter Y. K. Cheung and Wayne Luk and Kai{-}Pui Lam}, title = {A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing}, booktitle = {First International Symposium on Networks-on-Chips, {NOCS} 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings}, pages = {173--182}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/NOCS.2007.2}, doi = {10.1109/NOCS.2007.2}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/nocs/MakSCLL07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/MakSCL06, author = {Terrence S. T. Mak and N. Pete Sedcole and Peter Y. K. Cheung and Wayne Luk}, title = {On-FPGA Communication Architectures and Design Factors}, booktitle = {Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006}, pages = {1--8}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/FPL.2006.311209}, doi = {10.1109/FPL.2006.311209}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/MakSCL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/SedcoleC06, author = {N. Pete Sedcole and Peter Y. K. Cheung}, editor = {George A. Constantinides and Wai{-}Kei Mak and Phaophak Sirisuk and Theerayod Wiangtong}, title = {Within-die delay variability in 90nm FPGAs and beyond}, booktitle = {2006 {IEEE} International Conference on Field Programmable Technology, {FPT} 2006, Bangkok, Thailand, December 13-15, 2006}, pages = {97--104}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/FPT.2006.270300}, doi = {10.1109/FPT.2006.270300}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/fpt/SedcoleC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/samos/SedcoleCCL06, author = {N. Pete Sedcole and Peter Y. K. Cheung and George A. Constantinides and Wayne Luk}, editor = {Georgi Gaydadjiev and C. John Glossner and Jarmo Takala and Stamatis Vassiliadis}, title = {On-Chip Communication in Run-Time Assembled Reconfigurable Systems}, booktitle = {Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation {(IC-SAMOS} 2006), Samos, Greece, July 17-20, 2006}, pages = {168--176}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/ICSAMOS.2006.300824}, doi = {10.1109/ICSAMOS.2006.300824}, timestamp = {Thu, 25 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/samos/SedcoleCCL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/SedcoleBBAL05, author = {N. Pete Sedcole and Brandon Blodget and Tobias Becker and James Anderson and Patrick Lysaght}, editor = {Tero Rissa and Steven J. E. Wilton and Philip Heng Wai Leong}, title = {Modular Partial Reconfiguration in Virtex FPGAs}, booktitle = {Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005}, pages = {211--216}, publisher = {{IEEE}}, year = {2005}, url = {https://doi.org/10.1109/FPL.2005.1515724}, doi = {10.1109/FPL.2005.1515724}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/SedcoleBBAL05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/SedcoleCCL04, author = {N. Pete Sedcole and Peter Y. K. Cheung and George A. Constantinides and Wayne Luk}, title = {A Structured System Methodology for {FPGA} Based System-on-A-Chip Design}, booktitle = {12th {IEEE} Symposium on Field-Programmable Custom Computing Machines {(FCCM} 2004), 20-23 April 2004, Napa, CA, USA, Proceedings}, pages = {271--272}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/FCCM.2004.10}, doi = {10.1109/FCCM.2004.10}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/SedcoleCCL04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/SedcoleCCL04, author = {N. Pete Sedcole and Peter Y. K. Cheung and George A. Constantinides and Wayne Luk}, editor = {J{\"{u}}rgen Becker and Marco Platzner and Serge Vernalde}, title = {A Structured Methodology for System-on-an-FPGA Design}, booktitle = {Field Programmable Logic and Application, 14th International Conference , {FPL} 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {3203}, pages = {1047--1051}, publisher = {Springer}, year = {2004}, url = {https://doi.org/10.1007/978-3-540-30117-2\_124}, doi = {10.1007/978-3-540-30117-2\_124}, timestamp = {Fri, 19 Jul 2019 13:02:47 +0200}, biburl = {https://dblp.org/rec/conf/fpl/SedcoleCCL04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/SedcoleCCL03, author = {N. Pete Sedcole and Peter Y. K. Cheung and George A. Constantinides and Wayne Luk}, editor = {Peter Y. K. Cheung and George A. Constantinides and Jos{\'{e}} T. de Sousa}, title = {A Reconfigurable Platform for Real-Time Embedded Video Image Processing}, booktitle = {Field Programmable Logic and Application, 13th International Conference, {FPL} 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {2778}, pages = {606--615}, publisher = {Springer}, year = {2003}, url = {https://doi.org/10.1007/978-3-540-45234-8\_59}, doi = {10.1007/978-3-540-45234-8\_59}, timestamp = {Tue, 07 May 2024 20:11:13 +0200}, biburl = {https://dblp.org/rec/conf/fpl/SedcoleCCL03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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