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ORCIDBibTeX records: Simone Secchi
@article{DBLP:journals/symmetry/NojaRS19,
author = {Diego Noja and
Sergio Rolando and
Simone Secchi},
title = {A Note on Sign-Changing Solutions to the {NLS} on the Double-Bridge
Graph},
journal = {Symmetry},
volume = {11},
number = {2},
pages = {161},
year = {2019},
url = {https://doi.org/10.3390/sym11020161},
doi = {10.3390/SYM11020161},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/symmetry/NojaRS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/CerianiSVTP17,
author = {Marco Ceriani and
Simone Secchi and
Oreste Villa and
Antonino Tumeo and
Gianluca Palermo},
title = {Exploring Efficient Hardware Support for Applications with Irregular
Memory Patterns on Multinode Manycore Architectures},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {28},
number = {6},
pages = {1635--1648},
year = {2017},
url = {https://doi.org/10.1109/TPDS.2014.2345073},
doi = {10.1109/TPDS.2014.2345073},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/CerianiSVTP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jpdc/TumeoFVSM15,
author = {Antonino Tumeo and
John Feo and
Oreste Villa and
Simone Secchi and
Timothy G. Mattson},
title = {Special Issue on Architectures and Algorithms for Irregular Applications
{(AAIA)} - Guest editors' introduction},
journal = {J. Parallel Distributed Comput.},
volume = {76},
pages = {1--2},
year = {2015},
url = {https://doi.org/10.1016/j.jpdc.2014.12.001},
doi = {10.1016/J.JPDC.2014.12.001},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jpdc/TumeoFVSM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/SecchiCTVPR13,
author = {Simone Secchi and
Marco Ceriani and
Antonino Tumeo and
Oreste Villa and
Gianluca Palermo and
Luigi Raffo},
title = {Exploring hardware support for scaling irregular applications on multi-node
multi-core architectures},
booktitle = {24th International Conference on Application-Specific Systems, Architectures
and Processors, {ASAP} 2013, Washington, DC, USA, June 5-7, 2013},
pages = {309--313},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ASAP.2013.6567595},
doi = {10.1109/ASAP.2013.6567595},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/SecchiCTVPR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/TuveriSMRC13,
author = {Giuseppe Tuveri and
Simone Secchi and
Paolo Meloni and
Luigi Raffo and
Emanuele Cannella},
title = {A runtime adaptive {H.264} video-decoding MPSoC platform},
booktitle = {2013 Conference on Design and Architectures for Signal and Image Processing,
Cagliari, Italy, October 8-10, 2013},
pages = {149--156},
publisher = {{IEEE}},
year = {2013},
url = {https://ieeexplore.ieee.org/document/6661533/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/TuveriSMRC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/CerianiPSTV13,
author = {Marco Ceriani and
Gianluca Palermo and
Simone Secchi and
Antonino Tumeo and
Oreste Villa},
title = {Exploring Manycore Multinode Systems for Irregular Applications with
{FPGA} Prototyping},
booktitle = {21st {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2013, Seattle, WA, USA, April 28-30, 2013},
pages = {238},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/FCCM.2013.62},
doi = {10.1109/FCCM.2013.62},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/CerianiPSTV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/CerianiSTVP13,
author = {Marco Ceriani and
Simone Secchi and
Antonino Tumeo and
Oreste Villa and
Gianluca Palermo},
title = {Exploring manycore multinode systems for irregular applications with
{FPGA} prototyping},
booktitle = {2013 {IEEE} Hot Chips 25 Symposium (HCS), Stanford University, CA,
USA, August 25-27, 2013},
pages = {1},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2013.7478329},
doi = {10.1109/HOTCHIPS.2013.7478329},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hotchips/CerianiSTVP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rapido/CerianiSTV13,
author = {Marco Ceriani and
Simone Secchi and
Antonino Tumeo and
Oreste Villa},
editor = {Daniel Gracia P{\'{e}}rez and
Morteza Biglari{-}Abhari and
Daniel Chillet and
Gianluca Palermo},
title = {Prototyping hardware support for irregular applications},
booktitle = {Proceedings of the 2013 Workshop on Rapid Simulation and Performance
Evaluation: Methods and Tools, {RAPIDO} '13, 21 January, 2013, Berlin,
Germany},
pages = {4:1--4:8},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2432516.2432520},
doi = {10.1145/2432516.2432520},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rapido/CerianiSTV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/sc/2013ia3,
editor = {Antonino Tumeo and
John Feo and
Oreste Villa and
Simone Secchi},
title = {Proceedings of the 3rd Workshop on Irregular Applications - Architectures
and Algorithms, IA\({}^{\mbox{3}}\) 2013, Denver, Colorado, USA, November
17-22, 2013},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2535753},
doi = {10.1145/2535753},
isbn = {978-1-4503-2503-5},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sc/2013ia3.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/TumeoSV12,
author = {Antonino Tumeo and
Simone Secchi and
Oreste Villa},
title = {Designing Next-Generation Massively Multithreaded Architectures for
Irregular Applications},
journal = {Computer},
volume = {45},
number = {8},
pages = {53--61},
year = {2012},
url = {https://doi.org/10.1109/MC.2012.193},
doi = {10.1109/MC.2012.193},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/TumeoSV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/VillaTSM12,
author = {Oreste Villa and
Antonino Tumeo and
Simone Secchi and
Joseph B. Manzano},
title = {Fast and Accurate Simulation of the Cray {XMT} Multithreaded Supercomputer},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {23},
number = {12},
pages = {2266--2279},
year = {2012},
url = {https://doi.org/10.1109/TPDS.2012.70},
doi = {10.1109/TPDS.2012.70},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/VillaTSM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/MeloniPTSRL12,
author = {Paolo Meloni and
Sebastiano Pomata and
Giuseppe Tuveri and
Simone Secchi and
Luigi Raffo and
Menno Lindwer},
title = {Enabling Fast {ASIP} Design Space Exploration: An FPGA-Based Runtime
Reconfigurable Prototyper},
journal = {{VLSI} Design},
volume = {2012},
pages = {580584:1--580584:16},
year = {2012},
url = {https://doi.org/10.1155/2012/580584},
doi = {10.1155/2012/580584},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/MeloniPTSRL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccgrid/SecchiTV12,
author = {Simone Secchi and
Antonino Tumeo and
Oreste Villa},
title = {A Bandwidth-Optimized Multi-core Architecture for Irregular Applications},
booktitle = {12th {IEEE/ACM} International Symposium on Cluster, Cloud and Grid
Computing, CCGrid 2012, Ottawa, Canada, May 13-16, 2012},
pages = {580--587},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/CCGrid.2012.53},
doi = {10.1109/CCGRID.2012.53},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ccgrid/SecchiTV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbac-pad/MorariTVSV12,
author = {Alessandro Morari and
Antonino Tumeo and
Oreste Villa and
Simone Secchi and
Mateo Valero},
editor = {Jairo Panetta and
Jos{\'{e}} E. Moreira and
David A. Padua and
Philippe O. A. Navaux},
title = {Efficient Sorting on the Tilera Manycore Architecture},
booktitle = {{IEEE} 24th International Symposium on Computer Architecture and High
Performance Computing, {SBAC-PAD} 2012, New York, NY, USA, October
24-26, 2012},
pages = {171--178},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/SBAC-PAD.2012.41},
doi = {10.1109/SBAC-PAD.2012.41},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbac-pad/MorariTVSV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arcs/TumeoSV11,
author = {Antonino Tumeo and
Simone Secchi and
Oreste Villa},
editor = {Mladen Berekovic and
William Fornaciari and
Uwe Brinkschulte and
Cristina Silvano},
title = {Experiences with String Matching on the Fermi Architecture},
booktitle = {Architecture of Computing Systems - {ARCS} 2011 - 24th International
Conference, Como, Italy, February 24-25, 2011. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {6566},
pages = {26--37},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-19137-4\_3},
doi = {10.1007/978-3-642-19137-4\_3},
timestamp = {Wed, 25 Sep 2019 18:15:27 +0200},
biburl = {https://dblp.org/rec/conf/arcs/TumeoSV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ccgrid/SecchiTV11,
author = {Simone Secchi and
Antonino Tumeo and
Oreste Villa},
title = {Contention Modeling for Multithreaded Distributed Shared Memory Machines:
The Cray {XMT}},
booktitle = {11th {IEEE/ACM} International Symposium on Cluster, Cloud and Grid
Computing, CCGrid 2011, Newport Beach, CA, USA, May 23-26, 2011},
pages = {275--284},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/CCGrid.2011.39},
doi = {10.1109/CCGRID.2011.39},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ccgrid/SecchiTV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sc/FeoVTS11,
author = {John Feo and
Oreste Villa and
Antonino Tumeo and
Simone Secchi},
editor = {John Feo and
Oreste Villa and
Antonino Tumeo and
Simone Secchi},
title = {Irregular applications: architectures {\&} algorithms},
booktitle = {Proceedings of the first workshop on Irregular applications: architectures
and algorithm, {IA3} 2011, Seattle, WA, USA, November 13, 2011},
pages = {1--2},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2089142.2089144},
doi = {10.1145/2089142.2089144},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sc/FeoVTS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sc/FeoVTS11a,
author = {John Feo and
Oreste Villa and
Antonino Tumeo and
Simone Secchi},
editor = {John Feo and
Oreste Villa and
Antonino Tumeo and
Simone Secchi},
title = {Towards efficient execution of irregular applications: panel outline},
booktitle = {Proceedings of the first workshop on Irregular applications: architectures
and algorithm, {IA3} 2011, Seattle, WA, USA, November 13, 2011},
pages = {43--44},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2089142.2089154},
doi = {10.1145/2089142.2089154},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sc/FeoVTS11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/sc/2011ia3,
editor = {John Feo and
Oreste Villa and
Antonino Tumeo and
Simone Secchi},
title = {Proceedings of the first workshop on Irregular applications: architectures
and algorithm, {IA3} 2011, Seattle, WA, USA, November 13, 2011},
publisher = {{ACM}},
year = {2011},
url = {http://dl.acm.org/citation.cfm?id=2089142},
isbn = {978-1-4503-1121-2},
timestamp = {Fri, 22 Jan 2016 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sc/2011ia3.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/MeloniSR10,
author = {Paolo Meloni and
Simone Secchi and
Luigi Raffo},
title = {An FPGA-Based Framework for Technology-Aware Prototyping of Multicore
Embedded Architectures},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {2},
number = {1},
pages = {5--9},
year = {2010},
url = {https://doi.org/10.1109/LES.2010.2044365},
doi = {10.1109/LES.2010.2044365},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/MeloniSR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cf/PaniSR10,
author = {Danilo Pani and
Simone Secchi and
Luigi Raffo},
editor = {Nancy M. Amato and
Hubertus Franke and
Paul H. J. Kelly},
title = {Self organization on a swarm computing fabric: a new way to look at
fault tolerance},
booktitle = {Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro,
Italy, May 17-19, 2010},
pages = {327--336},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1787275.1787343},
doi = {10.1145/1787275.1787343},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cf/PaniSR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/SecchiMR10,
author = {Simone Secchi and
Paolo Meloni and
Luigi Raffo},
title = {Exploiting FPGAs for technology-aware system-level evaluation of multi-core
architectures},
booktitle = {{IEEE} International Symposium on Performance Analysis of Systems
and Software, {ISPASS} 2010, 28-30 March 2010, White Plains, NY, {USA}},
pages = {194--202},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ISPASS.2010.5452020},
doi = {10.1109/ISPASS.2010.5452020},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispass/SecchiMR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MeloniSR10,
author = {Paolo Meloni and
Simone Secchi and
Luigi Raffo},
title = {Enabling fast Network-on-Chip topology selection: an FPGA-based runtime
reconfigurable prototyper},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {43--48},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642625},
doi = {10.1109/VLSISOC.2010.5642625},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MeloniSR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/SecchiPPR08,
author = {Simone Secchi and
Francesca Palumbo and
Danilo Pani and
Luigi Raffo},
editor = {Luca Fanucci},
title = {A Network on Chip Architecture for Heterogeneous Traffic Support with
Non-Exclusive Dual-Mode Switching},
booktitle = {11th Euromicro Conference on Digital System Design: Architectures,
Methods and Tools, {DSD} 2008, Parma, Italy, September 3-5, 2008},
pages = {141--148},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/DSD.2008.64},
doi = {10.1109/DSD.2008.64},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/SecchiPPR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/PalumboSPR08,
author = {Francesca Palumbo and
Simone Secchi and
Danilo Pani and
Luigi Raffo},
editor = {Mladen Berekovic and
Nikitas J. Dimopoulos and
Stephan Wong},
title = {A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network
on Chip Designs},
booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation,
8th International Workshop, {SAMOS} 2008, Samos, Greece, July 21-24,
2008. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5114},
pages = {96--105},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-70550-5\_11},
doi = {10.1007/978-3-540-70550-5\_11},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/samos/PalumboSPR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:series/sci/PalumboPRS07,
author = {Francesca Palumbo and
Danilo Pani and
Luigi Raffo and
Simone Secchi},
editor = {Natalio Krasnogor and
Giuseppe Nicosia and
Mario Pavone and
David A. Pelta},
title = {A Surface Tension and Coalescence Model for Dynamic Distributed Resources
Allocation in Massively Parallel Processors on-Chip},
booktitle = {Nature Inspired Cooperative Strategies for Optimization {(NICSO} 2007)},
series = {Studies in Computational Intelligence},
volume = {129},
pages = {335--345},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-78987-1\_30},
doi = {10.1007/978-3-540-78987-1\_30},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/series/sci/PalumboPRS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/appml/PomponioS04,
author = {A. Pomponio and
Simone Secchi},
title = {Interior spikes of a singularly perturbed Neumann problem with potentials},
journal = {Appl. Math. Lett.},
volume = {17},
number = {9},
pages = {1025--1031},
year = {2004},
url = {https://doi.org/10.1016/j.aml.2004.07.004},
doi = {10.1016/J.AML.2004.07.004},
timestamp = {Tue, 29 Jan 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/appml/PomponioS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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