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ORCIDBibTeX records: Leomar S. da Rosa Jr.
@article{DBLP:journals/et/BalenGORSSAMAGMB23,
author = {Tiago R. Balen and
Carlos J. Gonz{\'{a}}lez and
Ingrid F. V. Oliveira and
Leomar S. da Rosa Jr. and
Rafael Iankowski Soares and
Rafael B. Schvittz and
Nemitala Added and
Eduardo L. A. Macchione and
Vitor A. P. Aguiar and
Marcilei Aparecida Guazzelli and
Nilberto H. Medina and
Paulo F. Butzen},
title = {Evaluating the Reliability of Different Voting Schemes for Fault Tolerant
Approximate Systems},
journal = {J. Electron. Test.},
volume = {39},
number = {4},
pages = {409--420},
year = {2023},
url = {https://doi.org/10.1007/s10836-023-06072-9},
doi = {10.1007/S10836-023-06072-9},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/et/BalenGORSSAMAGMB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/educon/JurginaAIRAP23,
author = {Laura Quevedo Jurgina and
Lui Gill Aquini and
Rafael Iankowski Soares and
Leomar Soares da Rosa Jr. and
Marilton Sanchotene de Aguiar and
Tiago Thompsen Primo},
title = {Alfaba: {A} Tangible Solution to Support Brazilian Dyslexic Students
in their Literacy Process},
booktitle = {{IEEE} Global Engineering Education Conference, {EDUCON} 2023, Kuwait,
May 1-4, 2023},
pages = {1--9},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/EDUCON54358.2023.10125140},
doi = {10.1109/EDUCON54358.2023.10125140},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/educon/JurginaAIRAP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/JuniorRM22,
author = {Julio Sara{\c{c}}ol Domingues J{\'{u}}nior and
Leomar Soares da Rosa Jr. and
Felipe de Souza Marques},
title = {Migortho: {A} Design Automation Flow for {QCA} Circuits},
journal = {{IEEE} Des. Test},
volume = {39},
number = {2},
pages = {23--30},
year = {2022},
url = {https://doi.org/10.1109/MDAT.2021.3108072},
doi = {10.1109/MDAT.2021.3108072},
timestamp = {Wed, 27 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/JuniorRM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/OliveiraPSRBS22,
author = {Ingrid F. V. Oliveira and
Matheus F. Pontes and
Rafael B. Schvittz and
Leomar S. da Rosa Jr. and
Paulo F. Butzen and
Rafael Iankowski Soares},
title = {Fault Tolerance Evaluation of Different Majority Voter Designs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {185--189},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9938002},
doi = {10.1109/ISCAS48785.2022.9938002},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/OliveiraPSRBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PontesOSRB22,
author = {Matheus F. Pontes and
Ingrid F. V. Oliveira and
Rafael B. Schvittz and
Leomar Soares da Rosa Jr. and
Paulo F. Butzen},
title = {The Impact of Logic Gates Susceptibility in Overall Circuit Reliability
Analysis},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {1610--1614},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937573},
doi = {10.1109/ISCAS48785.2022.9937573},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/PontesOSRB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KesslerPRC22,
author = {Henrique Kessler and
Marcelo Schiavon Porto and
Leomar Soares da Rosa Jr. and
Vinicius V. Camargo},
title = {Standard Cell and Supergates Designs: An Electrical Comparison on
4-Input Logic Functions},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {1744--1748},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937578},
doi = {10.1109/ISCAS48785.2022.9937578},
timestamp = {Thu, 05 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KesslerPRC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/KesslerBRPC22,
author = {Henrique Kessler and
Murilo Bohlke and
Leomar S. da Rosa and
Marcelo Schiavon Porto and
Vinicius V. Camargo},
title = {Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power
Supergate Design},
booktitle = {13th {IEEE} Latin America Symposium on Circuits and System, {LASCAS}
2022, Puerto Varas, Chile, March 1-4, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/LASCAS53948.2022.9789079},
doi = {10.1109/LASCAS53948.2022.9789079},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/lascas/KesslerBRPC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/ManskeFBR22,
author = {Guilherme B. Manske and
Clayton R. Farias and
Paulo F. Butzen and
Leomar S. da Rosa},
title = {A Fast Approximate Function Generation Method to {ATMR} Architecture},
booktitle = {13th {IEEE} Latin America Symposium on Circuits and System, {LASCAS}
2022, Puerto Varas, Chile, March 1-4, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/LASCAS53948.2022.9789047},
doi = {10.1109/LASCAS53948.2022.9789047},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/lascas/ManskeFBR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/GoncalvesRM20,
author = {Stephano Machado Moreira Goncalves and
Leomar S. da Rosa Jr. and
Felipe S. Marques},
title = {SmartDR: Algorithms and Techniques for Fast Detailed Routing with
Good Design Rule Handling},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {26},
number = {2},
pages = {9:1--9:38},
year = {2021},
url = {https://doi.org/10.1145/3417133},
doi = {10.1145/3417133},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/GoncalvesRM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RaiNMZYYFMPRABC21,
author = {Shubham Rai and
Walter Lau Neto and
Yukio Miyasaka and
Xinpei Zhang and
Mingfei Yu and
Qingyang Yi and
Masahiro Fujita and
Guilherme B. Manske and
Matheus F. Pontes and
Leomar S. da Rosa and
Marilton S. de Aguiar and
Paulo F. Butzen and
Po{-}Chun Chien and
Yu{-}Shan Huang and
Hoa{-}Ren Wang and
Jie{-}Hong R. Jiang and
Jiaqi Gu and
Zheng Zhao and
Zixuan Jiang and
David Z. Pan and
Brunno A. Abreu and
Isac de Souza Campos and
Augusto Andre Souza Berndt and
Cristina Meinhardt and
J{\^{o}}nata Tyska Carvalho and
Mateus Grellert and
Sergio Bampi and
Aditya Lohana and
Akash Kumar and
Wei Zeng and
Azadeh Davoodi and
Rasit Onur Topaloglu and
Yuan Zhou and
Jordan Dotzel and
Yichi Zhang and
Hanyu Wang and
Zhiru Zhang and
Valerio Tenace and
Pierre{-}Emmanuel Gaillardon and
Alan Mishchenko and
Satrajit Chatterjee},
title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1026--1031},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9473972},
doi = {10.23919/DATE51398.2021.9473972},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/RaiNMZYYFMPRABC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GoncalvesRM20,
author = {St{\'{e}}phano M. M. Gon{\c{c}}alves and
Leomar S. da Rosa Jr. and
Felipe de Souza Marques},
title = {{DRAPS:} {A} Design Rule Aware Path Search Algorithm for Detailed
Routing},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {67-II},
number = {7},
pages = {1239--1243},
year = {2020},
url = {https://doi.org/10.1109/TCSII.2019.2937893},
doi = {10.1109/TCSII.2019.2937893},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/GoncalvesRM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KesslerFBRC20,
author = {Henrique Kessler and
Plinio Finkenauer and
Thiago H. Both and
Leomar Soares da Rosa Jr. and
Vinicius V. Camargo},
title = {Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated
Design Methodologies},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180594},
doi = {10.1109/ISCAS45731.2020.9180594},
timestamp = {Thu, 05 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KesslerFBRC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SchvittzBR20,
author = {Rafael B. Schvittz and
Paulo F. Butzen and
Leomar S. da Rosa},
title = {Methods for Susceptibility Analysis of Logic Gates in the Presence
of Single Event Transients},
booktitle = {{IEEE} International Test Conference, {ITC} 2020, Washington, DC,
USA, November 1-6, 2020},
pages = {1--9},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ITC44778.2020.9325252},
doi = {10.1109/ITC44778.2020.9325252},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/itc/SchvittzBR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/DominguesRM20,
author = {Julio Sara{\c{c}}ol Domingues J{\'{u}}nior and
Leomar Soares da Rosa Jr. and
Felipe de Souza Marques},
title = {A Straightforward Methodology for {QCA} Circuits Design},
booktitle = {33rd Symposium on Integrated Circuits and Systems Design, {SBCCI}
2020, Campinas, Brazil, August 24-28, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/SBCCI50935.2020.9189930},
doi = {10.1109/SBCCI50935.2020.9189930},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/DominguesRM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2012-02530,
author = {Shubham Rai and
Walter Lau Neto and
Yukio Miyasaka and
Xinpei Zhang and
Mingfei Yu and
Qingyang Yi and
Masahiro Fujita and
Guilherme B. Manske and
Matheus F. Pontes and
Leomar S. da Rosa Jr. and
Marilton S. de Aguiar and
Paulo F. Butzen and
Po{-}Chun Chien and
Yu{-}Shan Huang and
Hoa{-}Ren Wang and
Jie{-}Hong R. Jiang and
Jiaqi Gu and
Zheng Zhao and
Zixuan Jiang and
David Z. Pan and
Brunno A. Abreu and
Isac de Souza Campos and
Augusto Andre Souza Berndt and
Cristina Meinhardt and
J{\^{o}}nata Tyska Carvalho and
Mateus Grellert and
Sergio Bampi and
Aditya Lohana and
Akash Kumar and
Wei Zeng and
Azadeh Davoodi and
Rasit Onur Topaloglu and
Yuan Zhou and
Jordan Dotzel and
Yichi Zhang and
Hanyu Wang and
Zhiru Zhang and
Valerio Tenace and
Pierre{-}Emmanuel Gaillardon and
Alan Mishchenko and
Satrajit Chatterjee},
title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
journal = {CoRR},
volume = {abs/2012.02530},
year = {2020},
url = {https://arxiv.org/abs/2012.02530},
eprinttype = {arXiv},
eprint = {2012.02530},
timestamp = {Thu, 24 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2012-02530.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GoncalvesRM19,
author = {St{\'{e}}phano M. M. Gon{\c{c}}alves and
Leomar S. da Rosa and
Felipe S. de Marques},
title = {An Improved Heuristic Function for A{\({_\ast}\)}-Based Path Search
in Detailed Routing},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702460},
doi = {10.1109/ISCAS.2019.8702460},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/GoncalvesRM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LimaPRRMCCSB19,
author = {Vitor G. Lima and
Guilherme Paim and
Leandro M. G. Rocha and
Leomar S. da Rosa Jr. and
Felipe S. Marques and
Eduardo A. C. da Costa and
Vinicius V. Camargo and
Rafael Soares and
Sergio Bampi},
title = {Maximizing Side Channel Attack-Resistance and Energy-Efficiency of
the {STTL} Combining Multi-Vt Transistors with Current and Capacitance
Balancing},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702687},
doi = {10.1109/ISCAS.2019.8702687},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LimaPRRMCCSB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchvittzFRB19,
author = {Rafael B. Schvittz and
Denis Teixeira Franco and
Leomar S. da Rosa and
Paulo F. Butzen},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {An Improved Technique for Logic Gate Susceptibility Evaluation of
Single Event Transient Faults},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {69--88},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_4},
doi = {10.1007/978-3-030-53273-4\_4},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SchvittzFRB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/CardosoSBMRM18,
author = {Maicon Schneider Cardoso and
Gustavo H. Smaniotto and
Andrei A. O. Bubolz and
Matheus T. Moreira and
Leomar S. da Rosa Jr. and
Felipe de Souza Marques},
title = {Libra: An Automatic Design Methodology for {CMOS} Complex Gates},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {65-II},
number = {10},
pages = {1345--1349},
year = {2018},
url = {https://doi.org/10.1109/TCSII.2018.2866231},
doi = {10.1109/TCSII.2018.2866231},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/CardosoSBMRM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SchvittzFRB18,
author = {Rafael B. Schvittz and
Denis Teixeira Franco and
Leomar S. da Rosa Jr. and
Paulo F. Butzen},
title = {Probabilistic Method for Reliability Estimation of {SP-} Networks
considering Single Event Transient Faults},
booktitle = {25th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2018, Bordeaux, France, December 9-12, 2018},
pages = {357--360},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICECS.2018.8617918},
doi = {10.1109/ICECS.2018.8617918},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/SchvittzFRB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PontesBSRF18,
author = {Matheus F. Pontes and
Paulo F. Butzen and
Rafael B. Schvittz and
Leomar S. da Rosa Jr. and
Denis Teixeira Franco},
title = {The Suitability of the {SPR-MP} Method to Evaluate the Reliability
of Logic Circuits},
booktitle = {25th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2018, Bordeaux, France, December 9-12, 2018},
pages = {433--436},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICECS.2018.8617852},
doi = {10.1109/ICECS.2018.8617852},
timestamp = {Thu, 05 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/PontesBSRF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/SchvittzPMFNRB18,
author = {Rafael B. Schvittz and
Matheus F. Pontes and
Cristina Meinhardt and
Denis Teixeira Franco and
Lirida A. B. Naviner and
Leomar S. da Rosa and
Paulo F. Butzen},
title = {Reliability evaluation of circuits designed in multi- and single-stage
versions},
booktitle = {9th {IEEE} Latin American Symposium on Circuits {\&} Systems,
{LASCAS} 2018, Puerto Vallarta, Mexico, February 25-28, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/LASCAS.2018.8399927},
doi = {10.1109/LASCAS.2018.8399927},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/lascas/SchvittzPMFNRB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/newcas/GoncalvesRM18,
author = {St{\'{e}}phano M. M. Gon{\c{c}}alves and
Leomar S. da Rosa and
Felipe S. de Marques},
title = {A New Technique Using Tunnel Shape Information to Improve Path Search
in Detailed Routing},
booktitle = {16th {IEEE} International New Circuits and Systems Conference, {NEWCAS}
2018, Montr{\'{e}}al, QC, Canada, June 24-27, 2018},
pages = {243--247},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NEWCAS.2018.8585609},
doi = {10.1109/NEWCAS.2018.8585609},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/newcas/GoncalvesRM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/newcas/CardosoSBJM18,
author = {Maicon Schneider Cardoso and
Gustavo H. Smaniotto and
Andrei A. O. Bubolz and
Leomar S. da Rosa Jr. and
Felipe S. Marques},
title = {Area-Aware Design of Static {CMOS} Complex Gates},
booktitle = {16th {IEEE} International New Circuits and Systems Conference, {NEWCAS}
2018, Montr{\'{e}}al, QC, Canada, June 24-27, 2018},
pages = {282--286},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NEWCAS.2018.8585570},
doi = {10.1109/NEWCAS.2018.8585570},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/newcas/CardosoSBJM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PossaniRRMR17,
author = {Vinicius N. Possani and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas and
Felipe S. Marques and
Leomar S. da Rosa Jr.},
title = {Transistor Count Optimization in {IG} FinFET Network Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {9},
pages = {1483--1496},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2016.2629451},
doi = {10.1109/TCAD.2016.2629451},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/PossaniRRMR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SmaniottoZCSMMR17,
author = {Gustavo H. Smaniotto and
Regis Zanandrea and
Maicon Schneider Cardoso and
Renato Souza de Souza and
Matheus T. Moreira and
Felipe S. Marques and
Leomar S. da Rosa Jr.},
title = {A post-processing methodology to improve the automatic design of {CMOS}
gates at layout-level},
booktitle = {24th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2017, Batumi, Georgia, December 5-8, 2017},
pages = {42--45},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICECS.2017.8292073},
doi = {10.1109/ICECS.2017.8292073},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/SmaniottoZCSMMR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GoncalvesRM17,
author = {Stephano Machado Moreira Goncalves and
Leomar S. da Rosa Jr. and
Felipe de Souza Marques},
title = {A survey of path search algorithms for {VLSI} detailed routing},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050432},
doi = {10.1109/ISCAS.2017.8050432},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GoncalvesRM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SmaniottoZCSMMR17,
author = {Gustavo H. Smaniotto and
Regis Zanandrea and
Maicon Schneider Cardoso and
Renato Souza de Souza and
Matheus T. Moreira and
Felipe S. Marques and
Leomar S. da Rosa Jr.},
title = {Post-processing of supergate networks aiming cell layout optimization},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050570},
doi = {10.1109/ISCAS.2017.8050570},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/SmaniottoZCSMMR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/CardosoSMMRM17,
author = {Maicon Schneider Cardoso and
Gustavo H. Smaniotto and
Joao Junior da Silva Machado and
Matheus T. Moreira and
Leomar S. da Rosa and
Felipe de Souza Marques},
title = {Transistor placement strategies for non-series-parallel cells},
booktitle = {{IEEE} 60th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2017, Boston, MA, USA, August 6-9, 2017},
pages = {523--526},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MWSCAS.2017.8052975},
doi = {10.1109/MWSCAS.2017.8052975},
timestamp = {Tue, 10 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/CardosoSMMRM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PossaniCRRMR16,
author = {Vinicius Neves Possani and
Vinicius Callegaro and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas and
Felipe de Souza Marques and
Leomar Soares da Rosa Jr.},
title = {Graph-Based Transistor Network Generation Method for Supergate Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {2},
pages = {692--705},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2410764},
doi = {10.1109/TVLSI.2015.2410764},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PossaniCRRMR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/CardosoZSMRM16,
author = {Maicon Schneider Cardoso and
Regis Zanandrea and
Renato Souza de Souza and
Joao Junior da Silva Machado and
Leomar Soares da Rosa Jr. and
Felipe de Souza Marques},
title = {Topological characteristics of logic networks generated by a graph-based
methodology},
booktitle = {{IEEE} 7th Latin American Symposium on Circuits {\&} Systems,
{LASCAS} 2016, Florianopolis, Brazil, February 28 - March 2, 2016},
pages = {343--346},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/LASCAS.2016.7451080},
doi = {10.1109/LASCAS.2016.7451080},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/lascas/CardosoZSMRM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/SmaniottoMMZMR16,
author = {Gustavo H. Smaniotto and
Joao Junior da Silva Machado and
Matheus T. Moreira and
Adriel Mota Ziesemer and
Felipe S. Marques and
Leomar S. da Rosa Jr.},
title = {Optimizing cell area by applying an alternative transistor folding
technique in an open source physical synthesis {CAD} tool},
booktitle = {{IEEE} 7th Latin American Symposium on Circuits {\&} Systems,
{LASCAS} 2016, Florianopolis, Brazil, February 28 - March 2, 2016},
pages = {355--358},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/LASCAS.2016.7451083},
doi = {10.1109/LASCAS.2016.7451083},
timestamp = {Tue, 10 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/lascas/SmaniottoMMZMR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/CardosoSZSRM16,
author = {Maicon Schneider Cardoso and
Gustavo H. Smaniotto and
Regis Zanandrea and
Renato Souza de Souza and
Leomar S. da Rosa and
Felipe de Souza Marques},
title = {Physical design of supergate cells aiming geometrical optimizations},
booktitle = {{IEEE} 59th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/MWSCAS.2016.7870091},
doi = {10.1109/MWSCAS.2016.7870091},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/CardosoSZSRM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/SmaniottoMZMR16,
author = {Gustavo H. Smaniotto and
Matheus T. Moreira and
Adriel Mota Ziesemer and
Felipe S. Marques and
Leomar S. da Rosa},
title = {Toward better layout design in {ASTRAN} {CAD} tool by using an efficient
transistor folding},
booktitle = {{IEEE} 59th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/MWSCAS.2016.7870097},
doi = {10.1109/MWSCAS.2016.7870097},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/SmaniottoMZMR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/CardosoRM15,
author = {Maicon Schneider Cardoso and
Leomar Soares da Rosa Jr. and
Felipe de Souza Marques},
editor = {Robson Nunes de Lima and
Ana Isabela Ara{\'{u}}jo Cunha and
Calvin Plett and
Wagner Luiz Alves de Oliveira},
title = {Evaluating Geometric Aspects of Non-Series-Parallel Cells},
booktitle = {Proceedings of the 28th Symposium on Integrated Circuits and Systems
Design, {SBCCI} 2015, Salvador, Brazil, August 31 - September 4, 2015},
pages = {16:1--16:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2800986.2801008},
doi = {10.1145/2800986.2801008},
timestamp = {Tue, 06 Nov 2018 16:58:27 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/CardosoRM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/GoncalvesJM14,
author = {Stephano Machado Moreira Goncalves and
Leomar Soares da Rosa Jr. and
Felipe de Souza Marques},
title = {A new general purpose line probe routing algorithm},
booktitle = {21st {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2014, Marseille, France, December 7-10, 2014},
pages = {658--661},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICECS.2014.7050071},
doi = {10.1109/ICECS.2014.7050071},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/GoncalvesJM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/PossaniRRMJ14,
author = {Vinicius N. Possani and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas and
Felipe S. Marques and
Leomar Soares da Rosa Jr.},
editor = {Edward David Moreno Ordonez and
Rodolfo Jardim de Azevedo and
Peter R. Kinget},
title = {Exploring Independent Gates in FinFET-Based Transistor Network Generation},
booktitle = {Proceedings of the 27th Symposium on Integrated Circuits and Systems
Design, Aracaju, Brazil, September 1-5, 2014},
pages = {41:1--41:6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2660540.2661009},
doi = {10.1145/2660540.2661009},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/PossaniRRMJ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PossaniCRRMJ13,
author = {Vinicius N. Possani and
Vinicius Callegaro and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas and
Felipe de Souza Marques and
Leomar Soares da Rosa Jr.},
editor = {Jos{\'{e}} Luis Ayala and
Alex K. Jones and
Patrick H. Madden and
Ayse K. Coskun},
title = {Efficient transistor-level design of {CMOS} gates},
booktitle = {Great Lakes Symposium on {VLSI} 2013 (part of ECRC), GLSVLSI'13, Paris,
France, May 2-4, 2013},
pages = {191--196},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2483028.2483089},
doi = {10.1145/2483028.2483089},
timestamp = {Fri, 10 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/PossaniCRRMJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/PossaniMRCRR13,
author = {Vinicius N. Possani and
Felipe S. Marques and
Leomar S. da Rosa Jr. and
Vinicius Callegaro and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Transistor-level optimization of {CMOS} complex gates},
booktitle = {4th {IEEE} Latin American Symposium on Circuits and Systems, {LASCAS}
2013, Cusco, Peru, February 27 - March 1, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/LASCAS.2013.6519029},
doi = {10.1109/LASCAS.2013.6519029},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/lascas/PossaniMRCRR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/PossaniCRRMR13,
author = {Vinicius N. Possani and
Vinicius Callegaro and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas and
Felipe S. Marques and
Leomar S. da Rosa Jr.},
title = {Improving the methodology to build non-series-parallel transistor
arrangements},
booktitle = {26th Symposium on Integrated Circuits and Systems Design, {SBCCI}
2013, Curitiba, Brazil, September 2-6, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/SBCCI.2013.6644854},
doi = {10.1109/SBCCI.2013.6644854},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/PossaniCRRMR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mta/TrojahnGMAR12,
author = {Tiago Henrique Trojahn and
Juliano Lucas Gon{\c{c}}alves and
J{\'{u}}lio Carlos Balzano de Mattos and
Luciano Volcan Agostini and
Leomar Soares da Rosa Jr.},
title = {Evaluating two implementations of the component responsible for decoding
video and audio in the Brazilian digital {TV} middleware},
journal = {Multim. Tools Appl.},
volume = {57},
number = {2},
pages = {373--392},
year = {2012},
url = {https://doi.org/10.1007/s11042-011-0753-x},
doi = {10.1007/S11042-011-0753-X},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mta/TrojahnGMAR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/PossaniMRCRR12,
author = {Vinicius N. Possani and
Felipe S. Marques and
Leomar S. da Rosa Jr. and
Vinicius Callegaro and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {{NSP} kernel finder - {A} methodology to find and to build non-series-parallel
transistor arrangements},
booktitle = {25th Symposium on Integrated Circuits and Systems Design, {SBCCI}
2012, Brasilia, Brazil, August 30 - September 2, 2012},
pages = {1--6},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/SBCCI.2012.6344452},
doi = {10.1109/SBCCI.2012.6344452},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/PossaniMRCRR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijitcc/TrojahnGMAJ11,
author = {Tiago Henrique Trojahn and
Juliano Lucas Gon{\c{c}}alves and
J{\'{u}}lio Carlos Balzano de Mattos and
Luciano Volcan Agostini and
Leomar Soares da Rosa Jr.},
title = {A comparative analysis of media processing component implementations
for the Brazilian digital {TV} middleware},
journal = {Int. J. Inf. Technol. Commun. Convergence},
volume = {1},
number = {4},
pages = {391--409},
year = {2011},
url = {https://doi.org/10.1504/IJITCC.2011.044642},
doi = {10.1504/IJITCC.2011.044642},
timestamp = {Thu, 04 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijitcc/TrojahnGMAJ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mue/TrojahnGMAJ11,
author = {Tiago Henrique Trojahn and
Juliano Lucas Gon{\c{c}}alves and
J{\'{u}}lio C. B. de Mattos and
Luciano Volcan Agostini and
Leomar Soares da Rosa Jr.},
title = {Tests and Performance Analysis of Media Processing Implementations
for the Middleware of Brazilian Digital {TV} System Using Different
Scenarios},
booktitle = {5th {FTRA} International Conference on Multimedia and Ubiquitous Engineering,
{MUE} 2011, Crete, Greece, 28-30 June, 2011},
pages = {95--100},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/MUE.2011.28},
doi = {10.1109/MUE.2011.28},
timestamp = {Thu, 05 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mue/TrojahnGMAJ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/ButzenRFRR10,
author = {Paulo F. Butzen and
Leomar S. da Rosa Jr. and
Erasmo J. D. Chiappetta Filho and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Standby power consumption estimation by interacting leakage current
mechanisms in nanoscaled {CMOS} digital circuits},
journal = {Microelectron. J.},
volume = {41},
number = {4},
pages = {247--255},
year = {2010},
url = {https://doi.org/10.1016/j.mejo.2010.03.003},
doi = {10.1016/J.MEJO.2010.03.003},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/ButzenRFRR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/MartinsRRRR10,
author = {Mayler G. A. Martins and
Leomar S. da Rosa Jr. and
Anders B. Rasmussen and
Renato P. Ribas and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {Boolean factoring with multi-objective goals},
booktitle = {28th International Conference on Computer Design, {ICCD} 2010, 3-6
October 2010, Amsterdam, The Netherlands, Proceedings},
pages = {229--234},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ICCD.2010.5647772},
doi = {10.1109/ICCD.2010.5647772},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/MartinsRRRR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/CallegaroMKRRR10,
author = {Vinicius Callegaro and
Felipe de Souza Marques and
Carlos Eduardo Klock and
Leomar Soares da Rosa Jr. and
Renato P. Ribas and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {Jo{\~{a}}o Antonio Martino and
Guido Araujo and
Alex Orailoglu and
Felipe Klein},
title = {SwitchCraft: a framework for transistor network design},
booktitle = {Proceedings of the 23rd Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2010, S{\~{a}}o Paulo, Brazil, September 6-9,
2010},
pages = {49--53},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1854153.1854167},
doi = {10.1145/1854153.1854167},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/CallegaroMKRRR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/RosaSRR09,
author = {Leomar S. da Rosa Jr. and
Felipe Ribeiro Schneider and
Renato P. Ribas and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {Switch level optimization of digital {CMOS} gate networks},
booktitle = {10th International Symposium on Quality of Electronic Design {(ISQED}
2009), 16-18 March 2009, San Jose, CA, {USA}},
pages = {324--329},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISQED.2009.4810315},
doi = {10.1109/ISQED.2009.4810315},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/RosaSRR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ButzenRFMRR08,
author = {Paulo F. Butzen and
Leomar S. da Rosa Jr. and
Erasmo J. D. Chiappetta Filho and
Dionatan S. Moura and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
editor = {Vijaykrishnan Narayanan and
Zhiyuan Yan and
Enrico Macii and
Sanjukta Bhanja},
title = {Simple and accurate method for fast static currentestimation in cmos
complex gates with interaction ofleakage mechanisms},
booktitle = {Proceedings of the 18th {ACM} Great Lakes Symposium on {VLSI} 2008,
Orlando, Florida, USA, May 4-6, 2008},
pages = {407--410},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1366110.1366207},
doi = {10.1145/1366110.1366207},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ButzenRFMRR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/CardosoRMRR08,
author = {Tiago Muller Gil Cardoso and
Leomar S. da Rosa Jr. and
Felipe de Souza Marques and
Renato P. Ribas and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis
Including Reordering},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {47--52},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479696},
doi = {10.1109/ISQED.2008.4479696},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/CardosoRMRR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MarquesRRSR07,
author = {Felipe S. Marques and
Leomar S. da Rosa Jr. and
Renato P. Ribas and
Sachin S. Sapatnekar and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {{DAG} based library-free technology mapping},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {293--298},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228857},
doi = {10.1145/1228784.1228857},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/MarquesRRSR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/RosaRRMS07,
author = {Leomar S. da Rosa Jr. and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas and
Felipe de Souza Marques and
Felipe Ribeiro Schneider},
editor = {Antonio Petraglia and
Volnei A. Pedroni and
Gert Cauwenberghs},
title = {A comparative study of {CMOS} gates with minimum transistor stacks},
booktitle = {Proceedings of the 20th Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2007, Copacabana, Rio de Janeiro, Brazil,
September 3-6, 2007},
pages = {93--98},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1284480.1284511},
doi = {10.1145/1284480.1284511},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/RosaRRMS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/RosaMCRSR06,
author = {Leomar S. da Rosa Jr. and
Felipe S. Marques and
Tiago Muller Gil Cardoso and
Renato P. Ribas and
Sachin S. Sapatnekar and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {Claudionor Jos{\'{e}} Nunes Coelho Jr. and
Ricardo P. Jacobi and
J{\"{u}}rgen Becker},
title = {Fast disjoint transistor networks from BDDs},
booktitle = {Proceedings of the 19th Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2006, Ouro Preto, MG, Brazil, August 28 -
September 1, 2006},
pages = {137--142},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1150343.1150381},
doi = {10.1145/1150343.1150381},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/RosaMCRSR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/otm/RosaWCCR03,
author = {Leomar S. da Rosa Jr. and
Fl{\'{a}}vio Rech Wagner and
Luigi Carro and
Alexandre Carissimi and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {Robert Meersman and
Zahir Tari},
title = {Scheduling Policy Costs on a {JAVA} Microcontroller},
booktitle = {On The Move to Meaningful Internet Systems 2003: {OTM} 2003 Workshops,
{OTM} Confederated International Workshops, HCI-SWWA, IPW, JTRES,
WORM, WMS, and {WRSM} 2003, Catania, Sicily, Italy, November 3-7,
2003, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2889},
pages = {520--533},
publisher = {Springer},
year = {2003},
url = {https://doi.org/10.1007/978-3-540-39962-9\_57},
doi = {10.1007/978-3-540-39962-9\_57},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/otm/RosaWCCR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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