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ORCIDBibTeX records: Jude A. Rivers
@article{DBLP:journals/tecs/LuLPGR17,
author = {Qining Lu and
Guanpeng Li and
Karthik Pattabiraman and
Meeta Sharma Gupta and
Jude A. Rivers},
title = {Configurable Detection of SDC-causing Errors in Programs},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {16},
number = {3},
pages = {88:1--88:25},
year = {2017},
url = {https://doi.org/10.1145/3014586},
doi = {10.1145/3014586},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/LuLPGR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/LuPGR14,
author = {Qining Lu and
Karthik Pattabiraman and
Meeta Sharma Gupta and
Jude A. Rivers},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {SDCTune: {A} model for predicting the {SDC} proneness of an application
for configurable protection},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {23:1--23:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656127},
doi = {10.1145/2656106.2656127},
timestamp = {Mon, 15 May 2023 22:11:16 +0200},
biburl = {https://dblp.org/rec/conf/cases/LuPGR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/SunKRX13,
author = {Guangyu Sun and
Eren Kursun and
Jude A. Rivers and
Yuan Xie},
title = {Exploring the vulnerability of CMPs to soft errors with 3D stacked
nonvolatile memory},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {9},
number = {3},
pages = {22:1--22:22},
year = {2013},
url = {https://doi.org/10.1145/2491679},
doi = {10.1145/2491679},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/SunKRX13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BoseBDGHJNRSVW12,
author = {Pradip Bose and
Alper Buyuktosunoglu and
John A. Darringer and
Meeta Sharma Gupta and
Michael B. Healy and
Hans M. Jacobson and
Indira Nair and
Jude A. Rivers and
Jeonghee Shin and
Augusto Vega and
Alan J. Weger},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {Power management of multi-core chips: Challenges and pitfalls},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {977--982},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176638},
doi = {10.1109/DATE.2012.6176638},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BoseBDGHJNRSVW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RiversGSKB11,
author = {Jude A. Rivers and
Meeta Sharma Gupta and
Jeonghee Shin and
Prabhakar Kudva and
Pradip Bose},
title = {Error Tolerance in Server Class Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {7},
pages = {945--959},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2158100},
doi = {10.1109/TCAD.2011.2158100},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RiversGSKB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/SunKRX11,
author = {Guangyu Sun and
Eren Kursun and
Jude A. Rivers and
Yuan Xie},
title = {Exploring the vulnerability of CMPs to soft errors with 3D stacked
non-volatile memory},
booktitle = {{IEEE} 29th International Conference on Computer Design, {ICCD} 2011,
Amherst, MA, USA, October 9-12, 2011},
pages = {366--372},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCD.2011.6081425},
doi = {10.1109/ICCD.2011.6081425},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/SunKRX11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BoseBCDGHJKKMNRSWZ10,
author = {Pradip Bose and
Alper Buyuktosunoglu and
Chen{-}Yong Cher and
John A. Darringer and
Meeta Sharma Gupta and
Hendrik F. Hamann and
Hans M. Jacobson and
Prabhakar Kudva and
Eren Kursun and
Niti Madan and
Indira Nair and
Jude A. Rivers and
Jeonghee Shin and
Alan J. Weger and
Victor V. Zyuban},
editor = {R. Iris Bahar and
Fabrizio Lombardi and
David Atienza and
Erik Brunvand},
title = {Power-efficient, reliable microprocessor architectures: modeling and
design methods},
booktitle = {Proceedings of the 20th {ACM} Great Lakes Symposium on {VLSI} 2009,
Providence, Rhode Island, USA, May 16-18 2010},
pages = {299--304},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1785481.1785551},
doi = {10.1145/1785481.1785551},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/BoseBCDGHJKKMNRSWZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/SeongWSRL10,
author = {Nak Hee Seong and
Dong Hyuk Woo and
Vijayalakshmi Srinivasan and
Jude A. Rivers and
Hsien{-}Hsin S. Lee},
title = {{SAFER:} Stuck-At-Fault Error Recovery for Memories},
booktitle = {43rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
{MICRO} 2010, 4-8 December 2010, Atlanta, Georgia, {USA}},
pages = {115--124},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/MICRO.2010.46},
doi = {10.1109/MICRO.2010.46},
timestamp = {Tue, 31 May 2022 14:39:58 +0200},
biburl = {https://dblp.org/rec/conf/micro/SeongWSRL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/RiversK09,
author = {Jude A. Rivers and
Prabhakar Kudva},
title = {Reliability Challenges and System Performance at the Architecture
Level},
journal = {{IEEE} Des. Test Comput.},
volume = {26},
number = {6},
pages = {62--73},
year = {2009},
url = {https://doi.org/10.1109/MDT.2009.153},
doi = {10.1109/MDT.2009.153},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/RiversK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/QureshiSR09,
author = {Moinuddin K. Qureshi and
Vijayalakshmi Srinivasan and
Jude A. Rivers},
editor = {Stephen W. Keckler and
Luiz Andr{\'{e}} Barroso},
title = {Scalable high performance main memory system using phase-change memory
technology},
booktitle = {36th International Symposium on Computer Architecture {(ISCA} 2009),
June 20-24, 2009, Austin, TX, {USA}},
pages = {24--33},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1555754.1555760},
doi = {10.1145/1555754.1555760},
timestamp = {Fri, 09 Jul 2021 15:51:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/QureshiSR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/GuptaRBWB09,
author = {Meeta Sharma Gupta and
Jude A. Rivers and
Pradip Bose and
Gu{-}Yeon Wei and
David M. Brooks},
editor = {David H. Albonesi and
Margaret Martonosi and
David I. August and
Jos{\'{e}} F. Mart{\'{\i}}nez},
title = {Tribeca: design for {PVT} variations with local recovery and fine-grained
adaptation},
booktitle = {42st Annual {IEEE/ACM} International Symposium on Microarchitecture
{(MICRO-42} 2009), December 12-16, 2009, New York, New York, {USA}},
pages = {435--446},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1669112.1669168},
doi = {10.1145/1669112.1669168},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/GuptaRBWB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/RiversBKWSCA08,
author = {Jude A. Rivers and
Pradip Bose and
Prabhakar Kudva and
John{-}David Wellman and
Pia N. Sanda and
Ethan H. Cannon and
Luiz C. Alves},
title = {Phaser: Phased methodology for modeling the system-level effects of
soft errors},
journal = {{IBM} J. Res. Dev.},
volume = {52},
number = {3},
pages = {293--306},
year = {2008},
url = {https://doi.org/10.1147/rd.523.0293},
doi = {10.1147/RD.523.0293},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/RiversBKWSCA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/LiABR08,
author = {Xiaodong Li and
Sarita V. Adve and
Pradip Bose and
Jude A. Rivers},
title = {Online Estimation of Architectural Vulnerability Factor for Soft Errors},
booktitle = {35th International Symposium on Computer Architecture {(ISCA} 2008),
June 21-25, 2008, Beijing, China},
pages = {341--352},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISCA.2008.9},
doi = {10.1109/ISCA.2008.9},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/LiABR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/RamachandranABR08,
author = {Pradeep Ramachandran and
Sarita V. Adve and
Pradip Bose and
Jude A. Rivers},
title = {Metrics for Architecture-Level Lifetime Reliability Analysis},
booktitle = {{IEEE} International Symposium on Performance Analysis of Systems
and Software, {ISPASS} 2008, April 20-22, 2008, Austin, Texas, USA,
Proceedings},
pages = {202--212},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISPASS.2008.4510752},
doi = {10.1109/ISPASS.2008.4510752},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispass/RamachandranABR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsn/LiABR07,
author = {Xiaodong Li and
Sarita V. Adve and
Pradip Bose and
Jude A. Rivers},
title = {Architecture-Level Soft Error Analysis: Examining the Limits of Common
Assumptions},
booktitle = {The 37th Annual {IEEE/IFIP} International Conference on Dependable
Systems and Networks, {DSN} 2007, 25-28 June 2007, Edinburgh, UK,
Proceedings},
pages = {266--275},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/DSN.2007.15},
doi = {10.1109/DSN.2007.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsn/LiABR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsn/ShinZHRB07,
author = {Jeonghee Shin and
Victor V. Zyuban and
Zhigang Hu and
Jude A. Rivers and
Pradip Bose},
title = {A Framework for Architecture-Level Lifetime Reliability Modeling},
booktitle = {The 37th Annual {IEEE/IFIP} International Conference on Dependable
Systems and Networks, {DSN} 2007, 25-28 June 2007, Edinburgh, UK,
Proceedings},
pages = {534--543},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/DSN.2007.8},
doi = {10.1109/DSN.2007.8},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsn/ShinZHRB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/SrinivasanABR05,
author = {Jayanth Srinivasan and
Sarita V. Adve and
Pradip Bose and
Jude A. Rivers},
title = {Lifetime Reliability: Toward an Architectural Solution},
journal = {{IEEE} Micro},
volume = {25},
number = {3},
pages = {70--80},
year = {2005},
url = {https://doi.org/10.1109/MM.2005.54},
doi = {10.1109/MM.2005.54},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/SrinivasanABR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsn/LiABR05,
author = {Xiaodong Li and
Sarita V. Adve and
Pradip Bose and
Jude A. Rivers},
title = {SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft
Errors},
booktitle = {2005 International Conference on Dependable Systems and Networks {(DSN}
2005), 28 June - 1 July 2005, Yokohama, Japan, Proceedings},
pages = {496--505},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DSN.2005.88},
doi = {10.1109/DSN.2005.88},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsn/LiABR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/SrinivasanABR05,
author = {Jayanth Srinivasan and
Sarita V. Adve and
Pradip Bose and
Jude A. Rivers},
title = {Exploiting Structural Duplication for Lifetime Reliability Enhancement},
booktitle = {32st International Symposium on Computer Architecture {(ISCA} 2005),
4-8 June 2005, Madison, Wisconsin, {USA}},
pages = {520--531},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISCA.2005.28},
doi = {10.1109/ISCA.2005.28},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/SrinivasanABR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsn/SrinivasanABR04,
author = {Jayanth Srinivasan and
Sarita V. Adve and
Pradip Bose and
Jude A. Rivers},
title = {The Impact of Technology Scaling on Lifetime Reliability},
booktitle = {2004 International Conference on Dependable Systems and Networks {(DSN}
2004), 28 June - 1 July 2004, Florence, Italy, Proceedings},
pages = {177},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DSN.2004.1311888},
doi = {10.1109/DSN.2004.1311888},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsn/SrinivasanABR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/SrinivasanABR04,
author = {Jayanth Srinivasan and
Sarita V. Adve and
Pradip Bose and
Jude A. Rivers},
title = {The Case for Lifetime Reliability-Aware Microprocessors},
booktitle = {31st International Symposium on Computer Architecture {(ISCA} 2004),
19-23 June 2004, Munich, Germany},
pages = {276--287},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISCA.2004.1310781},
doi = {10.1109/ISCA.2004.1310781},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/SrinivasanABR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/RiversAWM03,
author = {Jude A. Rivers and
Sameh W. Asaad and
John{-}David Wellman and
Jaime H. Moreno},
editor = {Ingrid Verbauwhede and
Hyung Roh},
title = {Reducing instruction fetch energy with backwards branch control information
and buffering},
booktitle = {Proceedings of the 2003 International Symposium on Low Power Electronics
and Design, 2003, Seoul, Korea, August 25-27, 2003},
pages = {322--325},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/871506.871586},
doi = {10.1145/871506.871586},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/RiversAWM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/TamRSTD99,
author = {Edward S. Tam and
Jude A. Rivers and
Vijayalakshmi Srinivasan and
Gary S. Tyson and
Edward S. Davidson},
title = {Active Management of Data Caches by Exploiting Reuse Information},
journal = {{IEEE} Trans. Computers},
volume = {48},
number = {11},
pages = {1244--1259},
year = {1999},
url = {https://doi.org/10.1109/12.811113},
doi = {10.1109/12.811113},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/TamRSTD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/us/Rivers98,
author = {Jude A. Rivers},
title = {Performance aspects of high-bandwidth multi-lateral cache organizations},
school = {University of Michigan, {USA}},
year = {1998},
url = {https://hdl.handle.net/2027.42/131086},
timestamp = {Fri, 06 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/us/Rivers98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/TamRSTD98,
author = {Edward S. Tam and
Jude A. Rivers and
Vijayalakshmi Srinivasan and
Gary S. Tyson and
Edward S. Davidson},
title = {Evaluating the performance of active cache management schemes},
booktitle = {International Conference on Computer Design: {VLSI} in Computers and
Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
{USA}},
pages = {368--375},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICCD.1998.727076},
doi = {10.1109/ICCD.1998.727076},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/TamRSTD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/RiversTTDF98,
author = {Jude A. Rivers and
Edward S. Tam and
Gary S. Tyson and
Edward S. Davidson and
Matthew K. Farrens},
editor = {Greg K. Egan and
Richard P. Brent and
Dennis Gannon},
title = {Utilizing Reuse Information in Data Cache Management},
booktitle = {Proceedings of the 12th international conference on Supercomputing,
{ICS} 1998, Melbourne, Australia, July 13-17, 1998},
pages = {449--456},
publisher = {{ACM}},
year = {1998},
url = {https://doi.org/10.1145/277830.277941},
doi = {10.1145/277830.277941},
timestamp = {Tue, 06 Nov 2018 11:07:02 +0100},
biburl = {https://dblp.org/rec/conf/ics/RiversTTDF98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mascots/TamRTD98,
author = {Edward S. Tam and
Jude A. Rivers and
Gary S. Tyson and
Edward S. Davidson},
title = {mlcache: {A} Flexible Multi-Lateral Cache Simulator},
booktitle = {{MASCOTS} 1998, Proceedings of the Sixth International Symposium on
Modeling, Analysis and Simulation of Computer and Telecommunication
Systems, 19-24 July, 1998, Montreal, Canada},
pages = {19--26},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/MASCOT.1998.693670},
doi = {10.1109/MASCOT.1998.693670},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mascots/TamRTD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/RiversTD97,
author = {Jude A. Rivers and
Edward S. Tam and
Edward S. Davidson},
title = {On Effective Data Supply For Multi-Issue Processors},
booktitle = {Proceedings 1997 International Conference on Computer Design: {VLSI}
in Computers {\&} Processors, {ICCD} '97, Austin, Texas, USA,
October 12-15, 1997},
pages = {519--528},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICCD.1997.628917},
doi = {10.1109/ICCD.1997.628917},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/RiversTD97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/RiversTDA97,
author = {Jude A. Rivers and
Gary S. Tyson and
Edward S. Davidson and
Todd M. Austin},
editor = {Mark Smotherman and
Tom Conte},
title = {On High-Bandwidth Data Cache Design for Multi-Issue Processors},
booktitle = {Proceedings of the Thirtieth Annual {IEEE/ACM} International Symposium
on Microarchitecture, {MICRO} 30, Research Triangle Park, North Carolina,
USA, December 1-3, 1997},
pages = {46--56},
publisher = {{ACM/IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/MICRO.1997.645796},
doi = {10.1109/MICRO.1997.645796},
timestamp = {Tue, 31 May 2022 14:39:58 +0200},
biburl = {https://dblp.org/rec/conf/micro/RiversTDA97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pe/RiversD96,
author = {Jude A. Rivers and
Edward S. Davidson},
title = {Performance Issues in Integrating Temporality-Based Caching with Prefetching},
journal = {Perform. Evaluation},
volume = {27/28},
number = {4},
pages = {189--207},
year = {1996},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pe/RiversD96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/RiversD96,
author = {Jude A. Rivers and
Edward S. Davidson},
editor = {Anthony P. Reeves},
title = {Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based
Design},
booktitle = {Proceedings of the 1996 International Conference on Parallel Processing,
{ICCP} 1996, Bloomingdale, IL, USA, August 12-16, 1996. Volume 1:
Architecture},
pages = {154--163},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ICPP.1996.537156},
doi = {10.1109/ICPP.1996.537156},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/RiversD96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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