BibTeX records: Luca Ravezzi

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@article{DBLP:journals/tcasI/Ravezzi21,
  author       = {Luca Ravezzi},
  title        = {Failure in Ring Oscillators With Capacitive Load},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {68},
  number       = {8},
  pages        = {3388--3396},
  year         = {2021},
  url          = {https://doi.org/10.1109/TCSI.2021.3081455},
  doi          = {10.1109/TCSI.2021.3081455},
  timestamp    = {Thu, 29 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcasI/Ravezzi21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/Ravezzi18,
  author       = {Luca Ravezzi},
  title        = {Up-Conversion of Clock Phase Noise in Plesiochronous Data Links},
  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume       = {65-II},
  number       = {12},
  pages        = {1939--1943},
  year         = {2018},
  url          = {https://doi.org/10.1109/TCSII.2018.2810160},
  doi          = {10.1109/TCSII.2018.2810160},
  timestamp    = {Wed, 27 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/Ravezzi18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/RavezziP15,
  author       = {Luca Ravezzi and
                  Hamid Partovi},
  title        = {Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core
                  SoC},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {50},
  number       = {7},
  pages        = {1702--1710},
  year         = {2015},
  url          = {https://doi.org/10.1109/JSSC.2015.2402222},
  doi          = {10.1109/JSSC.2015.2402222},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/RavezziP15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/esscirc/RavezziPWWCAYHHNF14,
  author       = {Luca Ravezzi and
                  Hamid Partovi and
                  Dong Wang and
                  C. Wang and
                  Ronen Cohen and
                  Matt Ashcraft and
                  Alfred Yeung and
                  Qawi Harvard and
                  Russell Homer and
                  John Ngai and
                  Greg Favor},
  title        = {Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoC},
  booktitle    = {{ESSCIRC} 2014 - 40th European Solid State Circuits Conference, Venice
                  Lido, Italy, September 22-26, 2014},
  pages        = {247--250},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ESSCIRC.2014.6942068},
  doi          = {10.1109/ESSCIRC.2014.6942068},
  timestamp    = {Tue, 22 Mar 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/esscirc/RavezziPWWCAYHHNF14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/YeungPHRNHAF14,
  author       = {Alfred Yeung and
                  Hamid Partovi and
                  Qawi Harvard and
                  Luca Ravezzi and
                  John Ngai and
                  Russell Homer and
                  M. Ashcraft and
                  Greg Favor},
  title        = {5.8 {A} 3GHz 64b {ARM} v8 processor in 40nm bulk {CMOS} technology},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {110--111},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757360},
  doi          = {10.1109/ISSCC.2014.6757360},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/YeungPHRNHAF14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/PartoviYRH12,
  author       = {Hamid Partovi and
                  Alfred Yeung and
                  Luca Ravezzi and
                  Mark Horowitz},
  title        = {A 3-stage Pseudo Single-phase Flip-flop family},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
                  13-15, 2012},
  pages        = {172--173},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/VLSIC.2012.6243845},
  doi          = {10.1109/VLSIC.2012.6243845},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/PartoviYRH12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/PartoviGRHSUK09,
  author       = {Hamid Partovi and
                  Karthik Gopalakrishnan and
                  Luca Ravezzi and
                  Russell Homer and
                  Otto Schumacher and
                  Reinhold Unterricker and
                  Werner Kederer},
  title        = {Single-ended transceiver design techniques for 5.33Gb/s graphics applications},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
                  Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
                  2009},
  pages        = {136--137},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/ISSCC.2009.4977345},
  doi          = {10.1109/ISSCC.2009.4977345},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/PartoviGRHSUK09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/PartoviWRLCGBSA06,
  author       = {Hamid Partovi and
                  Wolfgang Walthes and
                  Luca Ravezzi and
                  Paul Lindt and
                  Sivaraman Chokkalingam and
                  Karthik Gopalakrishnan and
                  Andreas Blum and
                  Otto Schumacher and
                  Claudio Andreotti and
                  Michael Bruennert and
                  Bruno Celli{-}Urbani and
                  Dirk Friebe and
                  Ivo Koren and
                  Michael Verbeck and
                  Ulrich Lange},
  title        = {Data Recovery and Retiming for the Fully Buffered {DIMM} 4.8Gb/s Serial
                  Links},
  booktitle    = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
                  2006, Digest of Technical Papers, an Francisco, CA, USA, February
                  6-9, 2006},
  pages        = {1314--1323},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ISSCC.2006.1696179},
  doi          = {10.1109/ISSCC.2006.1696179},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/PartoviWRLCGBSA06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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