BibTeX records: Bruce Petrick

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@article{DBLP:journals/jssc/ShinHPHTSPLJSLS11,
  author       = {Jinuk Luke Shin and
                  Dawei Huang and
                  Bruce Petrick and
                  Changku Hwang and
                  Kenway W. Tam and
                  Alan P. Smith and
                  Ha Pham and
                  Hongping Penny Li and
                  Timothy Johnson and
                  Francis Schumacher and
                  Ana Sonia Leon and
                  Allan Strong},
  title        = {A 40 nm 16-Core 128-Thread {SPARC} SoC Processor},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {46},
  number       = {1},
  pages        = {131--144},
  year         = {2011},
  url          = {https://doi.org/10.1109/JSSC.2010.2080491},
  doi          = {10.1109/JSSC.2010.2080491},
  timestamp    = {Fri, 15 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/ShinHPHTSPLJSLS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ShinTHPPHLSJSGLS10,
  author       = {Jinuk Luke Shin and
                  Kenway W. Tam and
                  Dawei Huang and
                  Bruce Petrick and
                  Ha Pham and
                  Changku Hwang and
                  Hongping Penny Li and
                  Alan P. Smith and
                  Timothy Johnson and
                  Francis Schumacher and
                  David Greenhill and
                  Ana Sonia Leon and
                  Allan Strong},
  title        = {A 40nm 16-core 128-thread {CMT} {SPARC} SoC processor},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
                  Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
                  2010},
  pages        = {98--99},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSCC.2010.5434030},
  doi          = {10.1109/ISSCC.2010.5434030},
  timestamp    = {Fri, 15 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/ShinTHPPHLSJSGLS10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/TakayanagiSPSLP05,
  author       = {Toshinari Takayanagi and
                  Jinuk Luke Shin and
                  Bruce Petrick and
                  Jeffrey Y. Su and
                  Howard Levy and
                  Ha Pham and
                  Jinseung Son and
                  Nathan Moon and
                  Dina Bistry and
                  Umesh Nair and
                  Mandeep Singh and
                  Vikas Mathur and
                  Ana Sonia Leon},
  title        = {A dual-core 64-bit ultraSPARC microprocessor for dense server applications},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {40},
  number       = {1},
  pages        = {7--18},
  year         = {2005},
  url          = {https://doi.org/10.1109/JSSC.2004.838023},
  doi          = {10.1109/JSSC.2004.838023},
  timestamp    = {Wed, 02 Mar 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/TakayanagiSPSLP05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ShinPSL05,
  author       = {Jinuk Luke Shin and
                  Bruce Petrick and
                  Mandeep Singh and
                  Ana Sonia Leon},
  title        = {Design and implementation of an embedded 512-KB level-2 cache subsystem},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {40},
  number       = {9},
  pages        = {1815--1820},
  year         = {2005},
  url          = {https://doi.org/10.1109/JSSC.2005.852165},
  doi          = {10.1109/JSSC.2005.852165},
  timestamp    = {Wed, 02 Mar 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/ShinPSL05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cicc/ShinPLSSMYCGZL04,
  author       = {Jinuk Luke Shin and
                  Bruce Petrick and
                  Howard Levy and
                  Jinseung Son and
                  Mandeep Singh and
                  Vikas Mathur and
                  Jung{-}Cheng Yeh and
                  Heesung Choi and
                  Vishal Gupta and
                  Tom Ziaja and
                  Ana Sonia Leon},
  title        = {Design and implementation of an embedded 512KB level 2 cache subsystem},
  booktitle    = {Proceedings of the {IEEE} 2004 Custom Integrated Circuits Conference,
                  {CICC} 2004, Orlando, FL, USA, October 2004},
  pages        = {349--352},
  publisher    = {{IEEE}},
  year         = {2004},
  url          = {https://doi.org/10.1109/CICC.2004.1358818},
  doi          = {10.1109/CICC.2004.1358818},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/ShinPLSSMYCGZL04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dac/TakayanagiSPSL04,
  author       = {Toshinari Takayanagi and
                  Jinuk Luke Shin and
                  Bruce Petrick and
                  Jeffrey Y. Su and
                  Ana Sonia Leon},
  editor       = {Sharad Malik and
                  Limor Fix and
                  Andrew B. Kahng},
  title        = {A dual-core 64b ultraSPARC microprocessor for dense server applications},
  booktitle    = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
                  San Diego, CA, USA, June 7-11, 2004},
  pages        = {673--677},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/996566.996750},
  doi          = {10.1145/996566.996750},
  timestamp    = {Fri, 25 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/TakayanagiSPSL04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}