BibTeX records: Victor Navarro-Botello

download as .bib file

@article{DBLP:journals/mj/Montiel-NelsonNSB14,
  author       = {Juan A. Montiel{-}Nelson and
                  Victor Navarro{-}Botello and
                  Javier Sosa and
                  Tom{\'{a}}s Bautista},
  title        = {Analysis and optimization of dynamically reconfigurable regenerative
                  comparators for ultra-low power 6-bit TC-ADCs in 90 nm {CMOS} technologies},
  journal      = {Microelectron. J.},
  volume       = {45},
  number       = {10},
  pages        = {1247--1253},
  year         = {2014},
  url          = {https://doi.org/10.1016/j.mejo.2014.02.005},
  doi          = {10.1016/J.MEJO.2014.02.005},
  timestamp    = {Thu, 23 Sep 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/mj/Montiel-NelsonNSB14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/NavarroNMNSG09,
  author       = {H{\'{e}}ctor Navarro and
                  Saeid Nooshabadi and
                  Juan A. Montiel{-}Nelson and
                  Victor Navarro{-}Botello and
                  Javier Sosa and
                  Jos{\'{e}} C. Garc{\'{\i}}a},
  title        = {A geometric approach to register transfer level satisfiability},
  booktitle    = {10th International Symposium on Quality of Electronic Design {(ISQED}
                  2009), 16-18 March 2009, San Jose, CA, {USA}},
  pages        = {272--275},
  publisher    = {{IEEE} Computer Society},
  year         = {2009},
  url          = {https://doi.org/10.1109/ISQED.2009.4810306},
  doi          = {10.1109/ISQED.2009.4810306},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isqed/NavarroNMNSG09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/Navarro-BotelloMN07,
  author       = {Victor Navarro{-}Botello and
                  Juan A. Montiel{-}Nelson and
                  Saeid Nooshabadi},
  title        = {High performance low power {CMOS} dynamic logic for arithmetic circuits},
  journal      = {Microelectron. J.},
  volume       = {38},
  number       = {4-5},
  pages        = {482--488},
  year         = {2007},
  url          = {https://doi.org/10.1016/j.mejo.2007.03.018},
  doi          = {10.1016/J.MEJO.2007.03.018},
  timestamp    = {Sat, 22 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/mj/Navarro-BotelloMN07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/Navarro-BotelloMN07,
  author       = {Victor Navarro{-}Botello and
                  Juan A. Montiel{-}Nelson and
                  Saeid Nooshabadi},
  title        = {Analysis of High-Performance Fast Feedthrough Logic Families in {CMOS}},
  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume       = {54-II},
  number       = {6},
  pages        = {489--493},
  year         = {2007},
  url          = {https://doi.org/10.1109/TCSII.2007.891759},
  doi          = {10.1109/TCSII.2007.891759},
  timestamp    = {Wed, 27 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/Navarro-BotelloMN07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/Navarro-BotelloMN06,
  author       = {Victor Navarro{-}Botello and
                  Juan A. Montiel{-}Nelson and
                  Saeid Nooshabadi},
  title        = {Low Power and High Performance Arithmetic Circuits in Feedthrough
                  {CMOS} Logic Family for Low Power Applications},
  journal      = {J. Low Power Electron.},
  volume       = {2},
  number       = {2},
  pages        = {300--307},
  year         = {2006},
  url          = {https://doi.org/10.1166/jolpe.2006.066},
  doi          = {10.1166/JOLPE.2006.066},
  timestamp    = {Fri, 22 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jolpe/Navarro-BotelloMN06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics