BibTeX records: Byongwook Na

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@inproceedings{DBLP:conf/isscc/ChoiHKHWKCLLJJHYLYLOLLKKPHNCLLSLRSPLB24,
  author       = {IkJoon Choi and
                  Seunghwan Hong and
                  Kihyun Kim and
                  Jeongsik Hwang and
                  Seunghan Woo and
                  Young{-}Sang Kim and
                  Cheongryong Cho and
                  Eun{-}Young Lee and
                  Hun{-}Jae Lee and
                  Min{-}Su Jung and
                  Hee{-}Yun Jung and
                  Ju{-}Seong Hwang and
                  Junsub Yoon and
                  Wonmook Lim and
                  Hyeong{-}Jin Yoo and
                  Won{-}Ki Lee and
                  Jung{-}Kyun Oh and
                  Dong{-}Su Lee and
                  Jong{-}Eun Lee and
                  Jun{-}Hyung Kim and
                  Young{-}Kwan Kim and
                  Su{-}Jin Park and
                  Byung{-}Kyu Ho and
                  Byongwook Na and
                  Hye{-}In Choi and
                  Chung{-}Ki Lee and
                  Soo{-}Jung Lee and
                  Hyunsung Shin and
                  Young{-}Kyu Lee and
                  Jang{-}Woo Ryu and
                  Sangwoong Shin and
                  Sungchul Park and
                  Daihyun Lim and
                  Seung{-}Jun Bae and
                  Young{-}Soo Sohn and
                  Tae{-}Young Oh and
                  SangJoon Hwang},
  title        = {13.2 {A} 32Gb 8.0Gb/s/pin {DDR5} {SDRAM} with a Symmetric-Mosaic Architecture
                  in a 5\({}^{\mbox{th}}\)-Generation 10nm {DRAM} Process},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
                  San Francisco, CA, USA, February 18-22, 2024},
  pages        = {234--236},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ISSCC49657.2024.10454327},
  doi          = {10.1109/ISSCC49657.2024.10454327},
  timestamp    = {Tue, 19 Mar 2024 09:04:31 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/ChoiHKHWKCLLJJHYLYLOLLKKPHNCLLSLRSPLB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/LeeCHPJLJLKKKPL21,
  author       = {Chang{-}Kyo Lee and
                  Hyung{-}Joon Chi and
                  Jin{-}Seok Heo and
                  Junghwan Park and
                  Jin{-}Hun Jang and
                  Dongkeon Lee and
                  Jaehoon Jung and
                  Dong{-}Hun Lee and
                  Dae{-}Hyun Kim and
                  Kihan Kim and
                  Sang{-}Yun Kim and
                  Dukha Park and
                  Youngil Lim and
                  Geuntae Park and
                  Seungjun Lee and
                  Seungki Hong and
                  Dae{-}Hyun Kwon and
                  Isak Hwang and
                  Byongwook Na and
                  Kyungryun Kim and
                  Seouk{-}Kyu Choi and
                  Hye{-}In Choi and
                  Hangi{-}Jung and
                  Wonil Bae and
                  Jeong{-}Don Ihm and
                  Seung{-}Jun Bae and
                  Nam Sung Kim and
                  Jung{-}Bae Lee},
  title        = {An 8.5-Gb/s/Pin 12-Gb {LPDDR5} {SDRAM} With a Hybrid-Bank Architecture,
                  Low Power, and Speed-Boosting Techniques},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {56},
  number       = {1},
  pages        = {212--224},
  year         = {2021},
  url          = {https://doi.org/10.1109/JSSC.2020.3017775},
  doi          = {10.1109/JSSC.2020.3017775},
  timestamp    = {Tue, 05 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/LeeCHPJLJLKKKPL21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/KimKCALCPPJKCYJ21,
  author       = {Yong{-}Hun Kim and
                  Hyung{-}Jin Kim and
                  Jaemin Choi and
                  Min{-}Su Ahn and
                  Dongkeon Lee and
                  Seung{-}Hyun Cho and
                  Dong{-}Yeon Park and
                  Young{-}Jae Park and
                  Min{-}Soo Jang and
                  Yong{-}Jun Kim and
                  Jinyong Choi and
                  Sung{-}Woo Yoon and
                  Jae{-}Woo Jung and
                  Jae{-}Koo Park and
                  Jae{-}Woo Lee and
                  Dae{-}Hyun Kwon and
                  Hyung{-}Seok Cha and
                  Si{-}Hyeong Cho and
                  Seong{-}Hoon Kim and
                  Jihwa You and
                  Kyoung{-}Ho Kim and
                  Dae{-}Hyun Kim and
                  Byung{-}Cheol Kim and
                  Young{-}Kwan Kim and
                  Jun{-}Ho Kim and
                  Seouk{-}Kyu Choi and
                  Chanyoung Kim and
                  Byongwook Na and
                  Hye{-}In Choi and
                  Reum Oh and
                  Jeong{-}Don Ihm and
                  Seung{-}Jun Bae and
                  Nam Sung Kim and
                  Jung{-}Bae Lee},
  title        = {25.2 {A} 16Gb Sub-1V 7.14Gb/s/pin {LPDDR5} {SDRAM} Applying a Mosaic
                  Architecture with a Short-Feedback 1-Tap DFE, an {FSS} Bus with Low-Level
                  Swing and an Adaptively Controlled Body Biasing in a 3\({}^{\mbox{rd}}\)-Generation
                  10nm {DRAM}},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
                  San Francisco, CA, USA, February 13-22, 2021},
  pages        = {346--348},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/ISSCC42613.2021.9366050},
  doi          = {10.1109/ISSCC42613.2021.9366050},
  timestamp    = {Sun, 30 Jul 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/KimKCALCPPJKCYJ21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/HaLPKOSBPLLLMHP20,
  author       = {Kyung{-}Soo Ha and
                  Seungseob Lee and
                  Youn{-}Sik Park and
                  Hyuck{-}Joon Kwon and
                  Tae{-}Young Oh and
                  Young{-}Soo Sohn and
                  Seung{-}Jun Bae and
                  Kwang{-}Il Park and
                  Jung{-}Bae Lee and
                  Chang{-}Kyo Lee and
                  Dongkeon Lee and
                  Daesik Moon and
                  Hyong{-}Ryol Hwang and
                  Dukha Park and
                  Young{-}Hwa Kim and
                  Young Hoon Son and
                  Byongwook Na},
  title        = {A 7.5 Gb/s/pin 8-Gb {LPDDR5} {SDRAM} With Various High-Speed and Low-Power
                  Techniques},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {55},
  number       = {1},
  pages        = {157--166},
  year         = {2020},
  url          = {https://doi.org/10.1109/JSSC.2019.2938396},
  doi          = {10.1109/JSSC.2019.2938396},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/HaLPKOSBPLLLMHP20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ChiLPHJLKPKKPCL20,
  author       = {Hyung{-}Joon Chi and
                  Chang{-}Kyo Lee and
                  Junghwan Park and
                  Jin{-}Seok Heo and
                  Jaehoon Jung and
                  Dongkeon Lee and
                  Dae{-}Hyun Kim and
                  Dukha Park and
                  Kihan Kim and
                  Sang{-}Yun Kim and
                  Jinsol Park and
                  Hyunyoon Cho and
                  Sukhyun Lim and
                  YeonKyu Choi and
                  Youngil Lim and
                  Daesik Moon and
                  Geuntae Park and
                  Jin{-}Hun Jang and
                  Kyungho Lee and
                  Isak Hwang and
                  Cheol Kim and
                  Younghoon Son and
                  Gil{-}Young Kang and
                  Kiwon Park and
                  Seungjun Lee and
                  Su{-}Yeon Doo and
                  Chang{-}Ho Shin and
                  Byongwook Na and
                  Ji{-}Suk Kwon and
                  Kyung Ryun Kim and
                  Hye{-}In Choi and
                  Seouk{-}Kyu Choi and
                  Soobong Chang and
                  Wonil Bae and
                  Hyuck{-}Joon Kwon and
                  Young{-}Soo Sohn and
                  Seung{-}Jun Bae and
                  Kwang{-}Il Park and
                  Jung{-}Bae Lee},
  title        = {22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 {SDRAM} with a Hybrid-Bank Architecture
                  using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a
                  2nd generation 10nm {DRAM} Process},
  booktitle    = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
                  2020, San Francisco, CA, USA, February 16-20, 2020},
  pages        = {382--384},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/ISSCC19947.2020.9062914},
  doi          = {10.1109/ISSCC19947.2020.9062914},
  timestamp    = {Tue, 05 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/ChiLPHJLKPKKPCL20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/HaLLMJHCPSPKLPC19,
  author       = {Kyung{-}Soo Ha and
                  Chang{-}Kyo Lee and
                  Dongkeon Lee and
                  Daesik Moon and
                  Jin{-}Hun Jang and
                  Hyong{-}Ryol Hwang and
                  Hyung{-}Joon Chi and
                  Junghwan Park and
                  Seungjun Shin and
                  Dukha Park and
                  Sang{-}Yun Kim and
                  Sukhyun Lim and
                  Kiwon Park and
                  YeonKyu Choi and
                  Young{-}Hwa Kim and
                  Younghoon Son and
                  Hyunyoon Cho and
                  Byongwook Na and
                  Hyo{-}Joo Ahn and
                  Seungseob Lee and
                  Seouk{-}Kyu Choi and
                  Youn{-}Sik Park and
                  Seok{-}Hun Hyun and
                  Soobong Chang and
                  Hyuck{-}Joon Kwon and
                  Jung{-}Hwan Choi and
                  Tae{-}Young Oh and
                  Young{-}Soo Sohn and
                  Kwang{-}Il Park and
                  Seong{-}Jin Jang},
  title        = {A 7.5Gb/s/pin {LPDDR5} {SDRAM} With {WCK} Clocking and Non-Target
                  {ODT} for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep
                  Mode for Low Power},
  booktitle    = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
                  San Francisco, CA, USA, February 17-21, 2019},
  pages        = {378--380},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/ISSCC.2019.8662509},
  doi          = {10.1109/ISSCC.2019.8662509},
  timestamp    = {Tue, 05 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/HaLLMJHCPSPKLPC19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/KimOLLHHNMKPRPKKKBCJHLCJ12,
  author       = {Jung{-}Sik Kim and
                  Chi Sung Oh and
                  Hocheol Lee and
                  Donghyuk Lee and
                  Hyong{-}Ryol Hwang and
                  Sooman Hwang and
                  Byongwook Na and
                  Joungwook Moon and
                  Jin{-}Guk Kim and
                  Hanna Park and
                  Jang{-}Woo Ryu and
                  Kiwon Park and
                  Sang{-}Kyu Kang and
                  So{-}Young Kim and
                  Hoyoung Kim and
                  Jong{-}Min Bang and
                  Hyunyoon Cho and
                  Minsoo Jang and
                  Cheolmin Han and
                  Jung{-}Bae Lee and
                  Joo{-}Sun Choi and
                  Young{-}Hyun Jun},
  title        = {A 1.2 {V} 12.8 GB/s 2 Gb Mobile Wide-I/O {DRAM} With 4 {\texttimes}
                  128 I/Os Using {TSV} Based Stacking},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {47},
  number       = {1},
  pages        = {107--116},
  year         = {2012},
  url          = {https://doi.org/10.1109/JSSC.2011.2164731},
  doi          = {10.1109/JSSC.2011.2164731},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KimOLLHHNMKPRPKKKBCJHLCJ12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/KimOLLHHNMKPRPKKKBCJHLKCJ11,
  author       = {Jung{-}Sik Kim and
                  Chi Sung Oh and
                  Hocheol Lee and
                  Donghyuk Lee and
                  Hyong{-}Ryol Hwang and
                  Sooman Hwang and
                  Byongwook Na and
                  Joungwook Moon and
                  Jin{-}Guk Kim and
                  Hanna Park and
                  Jang{-}Woo Ryu and
                  Kiwon Park and
                  Sang{-}Kyu Kang and
                  So{-}Young Kim and
                  Hoyoung Kim and
                  Jong{-}Min Bang and
                  Hyunyoon Cho and
                  Minsoo Jang and
                  Cheolmin Han and
                  Jung{-}Bae Lee and
                  Kyehyun Kyung and
                  Joo{-}Sun Choi and
                  Young{-}Hyun Jun},
  title        = {A 1.2V 12.8GB/s 2Gb mobile Wide-I/O {DRAM} with 4{\texttimes}128 I/Os
                  using TSV-based stacking},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
                  Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
                  2011},
  pages        = {496--498},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/ISSCC.2011.5746413},
  doi          = {10.1109/ISSCC.2011.5746413},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/KimOLLHHNMKPRPKKKBCJHLKCJ11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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