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BibTeX records: Malgorzata Marek-Sadowska
@inproceedings{DBLP:conf/ispd/Marek-Sadowska23, author = {Malgorzata Marek{-}Sadowska}, editor = {David G. Chinnery and Iris Hui{-}Ru Jiang}, title = {{ISPD} 2023 Lifetime Achievement Award Bio}, booktitle = {Proceedings of the 2023 International Symposium on Physical Design, {ISPD} 2023, Virtual Event, USA, March 26-29, 2023}, pages = {265}, publisher = {{ACM}}, year = {2023}, url = {https://doi.org/10.1145/3569052.3586950}, doi = {10.1145/3569052.3586950}, timestamp = {Tue, 28 Mar 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/Marek-Sadowska23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/AbbasinasabM19, author = {Ali Abbasinasab and Malgorzata Marek{-}Sadowska}, editor = {Houman Homayoun and Baris Taskin and Tinoosh Mohsenin and Weisheng Zhao}, title = {Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration}, booktitle = {Proceedings of the 2019 on Great Lakes Symposium on VLSI, {GLSVLSI} 2019, Tysons Corner, VA, USA, May 9-11, 2019}, pages = {117--122}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3299874.3317973}, doi = {10.1145/3299874.3317973}, timestamp = {Wed, 10 Mar 2021 14:55:38 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/AbbasinasabM19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/YangM18, author = {Ping{-}Lin Yang and Malgorzata Marek{-}Sadowska}, title = {High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {26}, number = {7}, pages = {1209--1222}, year = {2018}, url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2814627}, doi = {10.1109/TVLSI.2018.2814627}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/YangM18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/AbbasinasabM18, author = {Ali Abbasinasab and Malgorzata Marek{-}Sadowska}, title = {{RAIN:} a tool for reliability assessment of interconnect networks - physics to software}, booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC} 2018, San Francisco, CA, USA, June 24-29, 2018}, pages = {133:1--133:6}, publisher = {{ACM}}, year = {2018}, url = {https://doi.org/10.1145/3195970.3196099}, doi = {10.1145/3195970.3196099}, timestamp = {Wed, 16 Oct 2019 14:14:54 +0200}, biburl = {https://dblp.org/rec/conf/dac/AbbasinasabM18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/GuanM16, author = {Zhong Guan and Malgorzata Marek{-}Sadowska}, title = {Incorporating Process Variations Into {SRAM} Electromigration Reliability Assessment Using Atomic Flux Divergence}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {24}, number = {6}, pages = {2195--2207}, year = {2016}, url = {https://doi.org/10.1109/TVLSI.2015.2501900}, doi = {10.1109/TVLSI.2015.2501900}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/GuanM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/YangM16, author = {Ping{-}Lin Yang and Malgorzata Marek{-}Sadowska}, editor = {Frank Liu}, title = {Making split-fabrication more secure}, booktitle = {Proceedings of the 35th International Conference on Computer-Aided Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016}, pages = {91}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2966986.2967053}, doi = {10.1145/2966986.2967053}, timestamp = {Fri, 23 Jun 2023 22:29:48 +0200}, biburl = {https://dblp.org/rec/conf/iccad/YangM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/GuanM16, author = {Zhong Guan and Malgorzata Marek{-}Sadowska}, editor = {Frank Liu}, title = {An efficient and accurate algorithm for computing {RC} current response with applications to {EM} reliability evaluation}, booktitle = {Proceedings of the 35th International Conference on Computer-Aided Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016}, pages = {112}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2966986.2966999}, doi = {10.1145/2966986.2966999}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/GuanM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/YangM16, author = {Ping{-}Lin Yang and Malgorzata Marek{-}Sadowska}, title = {A fast, fully verifiable, and hardware predictable {ASIC} design methodology}, booktitle = {34th {IEEE} International Conference on Computer Design, {ICCD} 2016, Scottsdale, AZ, USA, October 2-5, 2016}, pages = {364--367}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/ICCD.2016.7753304}, doi = {10.1109/ICCD.2016.7753304}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/YangM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/GuanM16, author = {Zhong Guan and Malgorzata Marek{-}Sadowska}, title = {AFD-based method for signal line {EM} reliability evaluation}, booktitle = {17th International Symposium on Quality Electronic Design, {ISQED} 2016, Santa Clara, CA, USA, March 15-16, 2016}, pages = {443--449}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/ISQED.2016.7479241}, doi = {10.1109/ISQED.2016.7479241}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isqed/GuanM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/LiMN15, author = {Di{-}An Li and Malgorzata Marek{-}Sadowska and Sani R. Nassif}, title = {A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {23}, number = {1}, pages = {118--130}, year = {2015}, url = {https://doi.org/10.1109/TVLSI.2014.2301458}, doi = {10.1109/TVLSI.2014.2301458}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/LiMN15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/QiuMM15, author = {Xiang Qiu and Malgorzata Marek{-}Sadowska and Wojciech P. Maly}, title = {Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {23}, number = {5}, pages = {869--878}, year = {2015}, url = {https://doi.org/10.1109/TVLSI.2014.2325551}, doi = {10.1109/TVLSI.2014.2325551}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/QiuMM15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/LiMN15a, author = {Di{-}An Li and Malgorzata Marek{-}Sadowska and Sani R. Nassif}, title = {{T-VEMA:} {A} Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {23}, number = {10}, pages = {2327--2331}, year = {2015}, url = {https://doi.org/10.1109/TVLSI.2014.2358678}, doi = {10.1109/TVLSI.2014.2358678}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/LiMN15a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/WangM15, author = {Li{-}C. Wang and Malgorzata Marek{-}Sadowska}, editor = {Azadeh Davoodi and Evangeline F. Y. Young}, title = {Machine Learning in Simulation-Based Analysis}, booktitle = {Proceedings of the 2015 Symposium on International Symposium on Physical Design, {ISPD} 2015, Monterey, CA, USA, March 29 - April 1, 2015}, pages = {57--64}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2717764.2717786}, doi = {10.1145/2717764.2717786}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/WangM15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/AbbasinasabM15, author = {Ali Abbasinasab and Malgorzata Marek{-}Sadowska}, editor = {Azadeh Davoodi and Evangeline F. Y. Young}, title = {Blech Effect in Interconnects: Applications and Design Guidelines}, booktitle = {Proceedings of the 2015 Symposium on International Symposium on Physical Design, {ISPD} 2015, Monterey, CA, USA, March 29 - April 1, 2015}, pages = {111--118}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2717764.2717772}, doi = {10.1145/2717764.2717772}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispd/AbbasinasabM15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/cal/NandakumarM14, author = {Vivek S. Nandakumar and Malgorzata Marek{-}Sadowska}, title = {On Optimal Kernel Size for Integrated CPU-GPUs - {A} Case Study}, journal = {{IEEE} Comput. Archit. Lett.}, volume = {13}, number = {2}, pages = {81--84}, year = {2014}, url = {https://doi.org/10.1109/L-CA.2013.27}, doi = {10.1109/L-CA.2013.27}, timestamp = {Sun, 15 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/cal/NandakumarM14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/QiuMM14, author = {Xiang Qiu and Malgorzata Marek{-}Sadowska and Wojciech P. Maly}, title = {Characterizing VeSFET-Based ICs With CMOS-Oriented {EDA} Infrastructure}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {33}, number = {4}, pages = {495--506}, year = {2014}, url = {https://doi.org/10.1109/TCAD.2013.2293539}, doi = {10.1109/TCAD.2013.2293539}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/QiuMM14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/NandakumarM14, author = {Vivek S. Nandakumar and Malgorzata Marek{-}Sadowska}, title = {System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs}, booktitle = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San Francisco, CA, USA, June 1-5, 2014}, pages = {137:1--137:6}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2593069.2593225}, doi = {10.1145/2593069.2593225}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/NandakumarM14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/GuanMN14, author = {Zhong Guan and Malgorzata Marek{-}Sadowska and Sani R. Nassif}, title = {Statistical analysis of process variation induced {SRAM} electromigration degradation}, booktitle = {Fifteenth International Symposium on Quality Electronic Design, {ISQED} 2014, Santa Clara, CA, USA, March 3-5, 2014}, pages = {700--707}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ISQED.2014.6783395}, doi = {10.1109/ISQED.2014.6783395}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isqed/GuanMN14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/LiM14, author = {Di{-}An Li and Malgorzata Marek{-}Sadowska}, title = {Estimating true worst currents for power grid electromigration analysis}, booktitle = {Fifteenth International Symposium on Quality Electronic Design, {ISQED} 2014, Santa Clara, CA, USA, March 3-5, 2014}, pages = {708--714}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ISQED.2014.6783396}, doi = {10.1109/ISQED.2014.6783396}, timestamp = {Thu, 25 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isqed/LiM14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/QiuM13, author = {Xiang Qiu and Malgorzata Marek{-}Sadowska}, title = {Routing Challenges for Designs With Super High Pin Density}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {32}, number = {9}, pages = {1357--1368}, year = {2013}, url = {https://doi.org/10.1109/TCAD.2013.2256462}, doi = {10.1109/TCAD.2013.2256462}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/QiuM13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/QiuMM13, author = {Xiang Qiu and Malgorzata Marek{-}Sadowska and Wojciech Maly}, editor = {Cheng{-}Kok Koh and Cliff C. N. Sze}, title = {Designing VeSFET-based ICs with CMOS-oriented {EDA} infrastructure}, booktitle = {International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013}, pages = {130--136}, publisher = {{ACM}}, year = {2013}, url = {https://doi.org/10.1145/2451916.2451949}, doi = {10.1145/2451916.2451949}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/QiuMM13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/GuanMN13, author = {Zhong Guan and Malgorzata Marek{-}Sadowska and Sani R. Nassif}, title = {{SRAM} bit-line electromigration mechanism and its prevention scheme}, booktitle = {International Symposium on Quality Electronic Design, {ISQED} 2013, Santa Clara, CA, USA, March 4-6, 2013}, pages = {286--293}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/ISQED.2013.6523624}, doi = {10.1109/ISQED.2013.6523624}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isqed/GuanMN13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/esticas/NandakumarM12, author = {Vivek S. Nandakumar and Malgorzata Marek{-}Sadowska}, title = {A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures}, journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.}, volume = {2}, number = {2}, pages = {266--277}, year = {2012}, url = {https://doi.org/10.1109/JETCAS.2012.2193834}, doi = {10.1109/JETCAS.2012.2193834}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/esticas/NandakumarM12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/QiuM12, author = {Xiang Qiu and Malgorzata Marek{-}Sadowska}, editor = {Patrick Groeneveld and Donatella Sciuto and Soha Hassoun}, title = {Can pin access limit the footprint scaling?}, booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San Francisco, CA, USA, June 3-7, 2012}, pages = {1100--1106}, publisher = {{ACM}}, year = {2012}, url = {https://doi.org/10.1145/2228360.2228560}, doi = {10.1145/2228360.2228560}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/QiuM12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/WuuSM12, author = {Jen{-}Yi Wuu and Mark Simmons and Malgorzata Marek{-}Sadowska}, editor = {Keith A. Bowman and Kamesh V. Gadepally and Pallab Chatterjee and Mark M. Budnik and Lalitha Immaneni}, title = {Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs}, booktitle = {Thirteenth International Symposium on Quality Electronic Design, {ISQED} 2012, Santa Clara, CA, USA, March 19-21, 2012}, pages = {193--199}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/ISQED.2012.6187494}, doi = {10.1109/ISQED.2012.6187494}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isqed/WuuSM12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/QiuMM12, author = {Xiang Qiu and Malgorzata Marek{-}Sadowska and Wojciech Maly}, editor = {Keith A. Bowman and Kamesh V. Gadepally and Pallab Chatterjee and Mark M. Budnik and Lalitha Immaneni}, title = {Vertical Slit Field Effect Transistor in ultra-low power applications}, booktitle = {Thirteenth International Symposium on Quality Electronic Design, {ISQED} 2012, Santa Clara, CA, USA, March 19-21, 2012}, pages = {384--390}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/ISQED.2012.6187522}, doi = {10.1109/ISQED.2012.6187522}, timestamp = {Thu, 25 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isqed/QiuMM12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LinMM11, author = {Yi{-}Wei Lin and Malgorzata Marek{-}Sadowska and Wojciech Maly}, title = {On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {30}, number = {2}, pages = {229--241}, year = {2011}, url = {https://doi.org/10.1109/TCAD.2010.2097191}, doi = {10.1109/TCAD.2010.2097191}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LinMM11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/TodriM11, author = {Aida Todri and Malgorzata Marek{-}Sadowska}, title = {Reliability Analysis and Optimization of Power-Gated ICs}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {19}, number = {3}, pages = {457--468}, year = {2011}, url = {https://doi.org/10.1109/TVLSI.2009.2036267}, doi = {10.1109/TVLSI.2009.2036267}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/TodriM11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/SuWCM11, author = {Yu{-}Shih Su and Da{-}Chung Wang and Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska}, title = {Performance Optimization Using Variable-Latency Design Style}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {19}, number = {10}, pages = {1874--1883}, year = {2011}, url = {https://doi.org/10.1109/TVLSI.2010.2058874}, doi = {10.1109/TVLSI.2010.2058874}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/SuWCM11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/TodriM11a, author = {Aida Todri and Malgorzata Marek{-}Sadowska}, title = {Power Delivery for Multicore Systems}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {19}, number = {12}, pages = {2243--2255}, year = {2011}, url = {https://doi.org/10.1109/TVLSI.2010.2080694}, doi = {10.1109/TVLSI.2010.2080694}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/TodriM11a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/WuuPTM11, author = {Jen{-}Yi Wuu and Fedor G. Pikus and Andres J. Torres and Malgorzata Marek{-}Sadowska}, title = {Rapid layout pattern classification}, booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference, {ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011}, pages = {781--786}, publisher = {{IEEE}}, year = {2011}, url = {https://doi.org/10.1109/ASPDAC.2011.5722295}, doi = {10.1109/ASPDAC.2011.5722295}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/WuuPTM11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/NandakumarM11, author = {Vivek S. Nandakumar and Malgorzata Marek{-}Sadowska}, editor = {Leon Stok and Nikil D. Dutt and Soha Hassoun}, title = {Layout effects in fine grain 3D integrated regular microprocessor blocks}, booktitle = {Proceedings of the 48th Design Automation Conference, {DAC} 2011, San Diego, California, USA, June 5-10, 2011}, pages = {639--644}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/2024724.2024871}, doi = {10.1145/2024724.2024871}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/NandakumarM11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/LiM11, author = {Di{-}An Li and Malgorzata Marek{-}Sadowska}, editor = {Joel R. Phillips and Alan J. Hu and Helmut Graeb}, title = {Variation-aware electromigration analysis of power/ground networks}, booktitle = {2011 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2011, San Jose, California, USA, November 7-10, 2011}, pages = {571--576}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/ICCAD.2011.6105387}, doi = {10.1109/ICCAD.2011.6105387}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/LiM11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/NandakumarM11, author = {Vivek S. Nandakumar and Malgorzata Marek{-}Sadowska}, title = {Low power, high throughput network-on-chip fabric for 3D multicore processors}, booktitle = {{IEEE} 29th International Conference on Computer Design, {ICCD} 2011, Amherst, MA, USA, October 9-12, 2011}, pages = {453--454}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/ICCD.2011.6081458}, doi = {10.1109/ICCD.2011.6081458}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/NandakumarM11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/Marek-Sadowska11, author = {Malgorzata Marek{-}Sadowska}, editor = {Yao{-}Wen Chang and Jiang Hu}, title = {On old and new routing problems}, booktitle = {Proceedings of the 2011 International Symposium on Physical Design, {ISPD} 2011, Santa Barbara, California, USA, March 27-30, 2011}, pages = {13--20}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/1960397.1960404}, doi = {10.1145/1960397.1960404}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/Marek-Sadowska11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/WuuPM11, author = {Jen{-}Yi Wuu and Fedor G. Pikus and Malgorzata Marek{-}Sadowska}, title = {Metrics for characterizing machine learning-based hotspot detection methods}, booktitle = {Proceedings of the 12th International Symposium on Quality Electronic Design, {ISQED} 2011, Santa Clara, California, USA, 14-16 March 2011}, pages = {116--121}, publisher = {{IEEE}}, year = {2011}, url = {https://doi.org/10.1109/ISQED.2011.5770713}, doi = {10.1109/ISQED.2011.5770713}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isqed/WuuPM11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LinMM10, author = {Yi{-}Wei Lin and Malgorzata Marek{-}Sadowska and Wojciech Maly}, title = {Layout Generator for Transistor-Level High-Density Regular Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {29}, number = {2}, pages = {197--210}, year = {2010}, url = {https://doi.org/10.1109/TCAD.2009.2035580}, doi = {10.1109/TCAD.2009.2035580}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LinMM10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/LinMM10, author = {Yi{-}Wei Lin and Malgorzata Marek{-}Sadowska and Wojciech Maly}, editor = {Prashant Saxena and Yao{-}Wen Chang}, title = {Performance study of VeSFET-based, high-density regular circuits}, booktitle = {Proceedings of the 2010 International Symposium on Physical Design, {ISPD} 2010, San Francisco, California, USA, March 14-17, 2010}, pages = {161--168}, publisher = {{ACM}}, year = {2010}, url = {https://doi.org/10.1145/1735023.1735062}, doi = {10.1145/1735023.1735062}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/LinMM10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/NandakumarNZM10, author = {Vivek S. Nandakumar and David Newmark and Yaping Zhan and Malgorzata Marek{-}Sadowska}, title = {Statistical static timing analysis flow for transistor level macros in a microprocessor}, booktitle = {11th International Symposium on Quality of Electronic Design {(ISQED} 2010), 22-24 March 2010, San Jose, CA, {USA}}, pages = {163--170}, publisher = {{IEEE}}, year = {2010}, url = {https://doi.org/10.1109/ISQED.2010.5450412}, doi = {10.1109/ISQED.2010.5450412}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isqed/NandakumarNZM10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/LiML10, author = {Di{-}An Li and Malgorzata Marek{-}Sadowska and Bill Lee}, editor = {Sherief Reda and Janet Meiling Wang}, title = {On-chip em-sensitive interconnect structures}, booktitle = {International Workshop on System Level Interconnect Prediction Workshop, {SLIP} 2010, Anaheim, CA, USA, June 13, 2010}, pages = {43--50}, publisher = {{ACM}}, year = {2010}, url = {https://doi.org/10.1145/1811100.1811112}, doi = {10.1145/1811100.1811112}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/slip/LiML10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MehtaMTR09, author = {Vishal J. Mehta and Malgorzata Marek{-}Sadowska and Kun{-}Han Tsai and Janusz Rajski}, title = {Timing-Aware Multiple-Delay-Fault Diagnosis}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {28}, number = {2}, pages = {245--258}, year = {2009}, url = {https://doi.org/10.1109/TCAD.2008.2009164}, doi = {10.1109/TCAD.2008.2009164}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MehtaMTR09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/KuoCCM09, author = {Yu{-}Min Kuo and Ya{-}Ting Chang and Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska}, title = {Spare Cells With Constant Insertion for Engineering Change}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {28}, number = {3}, pages = {456--460}, year = {2009}, url = {https://doi.org/10.1109/TCAD.2009.2013537}, doi = {10.1109/TCAD.2009.2013537}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/KuoCCM09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/islped/TodriM09, author = {Aida Todri and Malgorzata Marek{-}Sadowska}, editor = {J{\"{o}}rg Henkel and Ali Keshavarzi and Naehyuck Chang and Tahir Ghani}, title = {Electromigration study of power-gated grids}, booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009}, pages = {315--318}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1594233.1594311}, doi = {10.1145/1594233.1594311}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/islped/TodriM09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/LinMM09, author = {Yi{-}Wei Lin and Malgorzata Marek{-}Sadowska and Wojciech Maly}, editor = {Gi{-}Joon Nam and Prashant Saxena}, title = {Transistor-level layout of high-density regular circuits}, booktitle = {Proceedings of the 2009 International Symposium on Physical Design, {ISPD} 2009, San Diego, California, USA, March 29 - April 1, 2009}, pages = {83--90}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1514932.1514954}, doi = {10.1145/1514932.1514954}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/LinMM09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/TodriMMM09, author = {Aida Todri and Malgorzata Marek{-}Sadowska and Francois Maire and Christophe Matheron}, title = {A study of decoupling capacitor effectiveness in power and ground grid networks}, booktitle = {10th International Symposium on Quality of Electronic Design {(ISQED} 2009), 16-18 March 2009, San Jose, CA, {USA}}, pages = {653--658}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/ISQED.2009.4810371}, doi = {10.1109/ISQED.2009.4810371}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/TodriMMM09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MehtaMTR08, author = {Vishal J. Mehta and Malgorzata Marek{-}Sadowska and Kun{-}Han Tsai and Janusz Rajski}, title = {Improving the Resolution of Single-Delay-Fault Diagnosis}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {27}, number = {5}, pages = {932--945}, year = {2008}, url = {https://doi.org/10.1109/TCAD.2008.917588}, doi = {10.1109/TCAD.2008.917588}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MehtaMTR08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/JiangM08, author = {Hailin Jiang and Malgorzata Marek{-}Sadowska}, editor = {Limor Fix}, title = {Power gating scheduling for power/ground noise reduction}, booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008, Anaheim, CA, USA, June 8-13, 2008}, pages = {980--985}, publisher = {{ACM}}, year = {2008}, url = {https://doi.org/10.1145/1391469.1391716}, doi = {10.1145/1391469.1391716}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/JiangM08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/TodriMK08, author = {Aida Todri and Malgorzata Marek{-}Sadowska and Joseph N. Kozhaya}, editor = {Sani R. Nassif and Jaijeet S. Roychowdhury}, title = {Power supply noise aware workload assignment for multi-core systems}, booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008, San Jose, CA, USA, November 10-13, 2008}, pages = {330--337}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ICCAD.2008.4681594}, doi = {10.1109/ICCAD.2008.4681594}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/TodriMK08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/TodriM08, author = {Aida Todri and Malgorzata Marek{-}Sadowska}, title = {A study of reliability issues in clock distribution networks}, booktitle = {26th International Conference on Computer Design, {ICCD} 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings}, pages = {101--106}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ICCD.2008.4751847}, doi = {10.1109/ICCD.2008.4751847}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/TodriM08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/WengKCM08, author = {Shih{-}Hung Weng and Yu{-}Min Kuo and Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska}, title = {Timing analysis considering {IR} drop waveforms in power gating designs}, booktitle = {26th International Conference on Computer Design, {ICCD} 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings}, pages = {532--537}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ICCD.2008.4751912}, doi = {10.1109/ICCD.2008.4751912}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/WengKCM08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/LinMMPK08, author = {Yi{-}Wei Lin and Malgorzata Marek{-}Sadowska and Wojciech Maly and Andrzej Pfitzner and Dominik Kasprowicz}, title = {Is there always performance overhead for regular fabric?}, booktitle = {26th International Conference on Computer Design, {ICCD} 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings}, pages = {557--562}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ICCD.2008.4751916}, doi = {10.1109/ICCD.2008.4751916}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/LinMMPK08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/ModiM08, author = {Nilesh Modi and Malgorzata Marek{-}Sadowska}, title = {ECO-Map: Technology remapping for post-mask {ECO} using simulated annealing}, booktitle = {26th International Conference on Computer Design, {ICCD} 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings}, pages = {652--657}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ICCD.2008.4751930}, doi = {10.1109/ICCD.2008.4751930}, timestamp = {Fri, 29 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccd/ModiM08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/MehtaMTR08, author = {Vishal J. Mehta and Malgorzata Marek{-}Sadowska and Kun{-}Han Tsai and Janusz Rajski}, title = {Timing-Aware Multiple-Delay-Fault Diagnosis}, booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED} 2008), 17-19 March 2008, San Jose, CA, {USA}}, pages = {246--253}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ISQED.2008.4479734}, doi = {10.1109/ISQED.2008.4479734}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/MehtaMTR08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YehM07, author = {Chao{-}Yang Yeh and Malgorzata Marek{-}Sadowska}, title = {Timing-Aware Power-Noise Reduction in Placement}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {26}, number = {3}, pages = {527--541}, year = {2007}, url = {https://doi.org/10.1109/TCAD.2006.883917}, doi = {10.1109/TCAD.2006.883917}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YehM07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/MalyLM07, author = {Wojciech Maly and Yi{-}Wei Lin and Malgorzata Marek{-}Sadowska}, title = {OPC-Free and Minimally Irregular {IC} Design Style}, booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007, San Diego, CA, USA, June 4-8, 2007}, pages = {954--957}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1145/1278480.1278715}, doi = {10.1145/1278480.1278715}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/MalyLM07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/SuWCM07, author = {Yu{-}Shih Su and Da{-}Chung Wang and Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska}, title = {An Efficient Mechanism for Performance Optimization of Variable-Latency Designs}, booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007, San Diego, CA, USA, June 4-8, 2007}, pages = {976--981}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1145/1278480.1278721}, doi = {10.1145/1278480.1278721}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/SuWCM07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/KuoCCM07, author = {Yu{-}Min Kuo and Ya{-}Ting Chang and Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska}, editor = {Georges G. E. Gielen}, title = {Engineering change using spare cells with constant insertion}, booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007, San Jose, CA, USA, November 5-8, 2007}, pages = {544--547}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/ICCAD.2007.4397321}, doi = {10.1109/ICCAD.2007.4397321}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/KuoCCM07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/TodriMC07, author = {Aida Todri and Malgorzata Marek{-}Sadowska and Shih{-}Chieh Chang}, editor = {Georges G. E. Gielen}, title = {Analysis and optimization of power-gated ICs with multiple power gating configurations}, booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007, San Jose, CA, USA, November 5-8, 2007}, pages = {783--790}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/ICCAD.2007.4397361}, doi = {10.1109/ICCAD.2007.4397361}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/TodriMC07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/islped/TodriCM07, author = {Aida Todri and Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska}, editor = {Diana Marculescu and Anand Raghunathan and Ali Keshavarzi and Vijaykrishnan Narayanan}, title = {Electromigration and voltage drop aware power grid optimization for power gated ICs}, booktitle = {Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007}, pages = {391--394}, publisher = {{ACM}}, year = {2007}, url = {https://doi.org/10.1145/1283780.1283866}, doi = {10.1145/1283780.1283866}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/islped/TodriCM07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/JiangM07, author = {Hailin Jiang and Malgorzata Marek{-}Sadowska}, title = {Power-Gating Aware Floorplanning}, booktitle = {8th International Symposium on Quality of Electronic Design {(ISQED} 2007), 26-28 March 2007, San Jose, CA, {USA}}, pages = {853--860}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/ISQED.2007.123}, doi = {10.1109/ISQED.2007.123}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/JiangM07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@incollection{DBLP:books/sp/07/HuM07, author = {Bo Hu and Malgorzata Marek{-}Sadowska}, editor = {Gi{-}Joon Nam and Jason Cong}, title = {mFAR: Multilevel Fixed-Points Addition-Based {VLSI} Placement}, booktitle = {Modern Circuit Placement, Best Practices and Results}, pages = {229--245}, publisher = {Springer}, year = {2007}, url = {https://doi.org/10.1007/978-0-387-68739-1\_9}, doi = {10.1007/978-0-387-68739-1\_9}, timestamp = {Wed, 11 Sep 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/books/sp/07/HuM07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangMTR06, author = {Zhiyuan Wang and Malgorzata Marek{-}Sadowska and Kun{-}Han Tsai and Janusz Rajski}, title = {Analysis and methodology for multiple-fault diagnosis}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {25}, number = {3}, pages = {558--575}, year = {2006}, url = {https://doi.org/10.1109/TCAD.2005.854624}, doi = {10.1109/TCAD.2005.854624}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangMTR06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiuM06, author = {Qinghua Liu and Malgorzata Marek{-}Sadowska}, title = {Semi-Individual Wire-Length Prediction With Application to Logic Synthesis}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {25}, number = {4}, pages = {611--624}, year = {2006}, url = {https://doi.org/10.1109/TCAD.2005.859487}, doi = {10.1109/TCAD.2005.859487}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LiuM06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/RanM06, author = {Yajun Ran and Malgorzata Marek{-}Sadowska}, title = {Designing via-configurable logic blocks for regular fabric}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {14}, number = {1}, pages = {1--14}, year = {2006}, url = {https://doi.org/10.1109/TVLSI.2005.863196}, doi = {10.1109/TVLSI.2005.863196}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/RanM06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/RanM06a, author = {Yajun Ran and Malgorzata Marek{-}Sadowska}, title = {Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {14}, number = {9}, pages = {998--1009}, year = {2006}, url = {https://doi.org/10.1109/TVLSI.2006.884051}, doi = {10.1109/TVLSI.2006.884051}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/RanM06a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/JiangM06, author = {Hailin Jiang and Malgorzata Marek{-}Sadowska}, title = {Power/ground supply network optimization for power-gating}, booktitle = {24th International Conference on Computer Design {(ICCD} 2006), 1-4 October 2006, San Jose, CA, {USA}}, pages = {332--337}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/ICCD.2006.4380837}, doi = {10.1109/ICCD.2006.4380837}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/JiangM06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/MehtaMWTR06, author = {Vishal J. Mehta and Malgorzata Marek{-}Sadowska and Zhiyuan Wang and Kun{-}Han Tsai and Janusz Rajski}, title = {Delay Fault Diagnosis for Non-Robust Test}, booktitle = {7th International Symposium on Quality of Electronic Design {(ISQED} 2006), 27-29 March 2006, San Jose, CA, {USA}}, pages = {463--472}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/ISQED.2006.45}, doi = {10.1109/ISQED.2006.45}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/MehtaMWTR06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/TsaiM06, author = {Chung{-}Kuan Tsai and Malgorzata Marek{-}Sadowska}, title = {Analysis of Process Variation's Effect on SRAM's Read Stability}, booktitle = {7th International Symposium on Quality of Electronic Design {(ISQED} 2006), 27-29 March 2006, San Jose, CA, {USA}}, pages = {603--610}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/ISQED.2006.26}, doi = {10.1109/ISQED.2006.26}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/TsaiM06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/MehtaMTR06, author = {Vishal J. Mehta and Malgorzata Marek{-}Sadowska and Kun{-}Han Tsai and Janusz Rajski}, editor = {Scott Davidson and Anne Gattiker}, title = {Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology}, booktitle = {2006 {IEEE} International Test Conference, {ITC} 2006, Santa Clara, CA, USA, October 22-27, 2006}, pages = {1--10}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/TEST.2006.297626}, doi = {10.1109/TEST.2006.297626}, timestamp = {Tue, 12 Dec 2023 09:46:27 +0100}, biburl = {https://dblp.org/rec/conf/itc/MehtaMTR06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangM05, author = {Kai Wang and Malgorzata Marek{-}Sadowska}, title = {On-chip power-supply network optimization using multigrid-based technique}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {24}, number = {3}, pages = {407--417}, year = {2005}, url = {https://doi.org/10.1109/TCAD.2004.842802}, doi = {10.1109/TCAD.2004.842802}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiuM05, author = {Qinghua Liu and Malgorzata Marek{-}Sadowska}, title = {A study of netlist structure and placement efficiency}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {24}, number = {5}, pages = {762--772}, year = {2005}, url = {https://doi.org/10.1109/TCAD.2005.846364}, doi = {10.1109/TCAD.2005.846364}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LiuM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangRJMM05, author = {Kai Wang and Yajun Ran and Hailin Jiang and Malgorzata Marek{-}Sadowska}, title = {General skew constrained clock network sizing based on sequential linear programming}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {24}, number = {5}, pages = {773--782}, year = {2005}, url = {https://doi.org/10.1109/TCAD.2005.846362}, doi = {10.1109/TCAD.2005.846362}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangRJMM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuM05a, author = {Bo Hu and Malgorzata Marek{-}Sadowska}, title = {Multilevel fixed-point-addition-based {VLSI} placement}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {24}, number = {8}, pages = {1188--1203}, year = {2005}, url = {https://doi.org/10.1109/TCAD.2005.850802}, doi = {10.1109/TCAD.2005.850802}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HuM05a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangMTR05, author = {Zhiyuan Wang and Malgorzata Marek{-}Sadowska and Kun{-}Han Tsai and Janusz Rajski}, title = {Delay-fault diagnosis using timing information}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {24}, number = {9}, pages = {1315--1325}, year = {2005}, url = {https://doi.org/10.1109/TCAD.2005.852062}, doi = {10.1109/TCAD.2005.852062}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangMTR05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/RanKTWM05, author = {Yajun Ran and Alex Kondratyev and Kenneth H. Tseng and Yosinori Watanabe and Malgorzata Marek{-}Sadowska}, title = {Eliminating false positives in crosstalk noise analysis}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {24}, number = {9}, pages = {1406--1419}, year = {2005}, url = {https://doi.org/10.1109/TCAD.2005.850829}, doi = {10.1109/TCAD.2005.850829}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/RanKTWM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/YehM05, author = {Chao{-}Yang Yeh and Malgorzata Marek{-}Sadowska}, editor = {Herman Schmit and Steven J. E. Wilton}, title = {Skew-programmable clock design for {FPGA} and skew-aware placement}, booktitle = {Proceedings of the {ACM/SIGDA} 13th International Symposium on Field Programmable Gate Arrays, {FPGA} 2005, Monterey, California, USA, February 20-22, 2005}, pages = {33--40}, publisher = {{ACM}}, year = {2005}, url = {https://doi.org/10.1145/1046192.1046198}, doi = {10.1145/1046192.1046198}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/YehM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/JiangWM05, author = {Hailin Jiang and Kai Wang and Malgorzata Marek{-}Sadowska}, editor = {John C. Lach and Gang Qu and Yehea I. Ismail}, title = {Clock skew bounds estimation under power supply and process variations}, booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005, Chicago, Illinois, USA, April 17-19, 2005}, pages = {332--336}, publisher = {{ACM}}, year = {2005}, url = {https://doi.org/10.1145/1057661.1057741}, doi = {10.1145/1057661.1057741}, timestamp = {Wed, 15 Dec 2021 17:59:57 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/JiangWM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/LiuM05, author = {Qinghua Liu and Malgorzata Marek{-}Sadowska}, editor = {John C. Lach and Gang Qu and Yehea I. Ismail}, title = {A congestion-driven placement framework with local congestion prediction}, booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005, Chicago, Illinois, USA, April 17-19, 2005}, pages = {488--493}, publisher = {{ACM}}, year = {2005}, url = {https://doi.org/10.1145/1057661.1057778}, doi = {10.1145/1057661.1057778}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/LiuM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/RanM05, author = {Yajun Ran and Malgorzata Marek{-}Sadowska}, title = {Via-configurable routing architectures and fast design mappability estimation for regular fabrics}, booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005, San Jose, CA, USA, November 6-10, 2005}, pages = {25--32}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ICCAD.2005.1560035}, doi = {10.1109/ICCAD.2005.1560035}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/RanM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/YehM05, author = {Chao{-}Yang Yeh and Malgorzata Marek{-}Sadowska}, title = {Timing-aware power noise reduction in layout}, booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005, San Jose, CA, USA, November 6-10, 2005}, pages = {627--634}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ICCAD.2005.1560143}, doi = {10.1109/ICCAD.2005.1560143}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/YehM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/LiuM05, author = {Qinghua Liu and Malgorzata Marek{-}Sadowska}, title = {Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement}, booktitle = {23rd International Conference on Computer Design {(ICCD} 2005), 2-5 October 2005, San Jose, CA, {USA}}, pages = {31--37}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ICCD.2005.86}, doi = {10.1109/ICCD.2005.86}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/LiuM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/JiangMN05, author = {Hailin Jiang and Malgorzata Marek{-}Sadowska and Sani R. Nassif}, title = {Benefits and Costs of Power-Gating Technique}, booktitle = {23rd International Conference on Computer Design {(ICCD} 2005), 2-5 October 2005, San Jose, CA, {USA}}, pages = {559--566}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ICCD.2005.34}, doi = {10.1109/ICCD.2005.34}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/JiangMN05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/LiuM05, author = {Qinghua Liu and Malgorzata Marek{-}Sadowska}, editor = {Patrick Groeneveld and Louis Scheffer}, title = {Wire length prediction-based technology mapping and fanout optimization}, booktitle = {Proceedings of the 2005 International Symposium on Physical Design, {ISPD} 2005, San Francisco, California, USA, April 3-6, 2005}, pages = {145--151}, publisher = {{ACM}}, year = {2005}, url = {https://doi.org/10.1145/1055137.1055167}, doi = {10.1145/1055137.1055167}, timestamp = {Tue, 06 Nov 2018 11:07:46 +0100}, biburl = {https://dblp.org/rec/conf/ispd/LiuM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/HuZM05, author = {Bo Hu and Yue Zeng and Malgorzata Marek{-}Sadowska}, editor = {Patrick Groeneveld and Louis Scheffer}, title = {mFAR: fixed-points-addition-based {VLSI} placement algorithm}, booktitle = {Proceedings of the 2005 International Symposium on Physical Design, {ISPD} 2005, San Francisco, California, USA, April 3-6, 2005}, pages = {239--241}, publisher = {{ACM}}, year = {2005}, url = {https://doi.org/10.1145/1055137.1055189}, doi = {10.1145/1055137.1055189}, timestamp = {Wed, 11 Sep 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/HuZM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/TsaiM05, author = {Chung{-}Kuan Tsai and Malgorzata Marek{-}Sadowska}, title = {An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis}, booktitle = {6th International Symposium on Quality of Electronic Design {(ISQED} 2005), 21-23 March 2005, San Jose, CA, {USA}}, pages = {654--661}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ISQED.2005.16}, doi = {10.1109/ISQED.2005.16}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/TsaiM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/MacchiaruloSM04, author = {Luca Macchiarulo and Shih{-}Min Shu and Malgorzata Marek{-}Sadowska}, title = {Pipelining Sequential Circuits with Wave Steering}, journal = {{IEEE} Trans. Computers}, volume = {53}, number = {9}, pages = {1205--1210}, year = {2004}, url = {https://doi.org/10.1109/TC.2004.65}, doi = {10.1109/TC.2004.65}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/MacchiaruloSM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChangHHWMCC04, author = {Chih{-}Wei Jim Chang and Ming{-}Fu Hsiao and Bo Hu and Kai Wang and Malgorzata Marek{-}Sadowska and Chung{-}Kuan Cheng and Sao{-}Jie Chen}, title = {Fast postplacement optimization using functional symmetries}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {23}, number = {1}, pages = {102--118}, year = {2004}, url = {https://doi.org/10.1109/TCAD.2003.819904}, doi = {10.1109/TCAD.2003.819904}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChangHHWMCC04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuM04, author = {Bo Hu and Malgorzata Marek{-}Sadowska}, title = {Fine granularity clustering-based placement}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {23}, number = {4}, pages = {527--536}, year = {2004}, url = {https://doi.org/10.1109/TCAD.2004.825868}, doi = {10.1109/TCAD.2004.825868}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HuM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/LiuHM04, author = {Qinghua Liu and Bo Hu and Malgorzata Marek{-}Sadowska}, title = {Individual wire-length prediction with application to timing-driven placement}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {12}, number = {10}, pages = {1004--1014}, year = {2004}, url = {https://doi.org/10.1109/TVLSI.2004.834234}, doi = {10.1109/TVLSI.2004.834234}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/LiuHM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/YehM04, author = {Chao{-}Yang Yeh and Malgorzata Marek{-}Sadowska}, title = {Sequential delay budgeting with interconnect prediction}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {12}, number = {10}, pages = {1028--1037}, year = {2004}, url = {https://doi.org/10.1109/TVLSI.2004.827563}, doi = {10.1109/TVLSI.2004.827563}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/YehM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cicc/RanM04, author = {Yajun Ran and Malgorzata Marek{-}Sadowska}, title = {Designing a via-configurable regular fabric}, booktitle = {Proceedings of the {IEEE} 2004 Custom Integrated Circuits Conference, {CICC} 2004, Orlando, FL, USA, October 2004}, pages = {423--426}, publisher = {{IEEE}}, year = {2004}, url = {https://doi.org/10.1109/CICC.2004.1358840}, doi = {10.1109/CICC.2004.1358840}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/cicc/RanM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/WangM04, author = {Kai Wang and Malgorzata Marek{-}Sadowska}, editor = {Sharad Malik and Limor Fix and Andrew B. Kahng}, title = {Buffer sizing for clock power minimization subject to general skew constraints}, booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004, San Diego, CA, USA, June 7-11, 2004}, pages = {159--164}, publisher = {{ACM}}, year = {2004}, url = {https://doi.org/10.1145/996566.996614}, doi = {10.1145/996566.996614}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/WangM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/RanM04, author = {Yajun Ran and Malgorzata Marek{-}Sadowska}, editor = {Sharad Malik and Limor Fix and Andrew B. Kahng}, title = {On designing via-configurable cell blocks for regular fabrics}, booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004, San Diego, CA, USA, June 7-11, 2004}, pages = {198--203}, publisher = {{ACM}}, year = {2004}, url = {https://doi.org/10.1145/996566.996624}, doi = {10.1145/996566.996624}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/RanM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LiuM04, author = {Qinghua Liu and Malgorzata Marek{-}Sadowska}, editor = {Sharad Malik and Limor Fix and Andrew B. Kahng}, title = {Pre-layout wire length and congestion estimation}, booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004, San Diego, CA, USA, June 7-11, 2004}, pages = {582--587}, publisher = {{ACM}}, year = {2004}, url = {https://doi.org/10.1145/996566.996726}, doi = {10.1145/996566.996726}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/LiuM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/RanKWM04, author = {Yajun Ran and Alex Kondratyev and Yosinori Watanabe and Malgorzata Marek{-}Sadowska}, title = {Eliminating False Positives in Crosstalk Noise Analysis}, booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2004), 16-20 February 2004, Paris, France}, pages = {1192--1197}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/DATE.2004.1269054}, doi = {10.1109/DATE.2004.1269054}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/RanKWM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/HuM04a, author = {Bo Hu and Malgorzata Marek{-}Sadowska}, title = {Multilevel expansion-based {VLSI} placement with blockages}, booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004, San Jose, CA, USA, November 7-11, 2004}, pages = {558--564}, publisher = {{IEEE} Computer Society / {ACM}}, year = {2004}, url = {https://doi.org/10.1109/ICCAD.2004.1382640}, doi = {10.1109/ICCAD.2004.1382640}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/HuM04a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/RanM04, author = {Yajun Ran and Malgorzata Marek{-}Sadowska}, title = {An integrated design flow for a via-configurable gate array}, booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004, San Jose, CA, USA, November 7-11, 2004}, pages = {582--589}, publisher = {{IEEE} Computer Society / {ACM}}, year = {2004}, url = {https://doi.org/10.1109/ICCAD.2004.1382644}, doi = {10.1109/ICCAD.2004.1382644}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/RanM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/WangMTR04, author = {Zhiyuan Wang and Malgorzata Marek{-}Sadowska and Kun{-}Han Tsai and Janusz Rajski}, title = {Diagnosis of Hold Time Defects}, booktitle = {22nd {IEEE} International Conference on Computer Design: {VLSI} in Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings}, pages = {192--199}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/ICCD.2004.1347921}, doi = {10.1109/ICCD.2004.1347921}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/WangMTR04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/WangM04, author = {Kai Wang and Malgorzata Marek{-}Sadowska}, title = {Potential Slack Budgeting with Clock Skew Optimization}, booktitle = {22nd {IEEE} International Conference on Computer Design: {VLSI} in Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings}, pages = {265--271}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/ICCD.2004.1347932}, doi = {10.1109/ICCD.2004.1347932}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/WangM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/RanM04, author = {Yajun Ran and Malgorzata Marek{-}Sadowska}, title = {The Magic of a Via-Configurable Regular Fabric}, booktitle = {22nd {IEEE} International Conference on Computer Design: {VLSI} in Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings}, pages = {338--343}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/ICCD.2004.1347943}, doi = {10.1109/ICCD.2004.1347943}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/RanM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/WangM04, author = {Kai Wang and Malgorzata Marek{-}Sadowska}, editor = {Charles J. Alpert and Patrick Groeneveld}, title = {Clock network sizing via sequential linear programming with time-domain analysis}, booktitle = {Proceedings of the 2004 International Symposium on Physical Design, {ISPD} 2004, Phoenix, Arizona, USA, April 18-21, 2004}, pages = {182--189}, publisher = {{ACM}}, year = {2004}, url = {https://doi.org/10.1145/981066.981105}, doi = {10.1145/981066.981105}, timestamp = {Tue, 06 Nov 2018 11:07:46 +0100}, biburl = {https://dblp.org/rec/conf/ispd/WangM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/LiuM04, author = {Qinghua Liu and Malgorzata Marek{-}Sadowska}, editor = {Charles J. Alpert and Patrick Groeneveld}, title = {A study of netlist structure and placement efficiency}, booktitle = {Proceedings of the 2004 International Symposium on Physical Design, {ISPD} 2004, Phoenix, Arizona, USA, April 18-21, 2004}, pages = {198--203}, publisher = {{ACM}}, year = {2004}, url = {https://doi.org/10.1145/981066.981109}, doi = {10.1145/981066.981109}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispd/LiuM04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/WangMTR04, author = {Zhiyuan Wang and Malgorzata Marek{-}Sadowska and Kun{-}Han Tsai and Janusz Rajski}, title = {Delay Fault Diagnosis Using Timing Information}, booktitle = {5th International Symposium on Quality of Electronic Design {(ISQED} 2004), 22-24 March 2004, San Jose, CA, {USA}}, pages = {485--490}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/ISQED.2004.1283720}, doi = {10.1109/ISQED.2004.1283720}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/WangMTR04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/dt/MukherjeeM03, author = {Arindam Mukherjee and Malgorzata Marek{-}Sadowska}, title = {Clock and Power Gating with Timing Closure}, journal = {{IEEE} Des. Test Comput.}, volume = {20}, number = {3}, pages = {32--39}, year = {2003}, url = {https://doi.org/10.1109/MDT.2003.1198683}, doi = {10.1109/MDT.2003.1198683}, timestamp = {Mon, 05 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/dt/MukherjeeM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChangHM03, author = {Chih{-}Wei Jim Chang and Ming{-}Fu Hsiao and Malgorzata Marek{-}Sadowska}, title = {A new reasoning scheme for efficient redundancy addition and removal}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {22}, number = {7}, pages = {945--951}, year = {2003}, url = {https://doi.org/10.1109/TCAD.2003.814239}, doi = {10.1109/TCAD.2003.814239}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChangHM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/MukherjeeM03, author = {Arindam Mukherjee and Malgorzata Marek{-}Sadowska}, title = {Wave steering to integrate logic and physical syntheses}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {11}, number = {1}, pages = {105--120}, year = {2003}, url = {https://doi.org/10.1109/TVLSI.2003.811100}, doi = {10.1109/TVLSI.2003.811100}, timestamp = {Mon, 05 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/MukherjeeM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/SinghMMM03, author = {Amit Singh and Arindam Mukherjee and Luca Macchiarulo and Malgorzata Marek{-}Sadowska}, title = {{PITIA:} an {FPGA} for throughput-intensive applications}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {11}, number = {3}, pages = {354--363}, year = {2003}, url = {https://doi.org/10.1109/TVLSI.2003.810780}, doi = {10.1109/TVLSI.2003.810780}, timestamp = {Mon, 05 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/SinghMMM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChenMB03, author = {Lauren Hui Chen and Malgorzata Marek{-}Sadowska and Forrest Brewer}, title = {Buffer delay change in the presence of power and ground noise}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {11}, number = {3}, pages = {461--473}, year = {2003}, url = {https://doi.org/10.1109/TVLSI.2003.812310}, doi = {10.1109/TVLSI.2003.812310}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ChenMB03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/WangM03, author = {Kai Wang and Malgorzata Marek{-}Sadowska}, title = {On-chip power supply network optimization using multigrid-based technique}, booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003, Anaheim, CA, USA, June 2-6, 2003}, pages = {113--118}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/775832.775864}, doi = {10.1145/775832.775864}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/WangM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/YehM03, author = {Chao{-}Yang Yeh and Malgorzata Marek{-}Sadowska}, title = {Delay budgeting in sequential circuit with application on {FPGA} placement}, booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003, Anaheim, CA, USA, June 2-6, 2003}, pages = {202--207}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/775832.775886}, doi = {10.1145/775832.775886}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/YehM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/HuWKM03, author = {Bo Hu and Yosinori Watanabe and Alex Kondratyev and Malgorzata Marek{-}Sadowska}, title = {Gain-based technology mapping for discrete-size cell libraries}, booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003, Anaheim, CA, USA, June 2-6, 2003}, pages = {574--579}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/775832.775979}, doi = {10.1145/775832.775979}, timestamp = {Wed, 11 Sep 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/HuWKM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/HuM03, author = {Bo Hu and Malgorzata Marek{-}Sadowska}, title = {Wire length prediction based clustering and its application in placement}, booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003, Anaheim, CA, USA, June 2-6, 2003}, pages = {800--805}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/775832.776035}, doi = {10.1145/775832.776035}, timestamp = {Wed, 11 Sep 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/HuM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ChaiKRTWM03, author = {Donald Chai and Alex Kondratyev and Yajun Ran and Kenneth H. Tseng and Yosinori Watanabe and Malgorzata Marek{-}Sadowska}, title = {Temporofunctional crosstalk noise analysis}, booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003, Anaheim, CA, USA, June 2-6, 2003}, pages = {860--863}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/775832.776048}, doi = {10.1145/775832.776048}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/ChaiKRTWM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/RanM03, author = {Yajun Ran and Malgorzata Marek{-}Sadowska}, title = {Crosstalk noise in FPGAs}, booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003, Anaheim, CA, USA, June 2-6, 2003}, pages = {944--949}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/775832.776069}, doi = {10.1145/775832.776069}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/RanM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/WangM03, author = {Kai Wang and Malgorzata Marek{-}Sadowska}, title = {Power/Ground Mesh Area Optimization Using Multigrid-Based Technique}, booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2003), 3-7 March 2003, Munich, Germany}, pages = {10850--10855}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10115}, doi = {10.1109/DATE.2003.10115}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/WangM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/YehM03, author = {Chao{-}Yang Yeh and Malgorzata Marek{-}Sadowska}, title = {Minimum-Area Sequential Budgeting for {FPGA}}, booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003, San Jose, CA, USA, November 9-13, 2003}, pages = {813--817}, publisher = {{IEEE} Computer Society / {ACM}}, year = {2003}, url = {https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257902}, doi = {10.1109/ICCAD.2003.1257902}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/YehM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/WangMTR03, author = {Zhiyuan Wang and Malgorzata Marek{-}Sadowska and Kun{-}Han Tsai and Janusz Rajski}, title = {Multiple Fault Diagnosis Using n-Detection Tests}, booktitle = {21st International Conference on Computer Design {(ICCD} 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings}, pages = {198}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.org/10.1109/ICCD.2003.1240895}, doi = {10.1109/ICCD.2003.1240895}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/WangMTR03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/HsiaoMC03, author = {Ming{-}Fu Hsiao and Malgorzata Marek{-}Sadowska and Sao{-}Jie Chen}, title = {A crosstalk aware two-pin net router}, booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems, {ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003}, pages = {485--488}, publisher = {{IEEE}}, year = {2003}, url = {https://doi.org/10.1109/ISCAS.2003.1206325}, doi = {10.1109/ISCAS.2003.1206325}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/HsiaoMC03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/HsiaoMC03a, author = {Ming{-}Fu Hsiao and Malgorzata Marek{-}Sadowska and Sao{-}Jie Chen}, title = {Minimizing coupling jitter by buffer resizing for coupled clock networks}, booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems, {ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003}, pages = {509--512}, publisher = {{IEEE}}, year = {2003}, url = {https://doi.org/10.1109/ISCAS.2003.1206333}, doi = {10.1109/ISCAS.2003.1206333}, timestamp = {Fri, 26 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iscas/HsiaoMC03a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/HuM03, author = {Bo Hu and Malgorzata Marek{-}Sadowska}, editor = {Massoud Pedram and Charles J. Alpert}, title = {Fine granularity clustering for large scale placement problems}, booktitle = {Proceedings of the 2003 International Symposium on Physical Design, {ISPD} 2003, Monterey, CA, USA, April 6-9, 2003}, pages = {67--74}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/640000.640017}, doi = {10.1145/640000.640017}, timestamp = {Wed, 11 Sep 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/HuM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/HuJLM03, author = {Bo Hu and Hailin Jiang and Qinghua Liu and Malgorzata Marek{-}Sadowska}, editor = {Massoud Pedram and Charles J. Alpert}, title = {Synthesis and placement flow for gain-based programmable regular fabrics}, booktitle = {Proceedings of the 2003 International Symposium on Physical Design, {ISPD} 2003, Monterey, CA, USA, April 6-9, 2003}, pages = {197--203}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/640000.640041}, doi = {10.1145/640000.640041}, timestamp = {Wed, 11 Sep 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/HuJLM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/TsaiM03, author = {Chung{-}Kuan Tsai and Malgorzata Marek{-}Sadowska}, title = {Modeling Crosstalk Induced Delay}, booktitle = {4th International Symposium on Quality of Electronic Design {(ISQED} 2003), 24-26 March 2003, San Jose, CA, {USA}}, pages = {189--194}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.org/10.1109/ISQED.2003.1194730}, doi = {10.1109/ISQED.2003.1194730}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/TsaiM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/HsiaoMC03, author = {Ming{-}Fu Hsiao and Malgorzata Marek{-}Sadowska and Sao{-}Jie Chen}, title = {Minimizing Inter-Clock Coupling Jitter}, booktitle = {4th International Symposium on Quality of Electronic Design {(ISQED} 2003), 24-26 March 2003, San Jose, CA, {USA}}, pages = {333--338}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.org/10.1109/ISQED.2003.1194754}, doi = {10.1109/ISQED.2003.1194754}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/HsiaoMC03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/WangTMR03, author = {Zhiyuan Wang and Kun{-}Han Tsai and Malgorzata Marek{-}Sadowska and Janusz Rajski}, title = {An Efficient and Effective Methodology on the Multiple Fault Diagnosis}, booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, {USA}}, pages = {329--338}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.org/10.1109/TEST.2003.1270855}, doi = {10.1109/TEST.2003.1270855}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/WangTMR03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/YehM03, author = {Chao{-}Yang Yeh and Malgorzata Marek{-}Sadowska}, editor = {Dennis Sylvester and Dirk Stroobandt and Louis Scheffer and Payman Zarkesh{-}Ha}, title = {Sequential delay budgeting with interconnect prediction}, booktitle = {The 5th International Workshop on System-Level Interconnect Prediction {(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings}, pages = {23--30}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/639929.639935}, doi = {10.1145/639929.639935}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/slip/YehM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/LiuHM03, author = {Qinghua Liu and Bo Hu and Malgorzata Marek{-}Sadowska}, editor = {Dennis Sylvester and Dirk Stroobandt and Louis Scheffer and Payman Zarkesh{-}Ha}, title = {Wire length prediction in constraint driven placement}, booktitle = {The 5th International Workshop on System-Level Interconnect Prediction {(SLIP} 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings}, pages = {99--105}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/639929.639950}, doi = {10.1145/639929.639950}, timestamp = {Wed, 11 Sep 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/slip/LiuHM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/SinghPM02, author = {Amit Singh and Ganapathy Parthasarathy and Malgorzata Marek{-}Sadowska}, title = {Efficient circuit clustering for area and power reduction in FPGAs}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {7}, number = {4}, pages = {643--663}, year = {2002}, url = {https://doi.org/10.1145/605440.605448}, doi = {10.1145/605440.605448}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/todaes/SinghPM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/vlsi/XiaoM02, author = {Tong Xiao and Malgorzata Marek{-}Sadowska}, title = {Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis}, journal = {{VLSI} Design}, volume = {15}, number = {3}, pages = {647--666}, year = {2002}, url = {https://doi.org/10.1080/1065514021000012264}, doi = {10.1080/1065514021000012264}, timestamp = {Mon, 08 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/vlsi/XiaoM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ChenMB02a, author = {Lauren Hui Chen and Malgorzata Marek{-}Sadowska and Forrest Brewer}, title = {Coping with buffer delay change due to power and ground noise}, booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002, New Orleans, LA, USA, June 10-14, 2002}, pages = {860--865}, publisher = {{ACM}}, year = {2002}, url = {https://doi.org/10.1145/513918.514131}, doi = {10.1145/513918.514131}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/ChenMB02a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/MukherjeeWCM02, author = {Arindam Mukherjee and Kai Wang and Lauren Hui Chen and Malgorzata Marek{-}Sadowska}, title = {Sizing Power/Ground Meshes for Clocking and Computing Circuit Components}, booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2002), 4-8 March 2002, Paris, France}, pages = {176--183}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/DATE.2002.998267}, doi = {10.1109/DATE.2002.998267}, timestamp = {Mon, 05 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/date/MukherjeeWCM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ChenM02, author = {Lauren Hui Chen and Malgorzata Marek{-}Sadowska}, title = {Closed-Form Crosstalk Noise Metrics for Physical Design Applications}, booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2002), 4-8 March 2002, Paris, France}, pages = {812--819}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/DATE.2002.998392}, doi = {10.1109/DATE.2002.998392}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/ChenM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/SinghM02, author = {Amit Singh and Malgorzata Marek{-}Sadowska}, editor = {Martine D. F. Schlag and Steve Trimberger}, title = {Efficient circuit clustering for area and power reduction in FPGAs}, booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable Gate Arrays, {FPGA} 2002, Monterey, CA, USA, February 24-26, 2002}, pages = {59--66}, publisher = {{ACM}}, year = {2002}, url = {https://doi.org/10.1145/503048.503058}, doi = {10.1145/503048.503058}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/SinghM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/HuM02, author = {Bo Hu and Malgorzata Marek{-}Sadowska}, editor = {Lawrence T. Pileggi and Andreas Kuehlmann}, title = {Congestion minimization during placement without estimation}, booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002}, pages = {739--745}, publisher = {{ACM} / {IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1145/774572.774681}, doi = {10.1145/774572.774681}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/HuM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChangM02, author = {Chih{-}Wei Jim Chang and Malgorzata Marek{-}Sadowska}, editor = {Lawrence T. Pileggi and Andreas Kuehlmann}, title = {ATPG-based logic synthesis: an overview}, booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002}, pages = {786--789}, publisher = {{ACM} / {IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1145/774572.774688}, doi = {10.1145/774572.774688}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/ChangM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/ChenM02, author = {Lauren Hui Chen and Malgorzata Marek{-}Sadowska}, editor = {Sachin S. Sapatnekar and Massoud Pedram}, title = {Incremental delay change due to crosstalk noise}, booktitle = {Proceedings of 2002 International Symposium on Physical Design, {ISPD} 2002, Del Mar, CA, USA, April 7-10, 2002}, pages = {120--125}, publisher = {{ACM}}, year = {2002}, url = {https://doi.org/10.1145/505388.505419}, doi = {10.1145/505388.505419}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/ChenM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/HuM02, author = {Bo Hu and Malgorzata Marek{-}Sadowska}, editor = {Sachin S. Sapatnekar and Massoud Pedram}, title = {{FAR:} fixed-points addition {\&} relaxation based placement}, booktitle = {Proceedings of 2002 International Symposium on Physical Design, {ISPD} 2002, Del Mar, CA, USA, April 7-10, 2002}, pages = {161--166}, publisher = {{ACM}}, year = {2002}, url = {https://doi.org/10.1145/505388.505426}, doi = {10.1145/505388.505426}, timestamp = {Wed, 11 Sep 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/HuM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/ChenM02, author = {Lauren Hui Chen and Malgorzata Marek{-}Sadowska}, title = {Efficient Closed-Form Crosstalk Delay Metrics}, booktitle = {3rd International Symposium on Quality of Electronic Design, {ISQED} 2002, San Jose, CA, USA, March 18-21, 2002}, pages = {431--436}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/ISQED.2002.996784}, doi = {10.1109/ISQED.2002.996784}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/ChenM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/SinghM02, author = {Amit Singh and Malgorzata Marek{-}Sadowska}, title = {{FPGA} interconnect planning}, booktitle = {The Fourth {IEEE/ACM} International Workshop on System-Level Interconnect Prediction {(SLIP} 2002), April 6-7, 2002, San Diego, California, USA, Proceedings}, pages = {23--30}, publisher = {{ACM}}, year = {2002}, url = {https://doi.org/10.1145/505348.505353}, doi = {10.1145/505348.505353}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/slip/SinghM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChenM01, author = {Lauren Hui Chen and Malgorzata Marek{-}Sadowska}, title = {Aggressor alignment for worst-case crosstalk noise}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {20}, number = {5}, pages = {612--621}, year = {2001}, url = {https://doi.org/10.1109/43.920689}, doi = {10.1109/43.920689}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChenM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ChangWM01, author = {Chih{-}Wei Jim Chang and Kai Wang and Malgorzata Marek{-}Sadowska}, title = {Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques}, booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001, Las Vegas, NV, USA, June 18-22, 2001}, pages = {97--102}, publisher = {{ACM}}, year = {2001}, url = {https://doi.org/10.1145/378239.378352}, doi = {10.1145/378239.378352}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/ChangWM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/SinghMM01, author = {Amit Singh and Arindam Mukherjee and Malgorzata Marek{-}Sadowska}, title = {Latency and Latch Count Minimization in Wave Steered Circuits}, booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001, Las Vegas, NV, USA, June 18-22, 2001}, pages = {383--388}, publisher = {{ACM}}, year = {2001}, url = {https://doi.org/10.1145/378239.378529}, doi = {10.1145/378239.378529}, timestamp = {Mon, 05 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/SinghMM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/XiaoM01, author = {Tong Xiao and Malgorzata Marek{-}Sadowska}, title = {Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification}, booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001, Las Vegas, NV, USA, June 18-22, 2001}, pages = {653--656}, publisher = {{ACM}}, year = {2001}, url = {https://doi.org/10.1145/378239.379041}, doi = {10.1145/378239.379041}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/XiaoM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ChangHM01, author = {Chih{-}Wei Jim Chang and Bo Hu and Malgorzata Marek{-}Sadowska}, editor = {Wolfgang Nebel and Ahmed Jerraya}, title = {In-place delay constrained power optimization using functional symmetries}, booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe, {DATE} 2001, Munich, Germany, March 12-16, 2001}, pages = {377--382}, publisher = {{IEEE} Computer Society}, year = {2001}, url = {https://doi.org/10.1109/DATE.2001.915052}, doi = {10.1109/DATE.2001.915052}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/ChangHM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dsd/FunabikiSMM01, author = {Nobuo Funabiki and Amit Singh and Arindam Mukherjee and Malgorzata Marek{-}Sadowska}, title = {A Global Routing Technique for Wave-Steering Design Methodology}, booktitle = {Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland}, pages = {430--437}, publisher = {{IEEE} Computer Society}, year = {2001}, url = {https://doi.org/10.1109/DSD.2001.952358}, doi = {10.1109/DSD.2001.952358}, timestamp = {Mon, 05 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dsd/FunabikiSMM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/SinghMM01, author = {Amit Singh and Arindam Mukherjee and Malgorzata Marek{-}Sadowska}, editor = {Scott Hauck and Martine D. F. Schlag and Russell Tessier}, title = {Interconnect pipelining in a throughput-intensive {FPGA} architecture}, booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001}, pages = {153--160}, publisher = {{ACM}}, year = {2001}, url = {https://doi.org/10.1145/360276.360323}, doi = {10.1145/360276.360323}, timestamp = {Mon, 05 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpga/SinghMM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/ChangM01, author = {Chih{-}Wei Jim Chang and Malgorzata Marek{-}Sadowska}, editor = {Kaushik Roy and Sung{-}Mo Kang and Cheng{-}Kok Koh}, title = {Who are the alternative wires in your neighborhood? (alternative wires identification without search)}, booktitle = {Proceedings of the 11th {ACM} Great Lakes Symposium on {VLSI} 2001, West Lafayette, Indiana, USA, 2001}, pages = {103--108}, publisher = {{ACM}}, year = {2001}, url = {https://doi.org/10.1145/368122.368880}, doi = {10.1145/368122.368880}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/ChangM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/SinghPM01, author = {Amit Singh and Ganapathy Parthasarathy and Malgorzata Marek{-}Sadowska}, editor = {Rolf Ernst}, title = {Interconnect Resource-Aware Placement for Hierarchical FPGAs}, booktitle = {Proceedings of the 2001 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2001, San Jose, CA, USA, November 4-8, 2001}, pages = {132--136}, publisher = {{IEEE} Computer Society}, year = {2001}, url = {https://doi.org/10.1109/ICCAD.2001.968609}, doi = {10.1109/ICCAD.2001.968609}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/SinghPM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChangM01, author = {Chih{-}Wei Jim Chang and Malgorzata Marek{-}Sadowska}, editor = {Rolf Ernst}, title = {Single-Pass Redundancy Addition and Removal}, booktitle = {Proceedings of the 2001 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2001, San Jose, CA, USA, November 4-8, 2001}, pages = {606--609}, publisher = {{IEEE} Computer Society}, year = {2001}, url = {https://doi.org/10.1109/ICCAD.2001.968723}, doi = {10.1109/ICCAD.2001.968723}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/ChangM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/XiaoM01, author = {Tong Xiao and Malgorzata Marek{-}Sadowska}, title = {Gate Sizing to Eliminate Crosstalk Induced Timing Violation}, booktitle = {19th International Conference on Computer Design {(ICCD} 2001), {VLSI} in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings}, pages = {186--191}, publisher = {{IEEE} Computer Society}, year = {2001}, url = {https://doi.org/10.1109/ICCD.2001.955023}, doi = {10.1109/ICCD.2001.955023}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/XiaoM01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/ParthasarathyMMS01, author = {Ganapathy Parthasarathy and Malgorzata Marek{-}Sadowska and Arindam Mukherjee and Amit Singh}, title = {Interconnect complexity-aware {FPGA} placement using Rent's rule}, booktitle = {The Third {IEEE/ACM} International Workshop on System-Level Interconnect Prediction {(SLIP} 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings}, pages = {115--121}, publisher = {{ACM}}, year = {2001}, url = {https://doi.org/10.1145/368640.368806}, doi = {10.1145/368640.368806}, timestamp = {Mon, 05 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/slip/ParthasarathyMMS01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/WuFMW00, author = {Yu{-}Liang Wu and Hongbing Fan and Malgorzata Marek{-}Sadowska and C. K. Wong}, title = {{OBDD} Minimization Based on Two-Level Representation of Boolean Functions}, journal = {{IEEE} Trans. Computers}, volume = {49}, number = {12}, pages = {1371--1379}, year = {2000}, url = {https://doi.org/10.1109/12.895868}, doi = {10.1109/12.895868}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/WuFMW00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/TsaiRM00, author = {Kun{-}Han Tsai and Janusz Rajski and Malgorzata Marek{-}Sadowska}, title = {Star test: the theory and its applications}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {19}, number = {9}, pages = {1052--1064}, year = {2000}, url = {https://doi.org/10.1109/43.863645}, doi = {10.1109/43.863645}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/TsaiRM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ChangCSM00, author = {Chih{-}Wei Jim Chang and Chung{-}Kuan Cheng and Peter Suaris and Malgorzata Marek{-}Sadowska}, editor = {Giovanni De Micheli}, title = {Fast post-placement rewiring using easily detectable functional symmetries}, booktitle = {Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000}, pages = {286--289}, publisher = {{ACM}}, year = {2000}, url = {https://doi.org/10.1145/337292.337420}, doi = {10.1145/337292.337420}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/ChangCSM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/MacchiaruloM00, author = {Luca Macchiarulo and Malgorzata Marek{-}Sadowska}, editor = {Giovanni De Micheli}, title = {Wave-steering one-hot encoded FSMs}, booktitle = {Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000}, pages = {357--360}, publisher = {{ACM}}, year = {2000}, url = {https://doi.org/10.1145/337292.337440}, doi = {10.1145/337292.337440}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/MacchiaruloM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/MacchiaruloSM00, author = {Luca Macchiarulo and Shih{-}Ming Shu and Malgorzata Marek{-}Sadowska}, editor = {Ivo Bolsens}, title = {Wave Steered FSMs}, booktitle = {2000 Design, Automation and Test in Europe {(DATE} 2000), 27-30 March 2000, Paris, France}, pages = {270--276}, publisher = {{IEEE} Computer Society / {ACM}}, year = {2000}, url = {https://doi.org/10.1109/DATE.2000.840283}, doi = {10.1109/DATE.2000.840283}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/MacchiaruloSM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/SinghMMM00, author = {Amit Singh and Luca Macchiarulo and Arindam Mukherjee and Malgorzata Marek{-}Sadowska}, editor = {Steve Trimberger and Scott Hauck}, title = {A novel high throughput reconfigurable {FPGA} architecture}, booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable Gate Arrays, {FPGA} 2000, Monterey, CA, USA, February 10-11, 2000}, pages = {22--29}, publisher = {{ACM}}, year = {2000}, url = {https://doi.org/10.1145/329166.329174}, doi = {10.1145/329166.329174}, timestamp = {Mon, 05 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpga/SinghMMM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/XiaoM00, author = {Tong Xiao and Malgorzata Marek{-}Sadowska}, title = {Worst Delay Estimation in Crosstalk Aware Static Timing Analysis}, booktitle = {Proceedings of the {IEEE} International Conference On Computer Design: {VLSI} In Computers {\&} Processors, {ICCD} '00, Austin, Texas, USA, September 17-20, 2000}, pages = {115--120}, publisher = {{IEEE} Computer Society}, year = {2000}, url = {https://doi.org/10.1109/ICCD.2000.878276}, doi = {10.1109/ICCD.2000.878276}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/XiaoM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/ChenM00, author = {Lauren Hui Chen and Malgorzata Marek{-}Sadowska}, editor = {Manfred Wiesel and Dwight D. Hill}, title = {Aggressor alignment for worst-case coupling noise}, booktitle = {Proceedings of the 2000 International Symposium on Physical Design, {ISPD} 2000, San Diego, CA, USA, April 9-12, 2000}, pages = {48--54}, publisher = {{ACM}}, year = {2000}, url = {https://doi.org/10.1145/332357.332373}, doi = {10.1145/332357.332373}, timestamp = {Thu, 26 Aug 2021 17:11:38 +0200}, biburl = {https://dblp.org/rec/conf/ispd/ChenM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isqed/XiaoM00, author = {Tong Xiao and Malgorzata Marek{-}Sadowska}, title = {Efficient Delay Calculation in Presence of Crosstalk}, booktitle = {1st International Symposium on Quality of Electronic Design {(ISQED} 2000), 20-22 March 2000, San Jose, CA, {USA}}, pages = {491--498}, publisher = {{IEEE} Computer Society}, year = {2000}, url = {https://doi.org/10.1109/ISQED.2000.838932}, doi = {10.1109/ISQED.2000.838932}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isqed/XiaoM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/ChangM99, author = {Douglas Chang and Malgorzata Marek{-}Sadowska}, title = {Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs}, journal = {{IEEE} Trans. Computers}, volume = {48}, number = {6}, pages = {565--578}, year = {1999}, url = {https://doi.org/10.1109/12.773794}, doi = {10.1109/12.773794}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/ChangM99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/ChangGM99, author = {Shih{-}Chieh Chang and Lukas P. P. P. van Ginneken and Malgorzata Marek{-}Sadowska}, title = {Circuit Optimization by Rewiring}, journal = {{IEEE} Trans. Computers}, volume = {48}, number = {9}, pages = {962--970}, year = {1999}, url = {https://doi.org/10.1109/12.795224}, doi = {10.1109/12.795224}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/ChangGM99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LinCM99, author = {Chih{-}Chang Lin and Kuang{-}Chien Chen and Malgorzata Marek{-}Sadowska}, title = {Logic synthesis for engineering change}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {18}, number = {3}, pages = {282--292}, year = {1999}, url = {https://doi.org/10.1109/43.748158}, doi = {10.1109/43.748158}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LinCM99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/VittalCMWY99, author = {Ashok Vittal and Lauren Hui Chen and Malgorzata Marek{-}Sadowska and Kai{-}Ping Wang and Sherry Yang}, title = {Crosstalk in {VLSI} interconnections}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {18}, number = {12}, pages = {1817--1824}, year = {1999}, url = {https://doi.org/10.1109/43.811330}, doi = {10.1109/43.811330}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/VittalCMWY99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/XiaoM99, author = {Tong Xiao and Malgorzata Marek{-}Sadowska}, title = {Crosstalk Reduction by Transistor Sizing}, booktitle = {Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999}, pages = {137--140}, publisher = {{IEEE} Computer Society}, year = {1999}, url = {https://doi.org/10.1109/ASPDAC.1999.759786}, doi = {10.1109/ASPDAC.1999.759786}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/aspdac/XiaoM99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cicc/MukherjeeML99, author = {Arindam Mukherjee and Malgorzata Marek{-}Sadowska and Stephen I. Long}, title = {Wave pipelining YADDs-a feasibility study}, booktitle = {Proceedings of the {IEEE} 1999 Custom Integrated Circuits Conference, {CICC} 1999, San Diego, CA, USA, May 16-19, 1999}, pages = {559--562}, publisher = {{IEEE}}, year = {1999}, url = {https://doi.org/10.1109/CICC.1999.777343}, doi = {10.1109/CICC.1999.777343}, timestamp = {Fri, 07 Jul 2023 11:00:51 +0200}, biburl = {https://dblp.org/rec/conf/cicc/MukherjeeML99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/MukherjeeSML99, author = {Arindam Mukherjee and Ranganathan Sudhakar and Malgorzata Marek{-}Sadowska and Stephen I. Long}, editor = {Mary Jane Irwin}, title = {Wave Steering in YADDs: {A} Novel Non-Iterative Synthesis and Layout Technique}, booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999}, pages = {466--471}, publisher = {{ACM} Press}, year = {1999}, url = {https://doi.org/10.1145/309847.309981}, doi = {10.1145/309847.309981}, timestamp = {Mon, 05 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/MukherjeeSML99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/SinghM99, author = {Amit Singh and Malgorzata Marek{-}Sadowska}, editor = {D. F. Wong}, title = {Circuit clustering using graph coloring}, booktitle = {Proceedings of the 1999 International Symposium on Physical Design, {ISPD} 1999, Monterey, CA, USA, April 12-14, 1999}, pages = {164--169}, publisher = {{ACM}}, year = {1999}, url = {https://doi.org/10.1145/299996.300055}, doi = {10.1145/299996.300055}, timestamp = {Sun, 02 Oct 2022 16:10:02 +0200}, biburl = {https://dblp.org/rec/conf/ispd/SinghM99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/TsaiTRM99, author = {Kuo{-}Hui Tsai and Tompson and Janusz Rajski and Malgorzata Marek{-}Sadowska}, title = {{STAR-ATPG:} a high speed test pattern generator for large scan designs}, booktitle = {Proceedings {IEEE} International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999}, pages = {1021--1030}, publisher = {{IEEE} Computer Society}, year = {1999}, url = {https://doi.org/10.1109/TEST.1999.805835}, doi = {10.1109/TEST.1999.805835}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/TsaiTRM99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/VittalCMWY99, author = {Ashok Vittal and Lauren Hui Chen and Malgorzata Marek{-}Sadowska and Kai{-}Ping Wang and Sherry Yang}, title = {Modeling Crosstalk in Resistive {VLSI} Interconnections}, booktitle = {12th International Conference on {VLSI} Design {(VLSI} Design 1999), 10-13 January 1999, Goa, India}, pages = {470--475}, publisher = {{IEEE} Computer Society}, year = {1999}, url = {https://doi.org/10.1109/ICVD.1999.745200}, doi = {10.1109/ICVD.1999.745200}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/VittalCMWY99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChengCWM98, author = {David Ihsin Cheng and Kwang{-}Ting Cheng and Deborah C. Wang and Malgorzata Marek{-}Sadowska}, title = {A hybrid methodology for switching activities estimation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {17}, number = {4}, pages = {357--366}, year = {1998}, url = {https://doi.org/10.1109/43.703825}, doi = {10.1109/43.703825}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/ChengCWM98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LinMCL98, author = {Chih{-}Chang Lin and Malgorzata Marek{-}Sadowska and Kwang{-}Ting Cheng and Mike Tien{-}Chien Lee}, title = {Test-point insertion: scan paths through functional logic}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {17}, number = {9}, pages = {838--851}, year = {1998}, url = {https://doi.org/10.1109/43.720319}, doi = {10.1109/43.720319}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/LinMCL98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LinMLC98, author = {Chih{-}Chang Lin and Malgorzata Marek{-}Sadowska and Mike Tien{-}Chien Lee and Kuang{-}Chien Chen}, title = {Cost-free scan: a low-overhead scan path design}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {17}, number = {9}, pages = {852--861}, year = {1998}, url = {https://doi.org/10.1109/43.720320}, doi = {10.1109/43.720320}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LinMLC98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/vlsi/VittalM98, author = {Ashok Vittal and Malgorzata Marek{-}Sadowska}, title = {Power Distribution Synthesis for {VLSI}}, journal = {{VLSI} Design}, volume = {7}, number = {1}, pages = {59--72}, year = {1998}, url = {https://doi.org/10.1155/1998/76525}, doi = {10.1155/1998/76525}, timestamp = {Mon, 08 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/vlsi/VittalM98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ChangCML98, author = {Douglas Chang and Kwang{-}Ting Cheng and Malgorzata Marek{-}Sadowska and Mike Tien{-}Chien Lee}, editor = {Patrick M. Dewilde and Franz J. Rammig and Gerry Musgrave}, title = {Functional Scan Chain Testing}, booktitle = {1998 Design, Automation and Test in Europe {(DATE} '98), February 23-26, 1998, Le Palais des Congr{\`{e}}s de Paris, Paris, France}, pages = {278--283}, publisher = {{IEEE} Computer Society}, year = {1998}, url = {https://doi.org/10.1109/DATE.1998.655868}, doi = {10.1109/DATE.1998.655868}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/ChangCML98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/ChangM98, author = {Douglas Chang and Malgorzata Marek{-}Sadowska}, editor = {Jason Cong and Sinan Kaptanoglu}, title = {Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs}, booktitle = {Proceedings of the 1998 {ACM/SIGDA} Sixth International Symposium on Field Programmable Gate Arrays, {FPGA} 1998, Monterey, CA, USA, February 22-24, 1998}, pages = {161--167}, publisher = {{ACM}}, year = {1998}, url = {https://doi.org/10.1145/275107.275136}, doi = {10.1145/275107.275136}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/ChangM98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/TsaiM97, author = {Chien{-}Chung Tsai and Malgorzata Marek{-}Sadowska}, title = {Boolean Functions Classification via Fixed Polarity Reed-Muller Forms}, journal = {{IEEE} Trans. Computers}, volume = {46}, number = {2}, pages = {173--186}, year = {1997}, url = {https://doi.org/10.1109/12.565592}, doi = {10.1109/12.565592}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/TsaiM97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/VittalM97, author = {Ashok Vittal and Malgorzata Marek{-}Sadowska}, title = {Crosstalk reduction for {VLSI}}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {16}, number = {3}, pages = {290--298}, year = {1997}, url = {https://doi.org/10.1109/43.594834}, doi = {10.1109/43.594834}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/VittalM97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WuM97, author = {Yu{-}Liang Wu and Malgorzata Marek{-}Sadowska}, title = {Routing for array-type FPGA's}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {16}, number = {5}, pages = {506--518}, year = {1997}, url = {https://doi.org/10.1109/43.631213}, doi = {10.1109/43.631213}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WuM97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LinM97, author = {Chih{-}Chang Lin and Malgorzata Marek{-}Sadowska}, title = {On designing universal logic blocks and their application to {FPGA} design}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {16}, number = {5}, pages = {519--527}, year = {1997}, url = {https://doi.org/10.1109/43.631214}, doi = {10.1109/43.631214}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LinM97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChangCWM97, author = {Shih{-}Chieh Chang and Kwang{-}Ting Cheng and Nam Sung Woo and Malgorzata Marek{-}Sadowska}, title = {Postlayout logic restructuring using alternative wires}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {16}, number = {6}, pages = {587--596}, year = {1997}, url = {https://doi.org/10.1109/43.640617}, doi = {10.1109/43.640617}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/ChangCWM97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/VittalM97a, author = {Ashok Vittal and Malgorzata Marek{-}Sadowska}, title = {Low-power buffered clock tree design}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {16}, number = {9}, pages = {965--975}, year = {1997}, url = {https://doi.org/10.1109/43.658565}, doi = {10.1109/43.658565}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/VittalM97a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/WuCMT97, author = {Yu{-}Liang Wu and Douglas Chang and Malgorzata Marek{-}Sadowska and Shuji Tsukiyama}, title = {Not necessarily more switches more routability [sic.]}, booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997}, pages = {579--584}, publisher = {{IEEE}}, year = {1997}, url = {https://doi.org/10.1109/ASPDAC.1997.600339}, doi = {10.1109/ASPDAC.1997.600339}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/WuCMT97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ChangLMAC97, author = {Douglas Chang and Mike Tien{-}Chien Lee and Malgorzata Marek{-}Sadowska and Takashi Aikyo and Kwang{-}Ting Cheng}, editor = {Ellen J. Yoffa and Giovanni De Micheli and Jan M. Rabaey}, title = {A Test Synthesis Approach to Reducing {BALLAST} {DFT} Overhead}, booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997}, pages = {466--471}, publisher = {{ACM} Press}, year = {1997}, url = {https://doi.org/10.1145/266021.266202}, doi = {10.1145/266021.266202}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/ChangLMAC97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/TsaiHRM97, author = {Kun{-}Han Tsai and Sybille Hellebrand and Janusz Rajski and Malgorzata Marek{-}Sadowska}, editor = {Ellen J. Yoffa and Giovanni De Micheli and Jan M. Rabaey}, title = {{STARBIST:} Scan Autocorrelated Random Pattern Generation}, booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997}, pages = {472--477}, publisher = {{ACM} Press}, year = {1997}, url = {https://doi.org/10.1145/266021.266203}, doi = {10.1145/266021.266203}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/TsaiHRM97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/JiangKCM97, author = {Yi{-}Min Jiang and Angela Krstic and Kwang{-}Ting Cheng and Malgorzata Marek{-}Sadowska}, editor = {Ellen J. Yoffa and Giovanni De Micheli and Jan M. Rabaey}, title = {Post-Layout Logic Restructuring for Performance Optimization}, booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997}, pages = {662--665}, publisher = {{ACM} Press}, year = {1997}, url = {https://doi.org/10.1145/266021.266313}, doi = {10.1145/266021.266313}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/JiangKCM97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/ChangM97, author = {Douglas Chang and Malgorzata Marek{-}Sadowska}, editor = {Carl Ebeling}, title = {Buffer Minimization and Time-Multiplexed {I/O} on Dynamically Reconfigurable FPGAs}, booktitle = {Proceedings of the 1997 {ACM/SIGDA} Fifth International Symposium on Field Programmable Gate Arrays, {FPGA} 1997, Monterey, CA, USA, February 9-11, 1997}, pages = {142--148}, publisher = {{ACM}}, year = {1997}, url = {https://doi.org/10.1145/258305.258331}, doi = {10.1145/258305.258331}, timestamp = {Tue, 06 Nov 2018 16:58:23 +0100}, biburl = {https://dblp.org/rec/conf/fpga/ChangM97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ismvl/PerkowskiMJLGNMWZ97, author = {Marek A. Perkowski and Malgorzata Marek{-}Sadowska and Lech J{\'{o}}zwiak and Tadeusz Luba and Stan Grygiel and Miroslawa Nowicka and Rahul Malvi and Zhi Wang and Jin S. Zhang}, title = {Decomposition of Multiple-Valued Relations}, booktitle = {27th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL} 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings}, pages = {13--18}, publisher = {{IEEE} Computer Society}, year = {1997}, url = {https://doi.org/10.1109/ISMVL.1997.601367}, doi = {10.1109/ISMVL.1997.601367}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ismvl/PerkowskiMJLGNMWZ97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ismvl/GrygielPMLJ97, author = {Stan Grygiel and Marek A. Perkowski and Malgorzata Marek{-}Sadowska and Tadeusz Luba and Lech J{\'{o}}zwiak}, title = {Cube Diagram Bundles: {A} New Representation of Strongly Unspecified Multiple-Valued Functions and Relations}, booktitle = {27th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL} 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings}, pages = {287--292}, publisher = {{IEEE} Computer Society}, year = {1997}, url = {https://doi.org/10.1109/ISMVL.1997.601416}, doi = {10.1109/ISMVL.1997.601416}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ismvl/GrygielPMLJ97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/TsaiMR97, author = {Kun{-}Han Tsai and Malgorzata Marek{-}Sadowska and Janusz Rajski}, title = {Scan-Encoded Test Pattern Generation for {BIST}}, booktitle = {Proceedings {IEEE} International Test Conference 1997, Washington, DC, USA, November 3-5, 1997}, pages = {548--556}, publisher = {{IEEE} Computer Society}, year = {1997}, url = {https://doi.org/10.1109/TEST.1997.639663}, doi = {10.1109/TEST.1997.639663}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/TsaiMR97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/TsaiM96, author = {Chien{-}Chung Tsai and Malgorzata Marek{-}Sadowska}, title = {Generalized Reed-Muller Forms as a Tool to Detect Symmetries}, journal = {{IEEE} Trans. Computers}, volume = {45}, number = {1}, pages = {33--40}, year = {1996}, url = {https://doi.org/10.1109/12.481484}, doi = {10.1109/12.481484}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/TsaiM96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WuTM96, author = {Yu{-}Liang Wu and Shuji Tsukiyama and Malgorzata Marek{-}Sadowska}, title = {Graph based analysis of 2-D {FPGA} routing}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {15}, number = {1}, pages = {33--44}, year = {1996}, url = {https://doi.org/10.1109/43.486270}, doi = {10.1109/43.486270}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WuTM96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChangMH96, author = {Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska and TingTing Hwang}, title = {Technology mapping for {TLU} FPGAs based on decomposition of binary decision diagrams}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {15}, number = {10}, pages = {1226--1236}, year = {1996}, url = {https://doi.org/10.1109/43.541442}, doi = {10.1109/43.541442}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChangMH96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChangMC96, author = {Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska and Kwang{-}Ting Cheng}, title = {Perturb and simplify: multilevel Boolean network optimizer}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {15}, number = {12}, pages = {1494--1504}, year = {1996}, url = {https://doi.org/10.1109/43.552082}, doi = {10.1109/43.552082}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/ChangMC96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/TsaiM96, author = {Chien{-}Chung Tsai and Malgorzata Marek{-}Sadowska}, editor = {Thomas Pennino and Ellen J. Yoffa}, title = {Multilevel Logic Synthesis for Arithmetic Functions}, booktitle = {Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996}, pages = {242--247}, publisher = {{ACM} Press}, year = {1996}, url = {https://doi.org/10.1145/240518.240563}, doi = {10.1145/240518.240563}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/TsaiM96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LinMCL96, author = {Chih{-}Chang Lin and Malgorzata Marek{-}Sadowska and Kwang{-}Ting Cheng and Mike Tien{-}Chien Lee}, editor = {Thomas Pennino and Ellen J. Yoffa}, title = {Test Point Insertion: Scan Paths through Combinational Logic}, booktitle = {Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996}, pages = {268--273}, publisher = {{ACM} Press}, year = {1996}, url = {https://doi.org/10.1145/240518.240568}, doi = {10.1145/240518.240568}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/LinMCL96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ChengCWM96, author = {David Ihsin Cheng and Kwang{-}Ting Cheng and Deborah C. Wang and Malgorzata Marek{-}Sadowska}, editor = {Thomas Pennino and Ellen J. Yoffa}, title = {A New Hybrid Methodology for Power Estimation}, booktitle = {Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996}, pages = {439--444}, publisher = {{ACM} Press}, year = {1996}, url = {https://doi.org/10.1145/240518.240602}, doi = {10.1145/240518.240602}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/ChengCWM96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/LinMCL96, author = {Chih{-}Chang Lin and Malgorzata Marek{-}Sadowska and Kuang{-}Chien Chen and Mike Tien{-}Chien Lee}, title = {Sequential Permissible Functions and their Application to Circuit Optimization}, booktitle = {1996 European Design and Test Conference, ED{\&}TC 1996, Paris, France, March 11-14, 1996}, pages = {334--339}, publisher = {{IEEE} Computer Society}, year = {1996}, url = {https://doi.org/10.1109/EDTC.1996.494322}, doi = {10.1109/EDTC.1996.494322}, timestamp = {Fri, 20 May 2022 15:52:30 +0200}, biburl = {https://dblp.org/rec/conf/date/LinMCL96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ChangM96, author = {Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska}, title = {Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares}, booktitle = {1996 European Design and Test Conference, ED{\&}TC 1996, Paris, France, March 11-14, 1996}, pages = {402--406}, publisher = {{IEEE} Computer Society}, year = {1996}, url = {https://doi.org/10.1109/EDTC.1996.494332}, doi = {10.1109/EDTC.1996.494332}, timestamp = {Fri, 20 May 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/date/ChangM96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/TsaiM96, author = {Chien{-}Chung Tsai and Malgorzata Marek{-}Sadowska}, title = {Logic Synthesis for Testability}, booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23, 1996, Ames, IA, {USA}}, pages = {118--121}, publisher = {{IEEE} Computer Society}, year = {1996}, url = {https://doi.org/10.1109/GLSV.1996.497605}, doi = {10.1109/GLSV.1996.497605}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/TsaiM96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChangGM96, author = {Shih{-}Chieh Chang and Lukas P. P. P. van Ginneken and Malgorzata Marek{-}Sadowska}, editor = {Rob A. Rutenbar and Ralph H. J. M. Otten}, title = {Fast Boolean optimization by rewiring}, booktitle = {Proceedings of the 1996 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 1996, San Jose, CA, USA, November 10-14, 1996}, pages = {262--269}, publisher = {{IEEE} Computer Society / {ACM}}, year = {1996}, url = {https://doi.org/10.1109/ICCAD.1996.569641}, doi = {10.1109/ICCAD.1996.569641}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/ChangGM96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/VittalHBM96, author = {Ashok Vittal and Hein Ha and Forrest Brewer and Malgorzata Marek{-}Sadowska}, editor = {Rob A. Rutenbar and Ralph H. J. M. Otten}, title = {Clock skew optimization for ground bounce control}, booktitle = {Proceedings of the 1996 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 1996, San Jose, CA, USA, November 10-14, 1996}, pages = {395--399}, publisher = {{IEEE} Computer Society / {ACM}}, year = {1996}, url = {https://doi.org/10.1109/ICCAD.1996.569827}, doi = {10.1109/ICCAD.1996.569827}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/VittalHBM96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Marek-SadowskaS95, author = {Malgorzata Marek{-}Sadowska and Majid Sarrafzadeh}, title = {The crossing distribution problem {[IC} layout]}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {14}, number = {4}, pages = {423--433}, year = {1995}, url = {https://doi.org/10.1109/43.372368}, doi = {10.1109/43.372368}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Marek-SadowskaS95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/LinCMC95, author = {Chih{-}Chang Lin and David Ihsin Cheng and Malgorzata Marek{-}Sadowska and Kuang{-}Chien Chen}, editor = {Isao Shirakawa}, title = {Logic rectification and synthesis for engineering change}, booktitle = {Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995}, publisher = {{ACM}}, year = {1995}, url = {https://doi.org/10.1145/224818.224913}, doi = {10.1145/224818.224913}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/LinCMC95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/WuM95, author = {Yu{-}Liang Wu and Malgorzata Marek{-}Sadowska}, editor = {Isao Shirakawa}, title = {Routing on regular segmented 2-D FPGAs}, booktitle = {Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995}, publisher = {{ACM}}, year = {1995}, url = {https://doi.org/10.1145/224818.224917}, doi = {10.1145/224818.224917}, timestamp = {Fri, 26 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/WuM95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/VittalM95, author = {Ashok Vittal and Malgorzata Marek{-}Sadowska}, editor = {Bryan Preas}, title = {Power Optimal Buffered Clock Tree Design}, booktitle = {Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995}, pages = {497--502}, publisher = {{ACM} Press}, year = {1995}, url = {https://doi.org/10.1145/217474.217577}, doi = {10.1145/217474.217577}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/VittalM95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/VittalM95a, author = {Ashok Vittal and Malgorzata Marek{-}Sadowska}, editor = {Bryan Preas}, title = {Power Distribution Topology Design}, booktitle = {Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995}, pages = {503--507}, publisher = {{ACM} Press}, year = {1995}, url = {https://doi.org/10.1145/217474.217578}, doi = {10.1145/217474.217578}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/VittalM95a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/WuM95, author = {Yu{-}Liang Wu and Malgorzata Marek{-}Sadowska}, editor = {Bryan Preas}, title = {Orthogonal Greedy Coupling - {A} New Optimization Approach to 2-D {FPGA} Routing}, booktitle = {Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995}, pages = {568--573}, publisher = {{ACM} Press}, year = {1995}, url = {https://doi.org/10.1145/217474.217591}, doi = {10.1145/217474.217591}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/WuM95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LinCCMC95, author = {Chih{-}Chang Lin and Kuang{-}Chien Chen and Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska and Kwang{-}Ting Cheng}, editor = {Bryan Preas}, title = {Logic Synthesis for Engineering Change}, booktitle = {Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995}, pages = {647--652}, publisher = {{ACM} Press}, year = {1995}, url = {https://doi.org/10.1145/217474.217604}, doi = {10.1145/217474.217604}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/LinCCMC95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ChangMC95, author = {Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska and Kwang{-}Ting Cheng}, editor = {Bryan Preas}, title = {An Efficient Algorithm for Local Don't Care Sets Calculation}, booktitle = {Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995}, pages = {663--667}, publisher = {{ACM} Press}, year = {1995}, url = {https://doi.org/10.1145/217474.217607}, doi = {10.1145/217474.217607}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/ChangMC95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/LinLMC95, author = {Chih{-}Chang Lin and Mike Tien{-}Chien Lee and Malgorzata Marek{-}Sadowska and Kuang{-}Chien Chen}, editor = {Richard L. Rudell}, title = {Cost-free scan: a low-overhead scan path design methodology}, booktitle = {Proceedings of the 1995 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 1995, San Jose, California, USA, November 5-9, 1995}, pages = {528--533}, publisher = {{IEEE} Computer Society / {ACM}}, year = {1995}, url = {https://doi.org/10.1109/ICCAD.1995.480167}, doi = {10.1109/ICCAD.1995.480167}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/LinLMC95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChengLM95, author = {David Ihsin Cheng and Chih{-}Chang Lin and Malgorzata Marek{-}Sadowska}, editor = {Richard L. Rudell}, title = {Circuit partitioning with logic perturbation}, booktitle = {Proceedings of the 1995 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 1995, San Jose, California, USA, November 5-9, 1995}, pages = {650--655}, publisher = {{IEEE} Computer Society / {ACM}}, year = {1995}, url = {https://doi.org/10.1109/ICCAD.1995.480198}, doi = {10.1109/ICCAD.1995.480198}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/ChengLM95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jcsc/ChengM94, author = {David Ihsin Cheng and Malgorzata Marek{-}Sadowska}, title = {On the Verification of Function Equivalence with unknown Input Correspondence}, journal = {J. Circuits Syst. Comput.}, volume = {4}, number = {2}, pages = {223--242}, year = {1994}, url = {https://doi.org/10.1142/S0218126694000132}, doi = {10.1142/S0218126694000132}, timestamp = {Tue, 25 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jcsc/ChengM94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ChangCWM94, author = {Shih{-}Chieh Chang and Kwang{-}Ting Cheng and Nam Sung Woo and Malgorzata Marek{-}Sadowska}, editor = {Michael J. Lorenzetti}, title = {Layout Driven Logic Synthesis for FPGAs}, booktitle = {Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994}, pages = {308--313}, publisher = {{ACM} Press}, year = {1994}, url = {https://doi.org/10.1145/196244.196388}, doi = {10.1145/196244.196388}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/ChangCWM94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/TsaiM94, author = {Chien{-}Chung Tsai and Malgorzata Marek{-}Sadowska}, editor = {Michael J. Lorenzetti}, title = {Boolean Matching Using Generalized Reed-Muller Forms}, booktitle = {Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994}, pages = {339--344}, publisher = {{ACM} Press}, year = {1994}, url = {https://doi.org/10.1145/196244.196404}, doi = {10.1145/196244.196404}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/TsaiM94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/VittalM94, author = {Ashok Vittal and Malgorzata Marek{-}Sadowska}, editor = {Michael J. Lorenzetti}, title = {Minimal Delay Interconnect Design Using Alphabetic Trees}, booktitle = {Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994}, pages = {392--396}, publisher = {{ACM} Press}, year = {1994}, url = {https://doi.org/10.1145/196244.196432}, doi = {10.1145/196244.196432}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/VittalM94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/eurodac/WuM94, author = {Yu{-}Liang Wu and Malgorzata Marek{-}Sadowska}, editor = {Robert Werner}, title = {An Efficient Router for 2-D Field Programmable Gate Arrays}, booktitle = {{EDAC} - The European Conference on Design Automation, {ETC} - European Test Conference, {EUROASIC} - The European Event in {ASIC} Design, Proceedings, February 28 - March 3, 1994, Paris, France}, pages = {412--416}, publisher = {{IEEE} Computer Society}, year = {1994}, url = {https://doi.org/10.1109/EDTC.1994.326843}, doi = {10.1109/EDTC.1994.326843}, timestamp = {Wed, 16 Oct 2019 14:14:54 +0200}, biburl = {https://dblp.org/rec/conf/eurodac/WuM94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/eurodac/ChangCM94, author = {Shih{-}Chieh Chang and David Ihsin Cheng and Malgorzata Marek{-}Sadowska}, editor = {Robert Werner}, title = {Minimizing {ROBDD} Size of Incompletely Specified Multiple Output Functions}, booktitle = {{EDAC} - The European Conference on Design Automation, {ETC} - European Test Conference, {EUROASIC} - The European Event in {ASIC} Design, Proceedings, February 28 - March 3, 1994, Paris, France}, pages = {620--624}, publisher = {{IEEE} Computer Society}, year = {1994}, url = {https://doi.org/10.1109/EDTC.1994.326921}, doi = {10.1109/EDTC.1994.326921}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/eurodac/ChangCM94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/WuTM94, author = {Yu{-}Liang Wu and Shuji Tsukiyama and Malgorzata Marek{-}Sadowska}, title = {On computational complexity of a detailed routing problem in two dimensional FPGAs}, booktitle = {Fourth Great Lakes Symposium on Design Automation of High Performance {VLSI} Systems, {GLSV} '94, Notre Dame, IN, USA, March 4-5, 1994}, pages = {70--75}, publisher = {{IEEE}}, year = {1994}, url = {https://doi.org/10.1109/GLSV.1994.289993}, doi = {10.1109/GLSV.1994.289993}, timestamp = {Wed, 16 Oct 2019 14:14:57 +0200}, biburl = {https://dblp.org/rec/conf/glvlsi/WuTM94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChangM94, author = {Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska}, editor = {Jochen A. G. Jess and Richard L. Rudell}, title = {Perturb and simplify: multi-level boolean network optimizer}, booktitle = {Proceedings of the 1994 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 1994, San Jose, California, USA, November 6-10, 1994}, pages = {2--5}, publisher = {{IEEE} Computer Society / {ACM}}, year = {1994}, url = {https://doi.org/10.1109/ICCAD.1994.629734}, doi = {10.1109/ICCAD.1994.629734}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/ChangM94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/LinMG94, author = {Chih{-}Chang Lin and Malgorzata Marek{-}Sadowska and Duane Gatlin}, editor = {Jochen A. G. Jess and Richard L. Rudell}, title = {Universal logic gate for {FPGA} design}, booktitle = {Proceedings of the 1994 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 1994, San Jose, California, USA, November 6-10, 1994}, pages = {164--168}, publisher = {{IEEE} Computer Society / {ACM}}, year = {1994}, url = {https://doi.org/10.1109/ICCAD.1994.629760}, doi = {10.1109/ICCAD.1994.629760}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/LinMG94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/TsaiM94, author = {Chien{-}Chung Tsai and Malgorzata Marek{-}Sadowska}, title = {Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms}, booktitle = {1994 {IEEE} International Symposium on Circuits and Systems, {ISCAS} 1994, London, England, UK, May 30 - June 2, 1994}, pages = {287--290}, publisher = {{IEEE}}, year = {1994}, url = {https://doi.org/10.1109/ISCAS.1994.408811}, doi = {10.1109/ISCAS.1994.408811}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/TsaiM94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LinKM93, author = {Shen Lin and Ernest S. Kuh and Malgorzata Marek{-}Sadowska}, title = {Stepwise equivalent conductance circuit simulation technique}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {12}, number = {5}, pages = {672--683}, year = {1993}, url = {https://doi.org/10.1109/43.277612}, doi = {10.1109/43.277612}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LinKM93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/eurodac/WuM93, author = {Yu{-}Liang Wu and Malgorzata Marek{-}Sadowska}, title = {Graph based analysis of {FPGA} routing}, booktitle = {Proceedings of the European Design Automation Conference 1993, {EURO-DAC} '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993}, pages = {104--109}, publisher = {{IEEE} Computer Society}, year = {1993}, url = {https://doi.org/10.1109/EURDAC.1993.410623}, doi = {10.1109/EURDAC.1993.410623}, timestamp = {Wed, 16 Oct 2019 14:14:54 +0200}, biburl = {https://dblp.org/rec/conf/eurodac/WuM93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/TsaiM93, author = {Chien{-}Chung Tsai and Malgorzata Marek{-}Sadowska}, title = {Efficient minimization algorithms for fixed polarity {AND/XOR} canonical networks}, booktitle = {Third Great Lakes Symposium on Design Automation of High Performance {VLSI} Systems, Kalamazoo, MI, USA, March 5-6, 1993}, pages = {76--79}, publisher = {{IEEE}}, year = {1993}, url = {https://doi.org/10.1109/GLSV.1993.224476}, doi = {10.1109/GLSV.1993.224476}, timestamp = {Wed, 16 Oct 2019 14:14:57 +0200}, biburl = {https://dblp.org/rec/conf/glvlsi/TsaiM93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@incollection{DBLP:books/ws/93/Marek-Sadowska93, author = {Malgorzata Marek{-}Sadowska}, editor = {Majid Sarrafzadeh and D. T. Lee}, title = {Issues in Timing Driven Layout}, booktitle = {Algorithmic Aspects of {VLSI} Layout}, series = {Lecture Notes Series on Computing}, volume = {2}, pages = {1--24}, publisher = {World Scientific}, year = {1993}, url = {https://doi.org/10.1142/9789812794468\_0001}, doi = {10.1142/9789812794468\_0001}, timestamp = {Mon, 03 Apr 2023 16:01:56 +0200}, biburl = {https://dblp.org/rec/books/ws/93/Marek-Sadowska93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/Marek-Sadowska92, author = {Malgorzata Marek{-}Sadowska}, title = {Switch box routing: a retrospective}, journal = {Integr.}, volume = {13}, number = {1}, pages = {39--65}, year = {1992}, url = {https://doi.org/10.1016/0167-9260(92)90017-S}, doi = {10.1016/0167-9260(92)90017-S}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/Marek-Sadowska92.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jcsc/DuttaM92, author = {Robi Dutta and Malgorzata Marek{-}Sadowska}, title = {Algorithm for wire sizing of Power and Ground Networks in {VLSI} Designs}, journal = {J. Circuits Syst. Comput.}, volume = {2}, number = {2}, pages = {141--158}, year = {1992}, url = {https://doi.org/10.1142/S0218126692000118}, doi = {10.1142/S0218126692000118}, timestamp = {Tue, 25 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jcsc/DuttaM92.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/ChangM92, author = {Shih{-}Chieh Chang and Malgorzata Marek{-}Sadowska}, title = {Technology Mapping via Transformations of Function Graphs}, booktitle = {Proceedings 1992 {IEEE} International Conference on Computer Design: {VLSI} in Computer {\&} Processors, {ICCD} '92, Cambridge, MA, USA, October 11-14, 1992}, pages = {159--162}, publisher = {{IEEE} Computer Society}, year = {1992}, url = {https://doi.org/10.1109/ICCD.1992.276240}, doi = {10.1109/ICCD.1992.276240}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/ChangM92.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/LinKM92, author = {Shen Lin and Ernest S. Kuh and Malgorzata Marek{-}Sadowska}, title = {A New Accurate and Efficient Timing Simulator}, booktitle = {Proceedings of the Fifth International Conference on {VLSI} Design, {VLSI} Design 1992, Bangalore, India, January 4-7, 1992}, pages = {281--286}, publisher = {{IEEE} Computer Society}, year = {1992}, url = {https://doi.org/10.1109/ICVD.1992.658063}, doi = {10.1109/ICVD.1992.658063}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/LinKM92.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/eurodac/LinMK91, author = {Shen Lin and Malgorzata Marek{-}Sadowska and Ernest S. Kuh}, editor = {Tony Ambler and Jochen A. G. Jess and Hugo De Man}, title = {{SWEC:} a Step Wise Equivalent Conductance timing simulator for {CMOS} {VLSI} circuits}, booktitle = {Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991}, pages = {142--148}, publisher = {{EEE} Computer Society}, year = {1991}, url = {http://dl.acm.org/citation.cfm?id=951545}, timestamp = {Tue, 27 Mar 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/eurodac/LinMK91.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/eurodac/LinM91, author = {Shen Lin and Malgorzata Marek{-}Sadowska}, editor = {Tony Ambler and Jochen A. G. Jess and Hugo De Man}, title = {A fast and efficient algorithm for determining fanout trees in large networks}, booktitle = {Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991}, pages = {539--544}, publisher = {{EEE} Computer Society}, year = {1991}, url = {http://dl.acm.org/citation.cfm?id=951631}, timestamp = {Tue, 27 Mar 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/eurodac/LinM91.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/Marek-SadowskaS91, author = {Malgorzata Marek{-}Sadowska and Majid Sarrafzadeh}, title = {The Crossing Distribution Problem}, booktitle = {1991 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of Technical Papers}, pages = {528--531}, publisher = {{IEEE} Computer Society}, year = {1991}, url = {https://doi.org/10.1109/ICCAD.1991.185323}, doi = {10.1109/ICCAD.1991.185323}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/Marek-SadowskaS91.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LinMK90, author = {Shen Lin and Malgorzata Marek{-}Sadowska and Ernest S. Kuh}, editor = {Richard C. Smith}, title = {Delay and Area Optimization in Standard-Cell Design}, booktitle = {Proceedings of the 27th {ACM/IEEE} Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990}, pages = {349--352}, publisher = {{IEEE} Computer Society Press}, year = {1990}, url = {https://doi.org/10.1145/123186.123301}, doi = {10.1145/123186.123301}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/LinMK90.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/PedramMK90, author = {Massoud Pedram and Malgorzata Marek{-}Sadowska and Ernest S. Kuh}, title = {Floorplanning with Pin Assignment}, booktitle = {{IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers}, pages = {98--101}, publisher = {{IEEE} Computer Society}, year = {1990}, url = {https://doi.org/10.1109/ICCAD.1990.129851}, doi = {10.1109/ICCAD.1990.129851}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/PedramMK90.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/Marek-SadowskaL90, author = {Malgorzata Marek{-}Sadowska and Shen P. Lin}, title = {Pin assignment for improved performance in standard cell design}, booktitle = {Proceedings of the 1990 {IEEE} International Conference on Computer Design: {VLSI} in Computers and Processors, {ICCD} 1990, Cambridge, MA, USA, 17-19 September, 1990}, pages = {339--342}, publisher = {{IEEE} Computer Society}, year = {1990}, url = {https://doi.org/10.1109/ICCD.1990.130244}, doi = {10.1109/ICCD.1990.130244}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/Marek-SadowskaL90.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/DuttaM89, author = {Rajiv Dutta and Malgorzata Marek{-}Sadowska}, editor = {Donald E. Thomas}, title = {Automatic Sizing of Power/Ground {(P/G)} Networks in {VLSI}}, booktitle = {Proceedings of the 26th {ACM/IEEE} Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989}, pages = {783--786}, publisher = {{ACM} Press}, year = {1989}, url = {https://doi.org/10.1145/74382.74529}, doi = {10.1145/74382.74529}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/DuttaM89.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/Marek-SadowskaL89, author = {Malgorzata Marek{-}Sadowska and Shen Lin}, title = {Timing driven placement}, booktitle = {1989 {IEEE} International Conference on Computer-Aided Design, {ICCAD} 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers}, pages = {94--97}, publisher = {{IEEE} Computer Society}, year = {1989}, url = {https://doi.org/10.1109/ICCAD.1989.76912}, doi = {10.1109/ICCAD.1989.76912}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/Marek-SadowskaL89.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccal/MakedonM89, author = {Fillia Makedon and Malgorzata Marek{-}Sadowska}, editor = {Hermann A. Maurer}, title = {Analysis of Heuristic Reasoning for the Visualization of {CAD} Quadratic}, booktitle = {Computer Assisted Learning, 2nd International Conference, {ICCAL} '89, Dallas, Texas, USA, May 9-11, 1989, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {360}, pages = {359--378}, publisher = {Springer}, year = {1989}, url = {https://doi.org/10.1007/3-540-51142-3\_72}, doi = {10.1007/3-540-51142-3\_72}, timestamp = {Tue, 14 May 2019 10:00:52 +0200}, biburl = {https://dblp.org/rec/conf/iccal/MakedonM89.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Marek-Sadowska87, author = {Malgorzata Marek{-}Sadowska}, title = {Pad Assignment for Power Nets in {VLSI} Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {6}, number = {4}, pages = {550--560}, year = {1987}, url = {https://doi.org/10.1109/TCAD.1987.1270302}, doi = {10.1109/TCAD.1987.1270302}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Marek-Sadowska87.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/Marek-Sadowska85, author = {Malgorzata Marek{-}Sadowska}, editor = {Hillel Ofek and Lawrence A. O'Neill}, title = {Two-dimensional router for double layer layout}, booktitle = {Proceedings of the 22nd {ACM/IEEE} conference on Design automation, {DAC} 1985, Las Vegas, Nevada, USA, 1985}, pages = {117--123}, publisher = {{ACM}}, year = {1985}, url = {https://doi.org/10.1145/317825.317844}, doi = {10.1145/317825.317844}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/Marek-Sadowska85.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/TarngMK84, author = {Tom Tsan{-}Kuo Tarng and Malgorzata Marek{-}Sadowska and Ernest S. Kuh}, title = {An Efficient Single-Row Routing Algorithm}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {3}, number = {3}, pages = {178--183}, year = {1984}, url = {https://doi.org/10.1109/TCAD.1984.1270073}, doi = {10.1109/TCAD.1984.1270073}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/TarngMK84.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Marek-Sadowska84, author = {Malgorzata Marek{-}Sadowska}, title = {An Unconstrained Topological Via Minimization Problem for Two-Layer Routing}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {3}, number = {3}, pages = {184--190}, year = {1984}, url = {https://doi.org/10.1109/TCAD.1984.1270074}, doi = {10.1109/TCAD.1984.1270074}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Marek-Sadowska84.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiM84, author = {Jeong{-}Tyng Li and Malgorzata Marek{-}Sadowska}, title = {Global Routing for Gate Array}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {3}, number = {4}, pages = {298--307}, year = {1984}, url = {https://doi.org/10.1109/TCAD.1984.1270088}, doi = {10.1109/TCAD.1984.1270088}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LiM84.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Marek-SadowskaT83, author = {Malgorzata Marek{-}Sadowska and Tom Tsan{-}Kuo Tarng}, title = {Single-Layer Routing for {VLSI:} Analysis and Algorithms}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {2}, number = {4}, pages = {246--259}, year = {1983}, url = {https://doi.org/10.1109/TCAD.1983.1270042}, doi = {10.1109/TCAD.1983.1270042}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Marek-SadowskaT83.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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